linux/drivers/crypto/chelsio/chcr_core.h
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   1/*
   2 * This file is part of the Chelsio T6 Crypto driver for Linux.
   3 *
   4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5 *
   6 * This software is available to you under a choice of one of two
   7 * licenses.  You may choose to be licensed under the terms of the GNU
   8 * General Public License (GPL) Version 2, available from the file
   9 * COPYING in the main directory of this source tree, or the
  10 * OpenIB.org BSD license below:
  11 *
  12 *     Redistribution and use in source and binary forms, with or
  13 *     without modification, are permitted provided that the following
  14 *     conditions are met:
  15 *
  16 *      - Redistributions of source code must retain the above
  17 *        copyright notice, this list of conditions and the following
  18 *        disclaimer.
  19 *
  20 *      - Redistributions in binary form must reproduce the above
  21 *        copyright notice, this list of conditions and the following
  22 *        disclaimer in the documentation and/or other materials
  23 *        provided with the distribution.
  24 *
  25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32 * SOFTWARE.
  33 *
  34 */
  35
  36#ifndef __CHCR_CORE_H__
  37#define __CHCR_CORE_H__
  38
  39#include <crypto/algapi.h>
  40#include <net/tls.h>
  41#include "t4_hw.h"
  42#include "cxgb4.h"
  43#include "t4_msg.h"
  44#include "cxgb4_uld.h"
  45
  46#define DRV_MODULE_NAME "chcr"
  47#define DRV_DESC "Chelsio T6 Crypto Co-processor Driver"
  48
  49#define MAX_PENDING_REQ_TO_HW 20
  50#define CHCR_TEST_RESPONSE_TIMEOUT 1000
  51#define WQ_DETACH_TM    (msecs_to_jiffies(50))
  52#define PAD_ERROR_BIT           1
  53#define CHK_PAD_ERR_BIT(x)      (((x) >> PAD_ERROR_BIT) & 1)
  54
  55#define MAC_ERROR_BIT           0
  56#define CHK_MAC_ERR_BIT(x)      (((x) >> MAC_ERROR_BIT) & 1)
  57#define MAX_SALT                4
  58#define CIP_WR_MIN_LEN (sizeof(struct chcr_wr) + \
  59                    sizeof(struct cpl_rx_phys_dsgl) + \
  60                    sizeof(struct ulptx_sgl) + 16) //IV
  61
  62#define HASH_WR_MIN_LEN (sizeof(struct chcr_wr) + \
  63                        DUMMY_BYTES + \
  64                    sizeof(struct ulptx_sgl))
  65struct uld_ctx;
  66
  67struct _key_ctx {
  68        __be32 ctx_hdr;
  69        u8 salt[MAX_SALT];
  70        __be64 iv_to_auth;
  71        unsigned char key[];
  72};
  73
  74#define WQ_RETRY        5
  75struct chcr_driver_data {
  76        struct list_head act_dev;
  77        struct list_head inact_dev;
  78        atomic_t dev_count;
  79        struct mutex drv_mutex;
  80        struct uld_ctx *last_dev;
  81};
  82
  83enum chcr_state {
  84        CHCR_INIT = 0,
  85        CHCR_ATTACH,
  86        CHCR_DETACH,
  87};
  88struct chcr_wr {
  89        struct fw_crypto_lookaside_wr wreq;
  90        struct ulp_txpkt ulptx;
  91        struct ulptx_idata sc_imm;
  92        struct cpl_tx_sec_pdu sec_cpl;
  93        struct _key_ctx key_ctx;
  94};
  95
  96struct chcr_dev {
  97        spinlock_t lock_chcr_dev;
  98        enum chcr_state state;
  99        atomic_t inflight;
 100        int wqretry;
 101        struct delayed_work detach_work;
 102        struct completion detach_comp;
 103};
 104
 105struct uld_ctx {
 106        struct list_head entry;
 107        struct cxgb4_lld_info lldi;
 108        struct chcr_dev dev;
 109};
 110
 111/*
 112 *      sgl_len - calculates the size of an SGL of the given capacity
 113 *      @n: the number of SGL entries
 114 *      Calculates the number of flits needed for a scatter/gather list that
 115 *      can hold the given number of entries.
 116 */
 117static inline unsigned int sgl_len(unsigned int n)
 118{
 119        n--;
 120        return (3 * n) / 2 + (n & 1) + 2;
 121}
 122
 123static inline void *padap(struct chcr_dev *dev)
 124{
 125        struct uld_ctx *u_ctx = container_of(dev, struct uld_ctx, dev);
 126
 127        return pci_get_drvdata(u_ctx->lldi.pdev);
 128}
 129
 130struct uld_ctx *assign_chcr_device(void);
 131int chcr_send_wr(struct sk_buff *skb);
 132int start_crypto(void);
 133int stop_crypto(void);
 134int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
 135                        const struct pkt_gl *pgl);
 136int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev);
 137int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
 138                     int err);
 139#endif /* __CHCR_CORE_H__ */
 140