linux/drivers/clocksource/arm_arch_timer.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  linux/drivers/clocksource/arm_arch_timer.c
   4 *
   5 *  Copyright (C) 2011 ARM Ltd.
   6 *  All Rights Reserved
   7 */
   8
   9#define pr_fmt(fmt)     "arch_timer: " fmt
  10
  11#include <linux/init.h>
  12#include <linux/kernel.h>
  13#include <linux/device.h>
  14#include <linux/smp.h>
  15#include <linux/cpu.h>
  16#include <linux/cpu_pm.h>
  17#include <linux/clockchips.h>
  18#include <linux/clocksource.h>
  19#include <linux/clocksource_ids.h>
  20#include <linux/interrupt.h>
  21#include <linux/of_irq.h>
  22#include <linux/of_address.h>
  23#include <linux/io.h>
  24#include <linux/slab.h>
  25#include <linux/sched/clock.h>
  26#include <linux/sched_clock.h>
  27#include <linux/acpi.h>
  28#include <linux/arm-smccc.h>
  29#include <linux/ptp_kvm.h>
  30
  31#include <asm/arch_timer.h>
  32#include <asm/virt.h>
  33
  34#include <clocksource/arm_arch_timer.h>
  35
  36#define CNTTIDR         0x08
  37#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
  38
  39#define CNTACR(n)       (0x40 + ((n) * 4))
  40#define CNTACR_RPCT     BIT(0)
  41#define CNTACR_RVCT     BIT(1)
  42#define CNTACR_RFRQ     BIT(2)
  43#define CNTACR_RVOFF    BIT(3)
  44#define CNTACR_RWVT     BIT(4)
  45#define CNTACR_RWPT     BIT(5)
  46
  47#define CNTVCT_LO       0x08
  48#define CNTVCT_HI       0x0c
  49#define CNTFRQ          0x10
  50#define CNTP_TVAL       0x28
  51#define CNTP_CTL        0x2c
  52#define CNTV_TVAL       0x38
  53#define CNTV_CTL        0x3c
  54
  55static unsigned arch_timers_present __initdata;
  56
  57static void __iomem *arch_counter_base __ro_after_init;
  58
  59struct arch_timer {
  60        void __iomem *base;
  61        struct clock_event_device evt;
  62};
  63
  64#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
  65
  66static u32 arch_timer_rate __ro_after_init;
  67u32 arch_timer_rate1 __ro_after_init;
  68static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init;
  69
  70static const char *arch_timer_ppi_names[ARCH_TIMER_MAX_TIMER_PPI] = {
  71        [ARCH_TIMER_PHYS_SECURE_PPI]    = "sec-phys",
  72        [ARCH_TIMER_PHYS_NONSECURE_PPI] = "phys",
  73        [ARCH_TIMER_VIRT_PPI]           = "virt",
  74        [ARCH_TIMER_HYP_PPI]            = "hyp-phys",
  75        [ARCH_TIMER_HYP_VIRT_PPI]       = "hyp-virt",
  76};
  77
  78static struct clock_event_device __percpu *arch_timer_evt;
  79
  80static enum arch_timer_ppi_nr arch_timer_uses_ppi __ro_after_init = ARCH_TIMER_VIRT_PPI;
  81static bool arch_timer_c3stop __ro_after_init;
  82static bool arch_timer_mem_use_virtual __ro_after_init;
  83static bool arch_counter_suspend_stop __ro_after_init;
  84#ifdef CONFIG_GENERIC_GETTIMEOFDAY
  85static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
  86#else
  87static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE;
  88#endif /* CONFIG_GENERIC_GETTIMEOFDAY */
  89
  90static cpumask_t evtstrm_available = CPU_MASK_NONE;
  91static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
  92
  93static int __init early_evtstrm_cfg(char *buf)
  94{
  95        return strtobool(buf, &evtstrm_enable);
  96}
  97early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
  98
  99/*
 100 * Architected system timer support.
 101 */
 102
 103static __always_inline
 104void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
 105                          struct clock_event_device *clk)
 106{
 107        if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 108                struct arch_timer *timer = to_arch_timer(clk);
 109                switch (reg) {
 110                case ARCH_TIMER_REG_CTRL:
 111                        writel_relaxed(val, timer->base + CNTP_CTL);
 112                        break;
 113                case ARCH_TIMER_REG_TVAL:
 114                        writel_relaxed(val, timer->base + CNTP_TVAL);
 115                        break;
 116                }
 117        } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 118                struct arch_timer *timer = to_arch_timer(clk);
 119                switch (reg) {
 120                case ARCH_TIMER_REG_CTRL:
 121                        writel_relaxed(val, timer->base + CNTV_CTL);
 122                        break;
 123                case ARCH_TIMER_REG_TVAL:
 124                        writel_relaxed(val, timer->base + CNTV_TVAL);
 125                        break;
 126                }
 127        } else {
 128                arch_timer_reg_write_cp15(access, reg, val);
 129        }
 130}
 131
 132static __always_inline
 133u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
 134                        struct clock_event_device *clk)
 135{
 136        u32 val;
 137
 138        if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 139                struct arch_timer *timer = to_arch_timer(clk);
 140                switch (reg) {
 141                case ARCH_TIMER_REG_CTRL:
 142                        val = readl_relaxed(timer->base + CNTP_CTL);
 143                        break;
 144                case ARCH_TIMER_REG_TVAL:
 145                        val = readl_relaxed(timer->base + CNTP_TVAL);
 146                        break;
 147                }
 148        } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 149                struct arch_timer *timer = to_arch_timer(clk);
 150                switch (reg) {
 151                case ARCH_TIMER_REG_CTRL:
 152                        val = readl_relaxed(timer->base + CNTV_CTL);
 153                        break;
 154                case ARCH_TIMER_REG_TVAL:
 155                        val = readl_relaxed(timer->base + CNTV_TVAL);
 156                        break;
 157                }
 158        } else {
 159                val = arch_timer_reg_read_cp15(access, reg);
 160        }
 161
 162        return val;
 163}
 164
 165static notrace u64 arch_counter_get_cntpct_stable(void)
 166{
 167        return __arch_counter_get_cntpct_stable();
 168}
 169
 170static notrace u64 arch_counter_get_cntpct(void)
 171{
 172        return __arch_counter_get_cntpct();
 173}
 174
 175static notrace u64 arch_counter_get_cntvct_stable(void)
 176{
 177        return __arch_counter_get_cntvct_stable();
 178}
 179
 180static notrace u64 arch_counter_get_cntvct(void)
 181{
 182        return __arch_counter_get_cntvct();
 183}
 184
 185/*
 186 * Default to cp15 based access because arm64 uses this function for
 187 * sched_clock() before DT is probed and the cp15 method is guaranteed
 188 * to exist on arm64. arm doesn't use this before DT is probed so even
 189 * if we don't have the cp15 accessors we won't have a problem.
 190 */
 191u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct;
 192EXPORT_SYMBOL_GPL(arch_timer_read_counter);
 193
 194static u64 arch_counter_read(struct clocksource *cs)
 195{
 196        return arch_timer_read_counter();
 197}
 198
 199static u64 arch_counter_read_cc(const struct cyclecounter *cc)
 200{
 201        return arch_timer_read_counter();
 202}
 203
 204static struct clocksource clocksource_counter = {
 205        .name   = "arch_sys_counter",
 206        .id     = CSID_ARM_ARCH_COUNTER,
 207        .rating = 400,
 208        .read   = arch_counter_read,
 209        .mask   = CLOCKSOURCE_MASK(56),
 210        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 211};
 212
 213static struct cyclecounter cyclecounter __ro_after_init = {
 214        .read   = arch_counter_read_cc,
 215        .mask   = CLOCKSOURCE_MASK(56),
 216};
 217
 218struct ate_acpi_oem_info {
 219        char oem_id[ACPI_OEM_ID_SIZE + 1];
 220        char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
 221        u32 oem_revision;
 222};
 223
 224#ifdef CONFIG_FSL_ERRATUM_A008585
 225/*
 226 * The number of retries is an arbitrary value well beyond the highest number
 227 * of iterations the loop has been observed to take.
 228 */
 229#define __fsl_a008585_read_reg(reg) ({                  \
 230        u64 _old, _new;                                 \
 231        int _retries = 200;                             \
 232                                                        \
 233        do {                                            \
 234                _old = read_sysreg(reg);                \
 235                _new = read_sysreg(reg);                \
 236                _retries--;                             \
 237        } while (unlikely(_old != _new) && _retries);   \
 238                                                        \
 239        WARN_ON_ONCE(!_retries);                        \
 240        _new;                                           \
 241})
 242
 243static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
 244{
 245        return __fsl_a008585_read_reg(cntp_tval_el0);
 246}
 247
 248static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
 249{
 250        return __fsl_a008585_read_reg(cntv_tval_el0);
 251}
 252
 253static u64 notrace fsl_a008585_read_cntpct_el0(void)
 254{
 255        return __fsl_a008585_read_reg(cntpct_el0);
 256}
 257
 258static u64 notrace fsl_a008585_read_cntvct_el0(void)
 259{
 260        return __fsl_a008585_read_reg(cntvct_el0);
 261}
 262#endif
 263
 264#ifdef CONFIG_HISILICON_ERRATUM_161010101
 265/*
 266 * Verify whether the value of the second read is larger than the first by
 267 * less than 32 is the only way to confirm the value is correct, so clear the
 268 * lower 5 bits to check whether the difference is greater than 32 or not.
 269 * Theoretically the erratum should not occur more than twice in succession
 270 * when reading the system counter, but it is possible that some interrupts
 271 * may lead to more than twice read errors, triggering the warning, so setting
 272 * the number of retries far beyond the number of iterations the loop has been
 273 * observed to take.
 274 */
 275#define __hisi_161010101_read_reg(reg) ({                               \
 276        u64 _old, _new;                                         \
 277        int _retries = 50;                                      \
 278                                                                \
 279        do {                                                    \
 280                _old = read_sysreg(reg);                        \
 281                _new = read_sysreg(reg);                        \
 282                _retries--;                                     \
 283        } while (unlikely((_new - _old) >> 5) && _retries);     \
 284                                                                \
 285        WARN_ON_ONCE(!_retries);                                \
 286        _new;                                                   \
 287})
 288
 289static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
 290{
 291        return __hisi_161010101_read_reg(cntp_tval_el0);
 292}
 293
 294static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
 295{
 296        return __hisi_161010101_read_reg(cntv_tval_el0);
 297}
 298
 299static u64 notrace hisi_161010101_read_cntpct_el0(void)
 300{
 301        return __hisi_161010101_read_reg(cntpct_el0);
 302}
 303
 304static u64 notrace hisi_161010101_read_cntvct_el0(void)
 305{
 306        return __hisi_161010101_read_reg(cntvct_el0);
 307}
 308
 309static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
 310        /*
 311         * Note that trailing spaces are required to properly match
 312         * the OEM table information.
 313         */
 314        {
 315                .oem_id         = "HISI  ",
 316                .oem_table_id   = "HIP05   ",
 317                .oem_revision   = 0,
 318        },
 319        {
 320                .oem_id         = "HISI  ",
 321                .oem_table_id   = "HIP06   ",
 322                .oem_revision   = 0,
 323        },
 324        {
 325                .oem_id         = "HISI  ",
 326                .oem_table_id   = "HIP07   ",
 327                .oem_revision   = 0,
 328        },
 329        { /* Sentinel indicating the end of the OEM array */ },
 330};
 331#endif
 332
 333#ifdef CONFIG_ARM64_ERRATUM_858921
 334static u64 notrace arm64_858921_read_cntpct_el0(void)
 335{
 336        u64 old, new;
 337
 338        old = read_sysreg(cntpct_el0);
 339        new = read_sysreg(cntpct_el0);
 340        return (((old ^ new) >> 32) & 1) ? old : new;
 341}
 342
 343static u64 notrace arm64_858921_read_cntvct_el0(void)
 344{
 345        u64 old, new;
 346
 347        old = read_sysreg(cntvct_el0);
 348        new = read_sysreg(cntvct_el0);
 349        return (((old ^ new) >> 32) & 1) ? old : new;
 350}
 351#endif
 352
 353#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
 354/*
 355 * The low bits of the counter registers are indeterminate while bit 10 or
 356 * greater is rolling over. Since the counter value can jump both backward
 357 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
 358 * with all ones or all zeros in the low bits. Bound the loop by the maximum
 359 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
 360 */
 361#define __sun50i_a64_read_reg(reg) ({                                   \
 362        u64 _val;                                                       \
 363        int _retries = 150;                                             \
 364                                                                        \
 365        do {                                                            \
 366                _val = read_sysreg(reg);                                \
 367                _retries--;                                             \
 368        } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries);        \
 369                                                                        \
 370        WARN_ON_ONCE(!_retries);                                        \
 371        _val;                                                           \
 372})
 373
 374static u64 notrace sun50i_a64_read_cntpct_el0(void)
 375{
 376        return __sun50i_a64_read_reg(cntpct_el0);
 377}
 378
 379static u64 notrace sun50i_a64_read_cntvct_el0(void)
 380{
 381        return __sun50i_a64_read_reg(cntvct_el0);
 382}
 383
 384static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
 385{
 386        return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
 387}
 388
 389static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
 390{
 391        return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
 392}
 393#endif
 394
 395#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 396DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
 397EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
 398
 399static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
 400
 401static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
 402                                                struct clock_event_device *clk)
 403{
 404        unsigned long ctrl;
 405        u64 cval;
 406
 407        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 408        ctrl |= ARCH_TIMER_CTRL_ENABLE;
 409        ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 410
 411        if (access == ARCH_TIMER_PHYS_ACCESS) {
 412                cval = evt + arch_counter_get_cntpct_stable();
 413                write_sysreg(cval, cntp_cval_el0);
 414        } else {
 415                cval = evt + arch_counter_get_cntvct_stable();
 416                write_sysreg(cval, cntv_cval_el0);
 417        }
 418
 419        arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 420}
 421
 422static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
 423                                            struct clock_event_device *clk)
 424{
 425        erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 426        return 0;
 427}
 428
 429static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
 430                                            struct clock_event_device *clk)
 431{
 432        erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 433        return 0;
 434}
 435
 436static const struct arch_timer_erratum_workaround ool_workarounds[] = {
 437#ifdef CONFIG_FSL_ERRATUM_A008585
 438        {
 439                .match_type = ate_match_dt,
 440                .id = "fsl,erratum-a008585",
 441                .desc = "Freescale erratum a005858",
 442                .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
 443                .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
 444                .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
 445                .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
 446                .set_next_event_phys = erratum_set_next_event_tval_phys,
 447                .set_next_event_virt = erratum_set_next_event_tval_virt,
 448        },
 449#endif
 450#ifdef CONFIG_HISILICON_ERRATUM_161010101
 451        {
 452                .match_type = ate_match_dt,
 453                .id = "hisilicon,erratum-161010101",
 454                .desc = "HiSilicon erratum 161010101",
 455                .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
 456                .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
 457                .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
 458                .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
 459                .set_next_event_phys = erratum_set_next_event_tval_phys,
 460                .set_next_event_virt = erratum_set_next_event_tval_virt,
 461        },
 462        {
 463                .match_type = ate_match_acpi_oem_info,
 464                .id = hisi_161010101_oem_info,
 465                .desc = "HiSilicon erratum 161010101",
 466                .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
 467                .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
 468                .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
 469                .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
 470                .set_next_event_phys = erratum_set_next_event_tval_phys,
 471                .set_next_event_virt = erratum_set_next_event_tval_virt,
 472        },
 473#endif
 474#ifdef CONFIG_ARM64_ERRATUM_858921
 475        {
 476                .match_type = ate_match_local_cap_id,
 477                .id = (void *)ARM64_WORKAROUND_858921,
 478                .desc = "ARM erratum 858921",
 479                .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
 480                .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
 481        },
 482#endif
 483#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
 484        {
 485                .match_type = ate_match_dt,
 486                .id = "allwinner,erratum-unknown1",
 487                .desc = "Allwinner erratum UNKNOWN1",
 488                .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
 489                .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
 490                .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
 491                .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
 492                .set_next_event_phys = erratum_set_next_event_tval_phys,
 493                .set_next_event_virt = erratum_set_next_event_tval_virt,
 494        },
 495#endif
 496#ifdef CONFIG_ARM64_ERRATUM_1418040
 497        {
 498                .match_type = ate_match_local_cap_id,
 499                .id = (void *)ARM64_WORKAROUND_1418040,
 500                .desc = "ARM erratum 1418040",
 501                .disable_compat_vdso = true,
 502        },
 503#endif
 504};
 505
 506typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
 507                               const void *);
 508
 509static
 510bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
 511                                 const void *arg)
 512{
 513        const struct device_node *np = arg;
 514
 515        return of_property_read_bool(np, wa->id);
 516}
 517
 518static
 519bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
 520                                        const void *arg)
 521{
 522        return this_cpu_has_cap((uintptr_t)wa->id);
 523}
 524
 525
 526static
 527bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
 528                                       const void *arg)
 529{
 530        static const struct ate_acpi_oem_info empty_oem_info = {};
 531        const struct ate_acpi_oem_info *info = wa->id;
 532        const struct acpi_table_header *table = arg;
 533
 534        /* Iterate over the ACPI OEM info array, looking for a match */
 535        while (memcmp(info, &empty_oem_info, sizeof(*info))) {
 536                if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
 537                    !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
 538                    info->oem_revision == table->oem_revision)
 539                        return true;
 540
 541                info++;
 542        }
 543
 544        return false;
 545}
 546
 547static const struct arch_timer_erratum_workaround *
 548arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
 549                          ate_match_fn_t match_fn,
 550                          void *arg)
 551{
 552        int i;
 553
 554        for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
 555                if (ool_workarounds[i].match_type != type)
 556                        continue;
 557
 558                if (match_fn(&ool_workarounds[i], arg))
 559                        return &ool_workarounds[i];
 560        }
 561
 562        return NULL;
 563}
 564
 565static
 566void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
 567                                  bool local)
 568{
 569        int i;
 570
 571        if (local) {
 572                __this_cpu_write(timer_unstable_counter_workaround, wa);
 573        } else {
 574                for_each_possible_cpu(i)
 575                        per_cpu(timer_unstable_counter_workaround, i) = wa;
 576        }
 577
 578        if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
 579                atomic_set(&timer_unstable_counter_workaround_in_use, 1);
 580
 581        /*
 582         * Don't use the vdso fastpath if errata require using the
 583         * out-of-line counter accessor. We may change our mind pretty
 584         * late in the game (with a per-CPU erratum, for example), so
 585         * change both the default value and the vdso itself.
 586         */
 587        if (wa->read_cntvct_el0) {
 588                clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
 589                vdso_default = VDSO_CLOCKMODE_NONE;
 590        } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
 591                vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
 592                clocksource_counter.vdso_clock_mode = vdso_default;
 593        }
 594}
 595
 596static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
 597                                            void *arg)
 598{
 599        const struct arch_timer_erratum_workaround *wa, *__wa;
 600        ate_match_fn_t match_fn = NULL;
 601        bool local = false;
 602
 603        switch (type) {
 604        case ate_match_dt:
 605                match_fn = arch_timer_check_dt_erratum;
 606                break;
 607        case ate_match_local_cap_id:
 608                match_fn = arch_timer_check_local_cap_erratum;
 609                local = true;
 610                break;
 611        case ate_match_acpi_oem_info:
 612                match_fn = arch_timer_check_acpi_oem_erratum;
 613                break;
 614        default:
 615                WARN_ON(1);
 616                return;
 617        }
 618
 619        wa = arch_timer_iterate_errata(type, match_fn, arg);
 620        if (!wa)
 621                return;
 622
 623        __wa = __this_cpu_read(timer_unstable_counter_workaround);
 624        if (__wa && wa != __wa)
 625                pr_warn("Can't enable workaround for %s (clashes with %s\n)",
 626                        wa->desc, __wa->desc);
 627
 628        if (__wa)
 629                return;
 630
 631        arch_timer_enable_workaround(wa, local);
 632        pr_info("Enabling %s workaround for %s\n",
 633                local ? "local" : "global", wa->desc);
 634}
 635
 636static bool arch_timer_this_cpu_has_cntvct_wa(void)
 637{
 638        return has_erratum_handler(read_cntvct_el0);
 639}
 640
 641static bool arch_timer_counter_has_wa(void)
 642{
 643        return atomic_read(&timer_unstable_counter_workaround_in_use);
 644}
 645#else
 646#define arch_timer_check_ool_workaround(t,a)            do { } while(0)
 647#define arch_timer_this_cpu_has_cntvct_wa()             ({false;})
 648#define arch_timer_counter_has_wa()                     ({false;})
 649#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
 650
 651static __always_inline irqreturn_t timer_handler(const int access,
 652                                        struct clock_event_device *evt)
 653{
 654        unsigned long ctrl;
 655
 656        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
 657        if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
 658                ctrl |= ARCH_TIMER_CTRL_IT_MASK;
 659                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
 660                evt->event_handler(evt);
 661                return IRQ_HANDLED;
 662        }
 663
 664        return IRQ_NONE;
 665}
 666
 667static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 668{
 669        struct clock_event_device *evt = dev_id;
 670
 671        return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
 672}
 673
 674static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 675{
 676        struct clock_event_device *evt = dev_id;
 677
 678        return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
 679}
 680
 681static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
 682{
 683        struct clock_event_device *evt = dev_id;
 684
 685        return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
 686}
 687
 688static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
 689{
 690        struct clock_event_device *evt = dev_id;
 691
 692        return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
 693}
 694
 695static __always_inline int timer_shutdown(const int access,
 696                                          struct clock_event_device *clk)
 697{
 698        unsigned long ctrl;
 699
 700        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 701        ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
 702        arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 703
 704        return 0;
 705}
 706
 707static int arch_timer_shutdown_virt(struct clock_event_device *clk)
 708{
 709        return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
 710}
 711
 712static int arch_timer_shutdown_phys(struct clock_event_device *clk)
 713{
 714        return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
 715}
 716
 717static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
 718{
 719        return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
 720}
 721
 722static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
 723{
 724        return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
 725}
 726
 727static __always_inline void set_next_event(const int access, unsigned long evt,
 728                                           struct clock_event_device *clk)
 729{
 730        unsigned long ctrl;
 731        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 732        ctrl |= ARCH_TIMER_CTRL_ENABLE;
 733        ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 734        arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
 735        arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 736}
 737
 738static int arch_timer_set_next_event_virt(unsigned long evt,
 739                                          struct clock_event_device *clk)
 740{
 741        set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 742        return 0;
 743}
 744
 745static int arch_timer_set_next_event_phys(unsigned long evt,
 746                                          struct clock_event_device *clk)
 747{
 748        set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 749        return 0;
 750}
 751
 752static int arch_timer_set_next_event_virt_mem(unsigned long evt,
 753                                              struct clock_event_device *clk)
 754{
 755        set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
 756        return 0;
 757}
 758
 759static int arch_timer_set_next_event_phys_mem(unsigned long evt,
 760                                              struct clock_event_device *clk)
 761{
 762        set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
 763        return 0;
 764}
 765
 766static void __arch_timer_setup(unsigned type,
 767                               struct clock_event_device *clk)
 768{
 769        clk->features = CLOCK_EVT_FEAT_ONESHOT;
 770
 771        if (type == ARCH_TIMER_TYPE_CP15) {
 772                typeof(clk->set_next_event) sne;
 773
 774                arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
 775
 776                if (arch_timer_c3stop)
 777                        clk->features |= CLOCK_EVT_FEAT_C3STOP;
 778                clk->name = "arch_sys_timer";
 779                clk->rating = 450;
 780                clk->cpumask = cpumask_of(smp_processor_id());
 781                clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
 782                switch (arch_timer_uses_ppi) {
 783                case ARCH_TIMER_VIRT_PPI:
 784                        clk->set_state_shutdown = arch_timer_shutdown_virt;
 785                        clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
 786                        sne = erratum_handler(set_next_event_virt);
 787                        break;
 788                case ARCH_TIMER_PHYS_SECURE_PPI:
 789                case ARCH_TIMER_PHYS_NONSECURE_PPI:
 790                case ARCH_TIMER_HYP_PPI:
 791                        clk->set_state_shutdown = arch_timer_shutdown_phys;
 792                        clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
 793                        sne = erratum_handler(set_next_event_phys);
 794                        break;
 795                default:
 796                        BUG();
 797                }
 798
 799                clk->set_next_event = sne;
 800        } else {
 801                clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
 802                clk->name = "arch_mem_timer";
 803                clk->rating = 400;
 804                clk->cpumask = cpu_possible_mask;
 805                if (arch_timer_mem_use_virtual) {
 806                        clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
 807                        clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
 808                        clk->set_next_event =
 809                                arch_timer_set_next_event_virt_mem;
 810                } else {
 811                        clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
 812                        clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
 813                        clk->set_next_event =
 814                                arch_timer_set_next_event_phys_mem;
 815                }
 816        }
 817
 818        clk->set_state_shutdown(clk);
 819
 820        clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
 821}
 822
 823static void arch_timer_evtstrm_enable(int divider)
 824{
 825        u32 cntkctl = arch_timer_get_cntkctl();
 826
 827        cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
 828        /* Set the divider and enable virtual event stream */
 829        cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
 830                        | ARCH_TIMER_VIRT_EVT_EN;
 831        arch_timer_set_cntkctl(cntkctl);
 832        arch_timer_set_evtstrm_feature();
 833        cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
 834}
 835
 836static void arch_timer_configure_evtstream(void)
 837{
 838        int evt_stream_div, lsb;
 839
 840        /*
 841         * As the event stream can at most be generated at half the frequency
 842         * of the counter, use half the frequency when computing the divider.
 843         */
 844        evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
 845
 846        /*
 847         * Find the closest power of two to the divisor. If the adjacent bit
 848         * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
 849         */
 850        lsb = fls(evt_stream_div) - 1;
 851        if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
 852                lsb++;
 853
 854        /* enable event stream */
 855        arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
 856}
 857
 858static void arch_counter_set_user_access(void)
 859{
 860        u32 cntkctl = arch_timer_get_cntkctl();
 861
 862        /* Disable user access to the timers and both counters */
 863        /* Also disable virtual event stream */
 864        cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
 865                        | ARCH_TIMER_USR_VT_ACCESS_EN
 866                        | ARCH_TIMER_USR_VCT_ACCESS_EN
 867                        | ARCH_TIMER_VIRT_EVT_EN
 868                        | ARCH_TIMER_USR_PCT_ACCESS_EN);
 869
 870        /*
 871         * Enable user access to the virtual counter if it doesn't
 872         * need to be workaround. The vdso may have been already
 873         * disabled though.
 874         */
 875        if (arch_timer_this_cpu_has_cntvct_wa())
 876                pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
 877        else
 878                cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
 879
 880        arch_timer_set_cntkctl(cntkctl);
 881}
 882
 883static bool arch_timer_has_nonsecure_ppi(void)
 884{
 885        return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
 886                arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
 887}
 888
 889static u32 check_ppi_trigger(int irq)
 890{
 891        u32 flags = irq_get_trigger_type(irq);
 892
 893        if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
 894                pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
 895                pr_warn("WARNING: Please fix your firmware\n");
 896                flags = IRQF_TRIGGER_LOW;
 897        }
 898
 899        return flags;
 900}
 901
 902static int arch_timer_starting_cpu(unsigned int cpu)
 903{
 904        struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
 905        u32 flags;
 906
 907        __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
 908
 909        flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
 910        enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
 911
 912        if (arch_timer_has_nonsecure_ppi()) {
 913                flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
 914                enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
 915                                  flags);
 916        }
 917
 918        arch_counter_set_user_access();
 919        if (evtstrm_enable)
 920                arch_timer_configure_evtstream();
 921
 922        return 0;
 923}
 924
 925static int validate_timer_rate(void)
 926{
 927        if (!arch_timer_rate)
 928                return -EINVAL;
 929
 930        /* Arch timer frequency < 1MHz can cause trouble */
 931        WARN_ON(arch_timer_rate < 1000000);
 932
 933        return 0;
 934}
 935
 936/*
 937 * For historical reasons, when probing with DT we use whichever (non-zero)
 938 * rate was probed first, and don't verify that others match. If the first node
 939 * probed has a clock-frequency property, this overrides the HW register.
 940 */
 941static void __init arch_timer_of_configure_rate(u32 rate, struct device_node *np)
 942{
 943        /* Who has more than one independent system counter? */
 944        if (arch_timer_rate)
 945                return;
 946
 947        if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
 948                arch_timer_rate = rate;
 949
 950        /* Check the timer frequency. */
 951        if (validate_timer_rate())
 952                pr_warn("frequency not available\n");
 953}
 954
 955static void __init arch_timer_banner(unsigned type)
 956{
 957        pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
 958                type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
 959                type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
 960                        " and " : "",
 961                type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
 962                (unsigned long)arch_timer_rate / 1000000,
 963                (unsigned long)(arch_timer_rate / 10000) % 100,
 964                type & ARCH_TIMER_TYPE_CP15 ?
 965                        (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
 966                        "",
 967                type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
 968                type & ARCH_TIMER_TYPE_MEM ?
 969                        arch_timer_mem_use_virtual ? "virt" : "phys" :
 970                        "");
 971}
 972
 973u32 arch_timer_get_rate(void)
 974{
 975        return arch_timer_rate;
 976}
 977
 978bool arch_timer_evtstrm_available(void)
 979{
 980        /*
 981         * We might get called from a preemptible context. This is fine
 982         * because availability of the event stream should be always the same
 983         * for a preemptible context and context where we might resume a task.
 984         */
 985        return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
 986}
 987
 988static u64 arch_counter_get_cntvct_mem(void)
 989{
 990        u32 vct_lo, vct_hi, tmp_hi;
 991
 992        do {
 993                vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
 994                vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
 995                tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
 996        } while (vct_hi != tmp_hi);
 997
 998        return ((u64) vct_hi << 32) | vct_lo;
 999}
1000
1001static struct arch_timer_kvm_info arch_timer_kvm_info;
1002
1003struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
1004{
1005        return &arch_timer_kvm_info;
1006}
1007
1008static void __init arch_counter_register(unsigned type)
1009{
1010        u64 start_count;
1011
1012        /* Register the CP15 based counter if we have one */
1013        if (type & ARCH_TIMER_TYPE_CP15) {
1014                u64 (*rd)(void);
1015
1016                if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
1017                    arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
1018                        if (arch_timer_counter_has_wa())
1019                                rd = arch_counter_get_cntvct_stable;
1020                        else
1021                                rd = arch_counter_get_cntvct;
1022                } else {
1023                        if (arch_timer_counter_has_wa())
1024                                rd = arch_counter_get_cntpct_stable;
1025                        else
1026                                rd = arch_counter_get_cntpct;
1027                }
1028
1029                arch_timer_read_counter = rd;
1030                clocksource_counter.vdso_clock_mode = vdso_default;
1031        } else {
1032                arch_timer_read_counter = arch_counter_get_cntvct_mem;
1033        }
1034
1035        if (!arch_counter_suspend_stop)
1036                clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1037        start_count = arch_timer_read_counter();
1038        clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1039        cyclecounter.mult = clocksource_counter.mult;
1040        cyclecounter.shift = clocksource_counter.shift;
1041        timecounter_init(&arch_timer_kvm_info.timecounter,
1042                         &cyclecounter, start_count);
1043
1044        /* 56 bits minimum, so we assume worst case rollover */
1045        sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
1046}
1047
1048static void arch_timer_stop(struct clock_event_device *clk)
1049{
1050        pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1051
1052        disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1053        if (arch_timer_has_nonsecure_ppi())
1054                disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1055
1056        clk->set_state_shutdown(clk);
1057}
1058
1059static int arch_timer_dying_cpu(unsigned int cpu)
1060{
1061        struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1062
1063        cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1064
1065        arch_timer_stop(clk);
1066        return 0;
1067}
1068
1069#ifdef CONFIG_CPU_PM
1070static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1071static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1072                                    unsigned long action, void *hcpu)
1073{
1074        if (action == CPU_PM_ENTER) {
1075                __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1076
1077                cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1078        } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1079                arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1080
1081                if (arch_timer_have_evtstrm_feature())
1082                        cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1083        }
1084        return NOTIFY_OK;
1085}
1086
1087static struct notifier_block arch_timer_cpu_pm_notifier = {
1088        .notifier_call = arch_timer_cpu_pm_notify,
1089};
1090
1091static int __init arch_timer_cpu_pm_init(void)
1092{
1093        return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1094}
1095
1096static void __init arch_timer_cpu_pm_deinit(void)
1097{
1098        WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1099}
1100
1101#else
1102static int __init arch_timer_cpu_pm_init(void)
1103{
1104        return 0;
1105}
1106
1107static void __init arch_timer_cpu_pm_deinit(void)
1108{
1109}
1110#endif
1111
1112static int __init arch_timer_register(void)
1113{
1114        int err;
1115        int ppi;
1116
1117        arch_timer_evt = alloc_percpu(struct clock_event_device);
1118        if (!arch_timer_evt) {
1119                err = -ENOMEM;
1120                goto out;
1121        }
1122
1123        ppi = arch_timer_ppi[arch_timer_uses_ppi];
1124        switch (arch_timer_uses_ppi) {
1125        case ARCH_TIMER_VIRT_PPI:
1126                err = request_percpu_irq(ppi, arch_timer_handler_virt,
1127                                         "arch_timer", arch_timer_evt);
1128                break;
1129        case ARCH_TIMER_PHYS_SECURE_PPI:
1130        case ARCH_TIMER_PHYS_NONSECURE_PPI:
1131                err = request_percpu_irq(ppi, arch_timer_handler_phys,
1132                                         "arch_timer", arch_timer_evt);
1133                if (!err && arch_timer_has_nonsecure_ppi()) {
1134                        ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1135                        err = request_percpu_irq(ppi, arch_timer_handler_phys,
1136                                                 "arch_timer", arch_timer_evt);
1137                        if (err)
1138                                free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1139                                                arch_timer_evt);
1140                }
1141                break;
1142        case ARCH_TIMER_HYP_PPI:
1143                err = request_percpu_irq(ppi, arch_timer_handler_phys,
1144                                         "arch_timer", arch_timer_evt);
1145                break;
1146        default:
1147                BUG();
1148        }
1149
1150        if (err) {
1151                pr_err("can't register interrupt %d (%d)\n", ppi, err);
1152                goto out_free;
1153        }
1154
1155        err = arch_timer_cpu_pm_init();
1156        if (err)
1157                goto out_unreg_notify;
1158
1159        /* Register and immediately configure the timer on the boot CPU */
1160        err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1161                                "clockevents/arm/arch_timer:starting",
1162                                arch_timer_starting_cpu, arch_timer_dying_cpu);
1163        if (err)
1164                goto out_unreg_cpupm;
1165        return 0;
1166
1167out_unreg_cpupm:
1168        arch_timer_cpu_pm_deinit();
1169
1170out_unreg_notify:
1171        free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1172        if (arch_timer_has_nonsecure_ppi())
1173                free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1174                                arch_timer_evt);
1175
1176out_free:
1177        free_percpu(arch_timer_evt);
1178out:
1179        return err;
1180}
1181
1182static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1183{
1184        int ret;
1185        irq_handler_t func;
1186        struct arch_timer *t;
1187
1188        t = kzalloc(sizeof(*t), GFP_KERNEL);
1189        if (!t)
1190                return -ENOMEM;
1191
1192        t->base = base;
1193        t->evt.irq = irq;
1194        __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
1195
1196        if (arch_timer_mem_use_virtual)
1197                func = arch_timer_handler_virt_mem;
1198        else
1199                func = arch_timer_handler_phys_mem;
1200
1201        ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
1202        if (ret) {
1203                pr_err("Failed to request mem timer irq\n");
1204                kfree(t);
1205        }
1206
1207        return ret;
1208}
1209
1210static const struct of_device_id arch_timer_of_match[] __initconst = {
1211        { .compatible   = "arm,armv7-timer",    },
1212        { .compatible   = "arm,armv8-timer",    },
1213        {},
1214};
1215
1216static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1217        { .compatible   = "arm,armv7-timer-mem", },
1218        {},
1219};
1220
1221static bool __init arch_timer_needs_of_probing(void)
1222{
1223        struct device_node *dn;
1224        bool needs_probing = false;
1225        unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1226
1227        /* We have two timers, and both device-tree nodes are probed. */
1228        if ((arch_timers_present & mask) == mask)
1229                return false;
1230
1231        /*
1232         * Only one type of timer is probed,
1233         * check if we have another type of timer node in device-tree.
1234         */
1235        if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1236                dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1237        else
1238                dn = of_find_matching_node(NULL, arch_timer_of_match);
1239
1240        if (dn && of_device_is_available(dn))
1241                needs_probing = true;
1242
1243        of_node_put(dn);
1244
1245        return needs_probing;
1246}
1247
1248static int __init arch_timer_common_init(void)
1249{
1250        arch_timer_banner(arch_timers_present);
1251        arch_counter_register(arch_timers_present);
1252        return arch_timer_arch_init();
1253}
1254
1255/**
1256 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1257 *
1258 * If HYP mode is available, we know that the physical timer
1259 * has been configured to be accessible from PL1. Use it, so
1260 * that a guest can use the virtual timer instead.
1261 *
1262 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1263 * accesses to CNTP_*_EL1 registers are silently redirected to
1264 * their CNTHP_*_EL2 counterparts, and use a different PPI
1265 * number.
1266 *
1267 * If no interrupt provided for virtual timer, we'll have to
1268 * stick to the physical timer. It'd better be accessible...
1269 * For arm64 we never use the secure interrupt.
1270 *
1271 * Return: a suitable PPI type for the current system.
1272 */
1273static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1274{
1275        if (is_kernel_in_hyp_mode())
1276                return ARCH_TIMER_HYP_PPI;
1277
1278        if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1279                return ARCH_TIMER_VIRT_PPI;
1280
1281        if (IS_ENABLED(CONFIG_ARM64))
1282                return ARCH_TIMER_PHYS_NONSECURE_PPI;
1283
1284        return ARCH_TIMER_PHYS_SECURE_PPI;
1285}
1286
1287static void __init arch_timer_populate_kvm_info(void)
1288{
1289        arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1290        if (is_kernel_in_hyp_mode())
1291                arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1292}
1293
1294static int __init arch_timer_of_init(struct device_node *np)
1295{
1296        int i, irq, ret;
1297        u32 rate;
1298        bool has_names;
1299
1300        if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1301                pr_warn("multiple nodes in dt, skipping\n");
1302                return 0;
1303        }
1304
1305        arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1306
1307        has_names = of_property_read_bool(np, "interrupt-names");
1308
1309        for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) {
1310                if (has_names)
1311                        irq = of_irq_get_byname(np, arch_timer_ppi_names[i]);
1312                else
1313                        irq = of_irq_get(np, i);
1314                if (irq > 0)
1315                        arch_timer_ppi[i] = irq;
1316        }
1317
1318        arch_timer_populate_kvm_info();
1319
1320        rate = arch_timer_get_cntfrq();
1321        arch_timer_of_configure_rate(rate, np);
1322
1323        arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1324
1325        /* Check for globally applicable workarounds */
1326        arch_timer_check_ool_workaround(ate_match_dt, np);
1327
1328        /*
1329         * If we cannot rely on firmware initializing the timer registers then
1330         * we should use the physical timers instead.
1331         */
1332        if (IS_ENABLED(CONFIG_ARM) &&
1333            of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1334                arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1335        else
1336                arch_timer_uses_ppi = arch_timer_select_ppi();
1337
1338        if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1339                pr_err("No interrupt available, giving up\n");
1340                return -EINVAL;
1341        }
1342
1343        /* On some systems, the counter stops ticking when in suspend. */
1344        arch_counter_suspend_stop = of_property_read_bool(np,
1345                                                         "arm,no-tick-in-suspend");
1346
1347        ret = arch_timer_register();
1348        if (ret)
1349                return ret;
1350
1351        if (arch_timer_needs_of_probing())
1352                return 0;
1353
1354        return arch_timer_common_init();
1355}
1356TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1357TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1358
1359static u32 __init
1360arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1361{
1362        void __iomem *base;
1363        u32 rate;
1364
1365        base = ioremap(frame->cntbase, frame->size);
1366        if (!base) {
1367                pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1368                return 0;
1369        }
1370
1371        rate = readl_relaxed(base + CNTFRQ);
1372
1373        iounmap(base);
1374
1375        return rate;
1376}
1377
1378static struct arch_timer_mem_frame * __init
1379arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1380{
1381        struct arch_timer_mem_frame *frame, *best_frame = NULL;
1382        void __iomem *cntctlbase;
1383        u32 cnttidr;
1384        int i;
1385
1386        cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1387        if (!cntctlbase) {
1388                pr_err("Can't map CNTCTLBase @ %pa\n",
1389                        &timer_mem->cntctlbase);
1390                return NULL;
1391        }
1392
1393        cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1394
1395        /*
1396         * Try to find a virtual capable frame. Otherwise fall back to a
1397         * physical capable frame.
1398         */
1399        for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1400                u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1401                             CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1402
1403                frame = &timer_mem->frame[i];
1404                if (!frame->valid)
1405                        continue;
1406
1407                /* Try enabling everything, and see what sticks */
1408                writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1409                cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1410
1411                if ((cnttidr & CNTTIDR_VIRT(i)) &&
1412                    !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1413                        best_frame = frame;
1414                        arch_timer_mem_use_virtual = true;
1415                        break;
1416                }
1417
1418                if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1419                        continue;
1420
1421                best_frame = frame;
1422        }
1423
1424        iounmap(cntctlbase);
1425
1426        return best_frame;
1427}
1428
1429static int __init
1430arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1431{
1432        void __iomem *base;
1433        int ret, irq = 0;
1434
1435        if (arch_timer_mem_use_virtual)
1436                irq = frame->virt_irq;
1437        else
1438                irq = frame->phys_irq;
1439
1440        if (!irq) {
1441                pr_err("Frame missing %s irq.\n",
1442                       arch_timer_mem_use_virtual ? "virt" : "phys");
1443                return -EINVAL;
1444        }
1445
1446        if (!request_mem_region(frame->cntbase, frame->size,
1447                                "arch_mem_timer"))
1448                return -EBUSY;
1449
1450        base = ioremap(frame->cntbase, frame->size);
1451        if (!base) {
1452                pr_err("Can't map frame's registers\n");
1453                return -ENXIO;
1454        }
1455
1456        ret = arch_timer_mem_register(base, irq);
1457        if (ret) {
1458                iounmap(base);
1459                return ret;
1460        }
1461
1462        arch_counter_base = base;
1463        arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1464
1465        return 0;
1466}
1467
1468static int __init arch_timer_mem_of_init(struct device_node *np)
1469{
1470        struct arch_timer_mem *timer_mem;
1471        struct arch_timer_mem_frame *frame;
1472        struct device_node *frame_node;
1473        struct resource res;
1474        int ret = -EINVAL;
1475        u32 rate;
1476
1477        timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1478        if (!timer_mem)
1479                return -ENOMEM;
1480
1481        if (of_address_to_resource(np, 0, &res))
1482                goto out;
1483        timer_mem->cntctlbase = res.start;
1484        timer_mem->size = resource_size(&res);
1485
1486        for_each_available_child_of_node(np, frame_node) {
1487                u32 n;
1488                struct arch_timer_mem_frame *frame;
1489
1490                if (of_property_read_u32(frame_node, "frame-number", &n)) {
1491                        pr_err(FW_BUG "Missing frame-number.\n");
1492                        of_node_put(frame_node);
1493                        goto out;
1494                }
1495                if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1496                        pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1497                               ARCH_TIMER_MEM_MAX_FRAMES - 1);
1498                        of_node_put(frame_node);
1499                        goto out;
1500                }
1501                frame = &timer_mem->frame[n];
1502
1503                if (frame->valid) {
1504                        pr_err(FW_BUG "Duplicated frame-number.\n");
1505                        of_node_put(frame_node);
1506                        goto out;
1507                }
1508
1509                if (of_address_to_resource(frame_node, 0, &res)) {
1510                        of_node_put(frame_node);
1511                        goto out;
1512                }
1513                frame->cntbase = res.start;
1514                frame->size = resource_size(&res);
1515
1516                frame->virt_irq = irq_of_parse_and_map(frame_node,
1517                                                       ARCH_TIMER_VIRT_SPI);
1518                frame->phys_irq = irq_of_parse_and_map(frame_node,
1519                                                       ARCH_TIMER_PHYS_SPI);
1520
1521                frame->valid = true;
1522        }
1523
1524        frame = arch_timer_mem_find_best_frame(timer_mem);
1525        if (!frame) {
1526                pr_err("Unable to find a suitable frame in timer @ %pa\n",
1527                        &timer_mem->cntctlbase);
1528                ret = -EINVAL;
1529                goto out;
1530        }
1531
1532        rate = arch_timer_mem_frame_get_cntfrq(frame);
1533        arch_timer_of_configure_rate(rate, np);
1534
1535        ret = arch_timer_mem_frame_register(frame);
1536        if (!ret && !arch_timer_needs_of_probing())
1537                ret = arch_timer_common_init();
1538out:
1539        kfree(timer_mem);
1540        return ret;
1541}
1542TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1543                       arch_timer_mem_of_init);
1544
1545#ifdef CONFIG_ACPI_GTDT
1546static int __init
1547arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1548{
1549        struct arch_timer_mem_frame *frame;
1550        u32 rate;
1551        int i;
1552
1553        for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1554                frame = &timer_mem->frame[i];
1555
1556                if (!frame->valid)
1557                        continue;
1558
1559                rate = arch_timer_mem_frame_get_cntfrq(frame);
1560                if (rate == arch_timer_rate)
1561                        continue;
1562
1563                pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1564                        &frame->cntbase,
1565                        (unsigned long)rate, (unsigned long)arch_timer_rate);
1566
1567                return -EINVAL;
1568        }
1569
1570        return 0;
1571}
1572
1573static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1574{
1575        struct arch_timer_mem *timers, *timer;
1576        struct arch_timer_mem_frame *frame, *best_frame = NULL;
1577        int timer_count, i, ret = 0;
1578
1579        timers = kcalloc(platform_timer_count, sizeof(*timers),
1580                            GFP_KERNEL);
1581        if (!timers)
1582                return -ENOMEM;
1583
1584        ret = acpi_arch_timer_mem_init(timers, &timer_count);
1585        if (ret || !timer_count)
1586                goto out;
1587
1588        /*
1589         * While unlikely, it's theoretically possible that none of the frames
1590         * in a timer expose the combination of feature we want.
1591         */
1592        for (i = 0; i < timer_count; i++) {
1593                timer = &timers[i];
1594
1595                frame = arch_timer_mem_find_best_frame(timer);
1596                if (!best_frame)
1597                        best_frame = frame;
1598
1599                ret = arch_timer_mem_verify_cntfrq(timer);
1600                if (ret) {
1601                        pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1602                        goto out;
1603                }
1604
1605                if (!best_frame) /* implies !frame */
1606                        /*
1607                         * Only complain about missing suitable frames if we
1608                         * haven't already found one in a previous iteration.
1609                         */
1610                        pr_err("Unable to find a suitable frame in timer @ %pa\n",
1611                                &timer->cntctlbase);
1612        }
1613
1614        if (best_frame)
1615                ret = arch_timer_mem_frame_register(best_frame);
1616out:
1617        kfree(timers);
1618        return ret;
1619}
1620
1621/* Initialize per-processor generic timer and memory-mapped timer(if present) */
1622static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1623{
1624        int ret, platform_timer_count;
1625
1626        if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1627                pr_warn("already initialized, skipping\n");
1628                return -EINVAL;
1629        }
1630
1631        arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1632
1633        ret = acpi_gtdt_init(table, &platform_timer_count);
1634        if (ret)
1635                return ret;
1636
1637        arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1638                acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1639
1640        arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1641                acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1642
1643        arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1644                acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1645
1646        arch_timer_populate_kvm_info();
1647
1648        /*
1649         * When probing via ACPI, we have no mechanism to override the sysreg
1650         * CNTFRQ value. This *must* be correct.
1651         */
1652        arch_timer_rate = arch_timer_get_cntfrq();
1653        ret = validate_timer_rate();
1654        if (ret) {
1655                pr_err(FW_BUG "frequency not available.\n");
1656                return ret;
1657        }
1658
1659        arch_timer_uses_ppi = arch_timer_select_ppi();
1660        if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1661                pr_err("No interrupt available, giving up\n");
1662                return -EINVAL;
1663        }
1664
1665        /* Always-on capability */
1666        arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1667
1668        /* Check for globally applicable workarounds */
1669        arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1670
1671        ret = arch_timer_register();
1672        if (ret)
1673                return ret;
1674
1675        if (platform_timer_count &&
1676            arch_timer_mem_acpi_init(platform_timer_count))
1677                pr_err("Failed to initialize memory-mapped timer.\n");
1678
1679        return arch_timer_common_init();
1680}
1681TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1682#endif
1683
1684int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts,
1685                                 struct clocksource **cs)
1686{
1687        struct arm_smccc_res hvc_res;
1688        u32 ptp_counter;
1689        ktime_t ktime;
1690
1691        if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY))
1692                return -EOPNOTSUPP;
1693
1694        if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
1695                ptp_counter = KVM_PTP_VIRT_COUNTER;
1696        else
1697                ptp_counter = KVM_PTP_PHYS_COUNTER;
1698
1699        arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
1700                             ptp_counter, &hvc_res);
1701
1702        if ((int)(hvc_res.a0) < 0)
1703                return -EOPNOTSUPP;
1704
1705        ktime = (u64)hvc_res.a0 << 32 | hvc_res.a1;
1706        *ts = ktime_to_timespec64(ktime);
1707        if (cycle)
1708                *cycle = (u64)hvc_res.a2 << 32 | hvc_res.a3;
1709        if (cs)
1710                *cs = &clocksource_counter;
1711
1712        return 0;
1713}
1714EXPORT_SYMBOL_GPL(kvm_arch_ptp_get_crosststamp);
1715