linux/drivers/clk/tegra/clk-pll.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#include <linux/slab.h>
   7#include <linux/io.h>
   8#include <linux/delay.h>
   9#include <linux/err.h>
  10#include <linux/clk.h>
  11#include <linux/clk-provider.h>
  12
  13#include "clk.h"
  14
  15#define PLL_BASE_BYPASS BIT(31)
  16#define PLL_BASE_ENABLE BIT(30)
  17#define PLL_BASE_REF_ENABLE BIT(29)
  18#define PLL_BASE_OVERRIDE BIT(28)
  19
  20#define PLL_BASE_DIVP_SHIFT 20
  21#define PLL_BASE_DIVP_WIDTH 3
  22#define PLL_BASE_DIVN_SHIFT 8
  23#define PLL_BASE_DIVN_WIDTH 10
  24#define PLL_BASE_DIVM_SHIFT 0
  25#define PLL_BASE_DIVM_WIDTH 5
  26#define PLLU_POST_DIVP_MASK 0x1
  27
  28#define PLL_MISC_DCCON_SHIFT 20
  29#define PLL_MISC_CPCON_SHIFT 8
  30#define PLL_MISC_CPCON_WIDTH 4
  31#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  32#define PLL_MISC_LFCON_SHIFT 4
  33#define PLL_MISC_LFCON_WIDTH 4
  34#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  35#define PLL_MISC_VCOCON_SHIFT 0
  36#define PLL_MISC_VCOCON_WIDTH 4
  37#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  38
  39#define OUT_OF_TABLE_CPCON 8
  40
  41#define PMC_PLLP_WB0_OVERRIDE 0xf8
  42#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  43#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  44
  45#define PLL_POST_LOCK_DELAY 50
  46
  47#define PLLDU_LFCON_SET_DIVN 600
  48
  49#define PLLE_BASE_DIVCML_SHIFT 24
  50#define PLLE_BASE_DIVCML_MASK 0xf
  51#define PLLE_BASE_DIVP_SHIFT 16
  52#define PLLE_BASE_DIVP_WIDTH 6
  53#define PLLE_BASE_DIVN_SHIFT 8
  54#define PLLE_BASE_DIVN_WIDTH 8
  55#define PLLE_BASE_DIVM_SHIFT 0
  56#define PLLE_BASE_DIVM_WIDTH 8
  57#define PLLE_BASE_ENABLE BIT(31)
  58
  59#define PLLE_MISC_SETUP_BASE_SHIFT 16
  60#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  61#define PLLE_MISC_LOCK_ENABLE BIT(9)
  62#define PLLE_MISC_READY BIT(15)
  63#define PLLE_MISC_SETUP_EX_SHIFT 2
  64#define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  65#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  66                              PLLE_MISC_SETUP_EX_MASK)
  67#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  68
  69#define PLLE_SS_CTRL 0x68
  70#define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  71#define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  72#define PLLE_SS_CNTL_SSC_BYP BIT(12)
  73#define PLLE_SS_CNTL_CENTER BIT(14)
  74#define PLLE_SS_CNTL_INVERT BIT(15)
  75#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  76                                PLLE_SS_CNTL_SSC_BYP)
  77#define PLLE_SS_MAX_MASK 0x1ff
  78#define PLLE_SS_MAX_VAL_TEGRA114 0x25
  79#define PLLE_SS_MAX_VAL_TEGRA210 0x21
  80#define PLLE_SS_INC_MASK (0xff << 16)
  81#define PLLE_SS_INC_VAL (0x1 << 16)
  82#define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  83#define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
  84#define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
  85#define PLLE_SS_COEFFICIENTS_MASK \
  86        (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  87#define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
  88        (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
  89         PLLE_SS_INCINTRV_VAL_TEGRA114)
  90#define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
  91        (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
  92         PLLE_SS_INCINTRV_VAL_TEGRA210)
  93
  94#define PLLE_AUX_PLLP_SEL       BIT(2)
  95#define PLLE_AUX_USE_LOCKDET    BIT(3)
  96#define PLLE_AUX_ENABLE_SWCTL   BIT(4)
  97#define PLLE_AUX_SS_SWCTL       BIT(6)
  98#define PLLE_AUX_SEQ_ENABLE     BIT(24)
  99#define PLLE_AUX_SEQ_START_STATE BIT(25)
 100#define PLLE_AUX_PLLRE_SEL      BIT(28)
 101#define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
 102
 103#define XUSBIO_PLL_CFG0         0x51c
 104#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 105#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 106#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 107#define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 108#define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 109
 110#define SATA_PLL_CFG0           0x490
 111#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 112#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 113#define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 114#define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 115
 116#define PLLE_MISC_PLLE_PTS      BIT(8)
 117#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 118#define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 119#define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 120#define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 121#define PLLE_MISC_VREG_CTRL_SHIFT       2
 122#define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 123
 124#define PLLCX_MISC_STROBE       BIT(31)
 125#define PLLCX_MISC_RESET        BIT(30)
 126#define PLLCX_MISC_SDM_DIV_SHIFT 28
 127#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 128#define PLLCX_MISC_FILT_DIV_SHIFT 26
 129#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 130#define PLLCX_MISC_ALPHA_SHIFT 18
 131#define PLLCX_MISC_DIV_LOW_RANGE \
 132                ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 133                (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 134#define PLLCX_MISC_DIV_HIGH_RANGE \
 135                ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 136                (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 137#define PLLCX_MISC_COEF_LOW_RANGE \
 138                ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 139#define PLLCX_MISC_KA_SHIFT 2
 140#define PLLCX_MISC_KB_SHIFT 9
 141#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 142                            (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 143                            PLLCX_MISC_DIV_LOW_RANGE | \
 144                            PLLCX_MISC_RESET)
 145#define PLLCX_MISC1_DEFAULT 0x000d2308
 146#define PLLCX_MISC2_DEFAULT 0x30211200
 147#define PLLCX_MISC3_DEFAULT 0x200
 148
 149#define PMC_SATA_PWRGT 0x1ac
 150#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 151#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 152
 153#define PLLSS_MISC_KCP          0
 154#define PLLSS_MISC_KVCO         0
 155#define PLLSS_MISC_SETUP        0
 156#define PLLSS_EN_SDM            0
 157#define PLLSS_EN_SSC            0
 158#define PLLSS_EN_DITHER2        0
 159#define PLLSS_EN_DITHER         1
 160#define PLLSS_SDM_RESET         0
 161#define PLLSS_CLAMP             0
 162#define PLLSS_SDM_SSC_MAX       0
 163#define PLLSS_SDM_SSC_MIN       0
 164#define PLLSS_SDM_SSC_STEP      0
 165#define PLLSS_SDM_DIN           0
 166#define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 167                            (PLLSS_MISC_KVCO << 24) | \
 168                            PLLSS_MISC_SETUP)
 169#define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 170                           (PLLSS_EN_SSC << 30) | \
 171                           (PLLSS_EN_DITHER2 << 29) | \
 172                           (PLLSS_EN_DITHER << 28) | \
 173                           (PLLSS_SDM_RESET) << 27 | \
 174                           (PLLSS_CLAMP << 22))
 175#define PLLSS_CTRL1_DEFAULT \
 176                        ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 177#define PLLSS_CTRL2_DEFAULT \
 178                        ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 179#define PLLSS_LOCK_OVERRIDE     BIT(24)
 180#define PLLSS_REF_SRC_SEL_SHIFT 25
 181#define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 182
 183#define UTMIP_PLL_CFG1 0x484
 184#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 185#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
 186#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 187#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 188#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 189#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 190#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 191
 192#define UTMIP_PLL_CFG2 0x488
 193#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
 194#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 195#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 196#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
 197#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 198#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
 199#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 200#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
 201#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
 202#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
 203#define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
 204
 205#define UTMIPLL_HW_PWRDN_CFG0 0x52c
 206#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
 207#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
 208#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 209#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
 210#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
 211#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 212#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 213#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
 214
 215#define PLLU_HW_PWRDN_CFG0 0x530
 216#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
 217#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 218#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 219#define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
 220#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 221#define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
 222
 223#define XUSB_PLL_CFG0 0x534
 224#define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
 225#define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
 226
 227#define PLLU_BASE_CLKENABLE_USB BIT(21)
 228#define PLLU_BASE_OVERRIDE BIT(24)
 229
 230#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 231#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 232#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 233#define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 234#define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
 235#define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
 236
 237#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 238#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 239#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 240#define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 241#define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
 242#define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
 243
 244#define mask(w) ((1 << (w)) - 1)
 245#define divm_mask(p) mask(p->params->div_nmp->divm_width)
 246#define divn_mask(p) mask(p->params->div_nmp->divn_width)
 247#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 248                      mask(p->params->div_nmp->divp_width))
 249#define sdm_din_mask(p) p->params->sdm_din_mask
 250#define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
 251
 252#define divm_shift(p) (p)->params->div_nmp->divm_shift
 253#define divn_shift(p) (p)->params->div_nmp->divn_shift
 254#define divp_shift(p) (p)->params->div_nmp->divp_shift
 255
 256#define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 257#define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 258#define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 259
 260#define divm_max(p) (divm_mask(p))
 261#define divn_max(p) (divn_mask(p))
 262#define divp_max(p) (1 << (divp_mask(p)))
 263
 264#define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 265#define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
 266
 267static struct div_nmp default_nmp = {
 268        .divn_shift = PLL_BASE_DIVN_SHIFT,
 269        .divn_width = PLL_BASE_DIVN_WIDTH,
 270        .divm_shift = PLL_BASE_DIVM_SHIFT,
 271        .divm_width = PLL_BASE_DIVM_WIDTH,
 272        .divp_shift = PLL_BASE_DIVP_SHIFT,
 273        .divp_width = PLL_BASE_DIVP_WIDTH,
 274};
 275
 276static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 277{
 278        u32 val;
 279
 280        if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 281                return;
 282
 283        if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 284                return;
 285
 286        val = pll_readl_misc(pll);
 287        val |= BIT(pll->params->lock_enable_bit_idx);
 288        pll_writel_misc(val, pll);
 289}
 290
 291static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 292{
 293        int i;
 294        u32 val, lock_mask;
 295        void __iomem *lock_addr;
 296
 297        if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 298                udelay(pll->params->lock_delay);
 299                return 0;
 300        }
 301
 302        lock_addr = pll->clk_base;
 303        if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 304                lock_addr += pll->params->misc_reg;
 305        else
 306                lock_addr += pll->params->base_reg;
 307
 308        lock_mask = pll->params->lock_mask;
 309
 310        for (i = 0; i < pll->params->lock_delay; i++) {
 311                val = readl_relaxed(lock_addr);
 312                if ((val & lock_mask) == lock_mask) {
 313                        udelay(PLL_POST_LOCK_DELAY);
 314                        return 0;
 315                }
 316                udelay(2); /* timeout = 2 * lock time */
 317        }
 318
 319        pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 320               clk_hw_get_name(&pll->hw));
 321
 322        return -1;
 323}
 324
 325int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
 326{
 327        return clk_pll_wait_for_lock(pll);
 328}
 329
 330static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
 331{
 332        u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 333
 334        return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
 335              !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
 336}
 337
 338static int clk_pll_is_enabled(struct clk_hw *hw)
 339{
 340        struct tegra_clk_pll *pll = to_clk_pll(hw);
 341        u32 val;
 342
 343        /*
 344         * Power Management Controller (PMC) can override the PLLM clock
 345         * settings, including the enable-state. The PLLM is enabled when
 346         * PLLM's CaR state is ON and when PLLM isn't gated by PMC.
 347         */
 348        if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
 349                return 0;
 350
 351        val = pll_readl_base(pll);
 352
 353        return val & PLL_BASE_ENABLE ? 1 : 0;
 354}
 355
 356static void _clk_pll_enable(struct clk_hw *hw)
 357{
 358        struct tegra_clk_pll *pll = to_clk_pll(hw);
 359        u32 val;
 360
 361        if (pll->params->iddq_reg) {
 362                val = pll_readl(pll->params->iddq_reg, pll);
 363                val &= ~BIT(pll->params->iddq_bit_idx);
 364                pll_writel(val, pll->params->iddq_reg, pll);
 365                udelay(5);
 366        }
 367
 368        if (pll->params->reset_reg) {
 369                val = pll_readl(pll->params->reset_reg, pll);
 370                val &= ~BIT(pll->params->reset_bit_idx);
 371                pll_writel(val, pll->params->reset_reg, pll);
 372        }
 373
 374        clk_pll_enable_lock(pll);
 375
 376        val = pll_readl_base(pll);
 377        if (pll->params->flags & TEGRA_PLL_BYPASS)
 378                val &= ~PLL_BASE_BYPASS;
 379        val |= PLL_BASE_ENABLE;
 380        pll_writel_base(val, pll);
 381
 382        if (pll->params->flags & TEGRA_PLLM) {
 383                val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 384                val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 385                writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 386        }
 387}
 388
 389static void _clk_pll_disable(struct clk_hw *hw)
 390{
 391        struct tegra_clk_pll *pll = to_clk_pll(hw);
 392        u32 val;
 393
 394        val = pll_readl_base(pll);
 395        if (pll->params->flags & TEGRA_PLL_BYPASS)
 396                val &= ~PLL_BASE_BYPASS;
 397        val &= ~PLL_BASE_ENABLE;
 398        pll_writel_base(val, pll);
 399
 400        if (pll->params->flags & TEGRA_PLLM) {
 401                val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 402                val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 403                writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 404        }
 405
 406        if (pll->params->reset_reg) {
 407                val = pll_readl(pll->params->reset_reg, pll);
 408                val |= BIT(pll->params->reset_bit_idx);
 409                pll_writel(val, pll->params->reset_reg, pll);
 410        }
 411
 412        if (pll->params->iddq_reg) {
 413                val = pll_readl(pll->params->iddq_reg, pll);
 414                val |= BIT(pll->params->iddq_bit_idx);
 415                pll_writel(val, pll->params->iddq_reg, pll);
 416                udelay(2);
 417        }
 418}
 419
 420static void pll_clk_start_ss(struct tegra_clk_pll *pll)
 421{
 422        if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 423                u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 424
 425                val |= pll->params->ssc_ctrl_en_mask;
 426                pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 427        }
 428}
 429
 430static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
 431{
 432        if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 433                u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 434
 435                val &= ~pll->params->ssc_ctrl_en_mask;
 436                pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 437        }
 438}
 439
 440static int clk_pll_enable(struct clk_hw *hw)
 441{
 442        struct tegra_clk_pll *pll = to_clk_pll(hw);
 443        unsigned long flags = 0;
 444        int ret;
 445
 446        if (clk_pll_is_enabled(hw))
 447                return 0;
 448
 449        if (pll->lock)
 450                spin_lock_irqsave(pll->lock, flags);
 451
 452        _clk_pll_enable(hw);
 453
 454        ret = clk_pll_wait_for_lock(pll);
 455
 456        pll_clk_start_ss(pll);
 457
 458        if (pll->lock)
 459                spin_unlock_irqrestore(pll->lock, flags);
 460
 461        return ret;
 462}
 463
 464static void clk_pll_disable(struct clk_hw *hw)
 465{
 466        struct tegra_clk_pll *pll = to_clk_pll(hw);
 467        unsigned long flags = 0;
 468
 469        if (pll->lock)
 470                spin_lock_irqsave(pll->lock, flags);
 471
 472        pll_clk_stop_ss(pll);
 473
 474        _clk_pll_disable(hw);
 475
 476        if (pll->lock)
 477                spin_unlock_irqrestore(pll->lock, flags);
 478}
 479
 480static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 481{
 482        struct tegra_clk_pll *pll = to_clk_pll(hw);
 483        const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 484
 485        if (p_tohw) {
 486                while (p_tohw->pdiv) {
 487                        if (p_div <= p_tohw->pdiv)
 488                                return p_tohw->hw_val;
 489                        p_tohw++;
 490                }
 491                return -EINVAL;
 492        }
 493        return -EINVAL;
 494}
 495
 496int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
 497{
 498        return _p_div_to_hw(&pll->hw, p_div);
 499}
 500
 501static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 502{
 503        struct tegra_clk_pll *pll = to_clk_pll(hw);
 504        const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 505
 506        if (p_tohw) {
 507                while (p_tohw->pdiv) {
 508                        if (p_div_hw == p_tohw->hw_val)
 509                                return p_tohw->pdiv;
 510                        p_tohw++;
 511                }
 512                return -EINVAL;
 513        }
 514
 515        return 1 << p_div_hw;
 516}
 517
 518static int _get_table_rate(struct clk_hw *hw,
 519                           struct tegra_clk_pll_freq_table *cfg,
 520                           unsigned long rate, unsigned long parent_rate)
 521{
 522        struct tegra_clk_pll *pll = to_clk_pll(hw);
 523        struct tegra_clk_pll_freq_table *sel;
 524        int p;
 525
 526        for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 527                if (sel->input_rate == parent_rate &&
 528                    sel->output_rate == rate)
 529                        break;
 530
 531        if (sel->input_rate == 0)
 532                return -EINVAL;
 533
 534        if (pll->params->pdiv_tohw) {
 535                p = _p_div_to_hw(hw, sel->p);
 536                if (p < 0)
 537                        return p;
 538        } else {
 539                p = ilog2(sel->p);
 540        }
 541
 542        cfg->input_rate = sel->input_rate;
 543        cfg->output_rate = sel->output_rate;
 544        cfg->m = sel->m;
 545        cfg->n = sel->n;
 546        cfg->p = p;
 547        cfg->cpcon = sel->cpcon;
 548        cfg->sdm_data = sel->sdm_data;
 549
 550        return 0;
 551}
 552
 553static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 554                      unsigned long rate, unsigned long parent_rate)
 555{
 556        struct tegra_clk_pll *pll = to_clk_pll(hw);
 557        unsigned long cfreq;
 558        u32 p_div = 0;
 559        int ret;
 560
 561        switch (parent_rate) {
 562        case 12000000:
 563        case 26000000:
 564                cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 565                break;
 566        case 13000000:
 567                cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 568                break;
 569        case 16800000:
 570        case 19200000:
 571                cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 572                break;
 573        case 9600000:
 574        case 28800000:
 575                /*
 576                 * PLL_P_OUT1 rate is not listed in PLLA table
 577                 */
 578                cfreq = parent_rate / (parent_rate / 1000000);
 579                break;
 580        default:
 581                pr_err("%s Unexpected reference rate %lu\n",
 582                       __func__, parent_rate);
 583                BUG();
 584        }
 585
 586        /* Raise VCO to guarantee 0.5% accuracy */
 587        for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 588             cfg->output_rate <<= 1)
 589                p_div++;
 590
 591        cfg->m = parent_rate / cfreq;
 592        cfg->n = cfg->output_rate / cfreq;
 593        cfg->cpcon = OUT_OF_TABLE_CPCON;
 594
 595        if (cfg->m == 0 || cfg->m > divm_max(pll) ||
 596            cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
 597            cfg->output_rate > pll->params->vco_max) {
 598                return -EINVAL;
 599        }
 600
 601        cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
 602        cfg->output_rate >>= p_div;
 603
 604        if (pll->params->pdiv_tohw) {
 605                ret = _p_div_to_hw(hw, 1 << p_div);
 606                if (ret < 0)
 607                        return ret;
 608                else
 609                        cfg->p = ret;
 610        } else
 611                cfg->p = p_div;
 612
 613        return 0;
 614}
 615
 616/*
 617 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
 618 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
 619 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
 620 * to indicate that SDM is disabled.
 621 *
 622 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
 623 */
 624static void clk_pll_set_sdm_data(struct clk_hw *hw,
 625                                 struct tegra_clk_pll_freq_table *cfg)
 626{
 627        struct tegra_clk_pll *pll = to_clk_pll(hw);
 628        u32 val;
 629        bool enabled;
 630
 631        if (!pll->params->sdm_din_reg)
 632                return;
 633
 634        if (cfg->sdm_data) {
 635                val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
 636                val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
 637                pll_writel_sdm_din(val, pll);
 638        }
 639
 640        val = pll_readl_sdm_ctrl(pll);
 641        enabled = (val & sdm_en_mask(pll));
 642
 643        if (cfg->sdm_data == 0 && enabled)
 644                val &= ~pll->params->sdm_ctrl_en_mask;
 645
 646        if (cfg->sdm_data != 0 && !enabled)
 647                val |= pll->params->sdm_ctrl_en_mask;
 648
 649        pll_writel_sdm_ctrl(val, pll);
 650}
 651
 652static void _update_pll_mnp(struct tegra_clk_pll *pll,
 653                            struct tegra_clk_pll_freq_table *cfg)
 654{
 655        u32 val;
 656        struct tegra_clk_pll_params *params = pll->params;
 657        struct div_nmp *div_nmp = params->div_nmp;
 658
 659        if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 660                (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 661                        PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 662                val = pll_override_readl(params->pmc_divp_reg, pll);
 663                val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 664                val |= cfg->p << div_nmp->override_divp_shift;
 665                pll_override_writel(val, params->pmc_divp_reg, pll);
 666
 667                val = pll_override_readl(params->pmc_divnm_reg, pll);
 668                val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
 669                        (divn_mask(pll) << div_nmp->override_divn_shift));
 670                val |= (cfg->m << div_nmp->override_divm_shift) |
 671                        (cfg->n << div_nmp->override_divn_shift);
 672                pll_override_writel(val, params->pmc_divnm_reg, pll);
 673        } else {
 674                val = pll_readl_base(pll);
 675
 676                val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 677                         divp_mask_shifted(pll));
 678
 679                val |= (cfg->m << divm_shift(pll)) |
 680                       (cfg->n << divn_shift(pll)) |
 681                       (cfg->p << divp_shift(pll));
 682
 683                pll_writel_base(val, pll);
 684
 685                clk_pll_set_sdm_data(&pll->hw, cfg);
 686        }
 687}
 688
 689static void _get_pll_mnp(struct tegra_clk_pll *pll,
 690                         struct tegra_clk_pll_freq_table *cfg)
 691{
 692        u32 val;
 693        struct tegra_clk_pll_params *params = pll->params;
 694        struct div_nmp *div_nmp = params->div_nmp;
 695
 696        *cfg = (struct tegra_clk_pll_freq_table) { };
 697
 698        if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 699                (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 700                        PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 701                val = pll_override_readl(params->pmc_divp_reg, pll);
 702                cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 703
 704                val = pll_override_readl(params->pmc_divnm_reg, pll);
 705                cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 706                cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 707        }  else {
 708                val = pll_readl_base(pll);
 709
 710                cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 711                cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 712                cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 713
 714                if (pll->params->sdm_din_reg) {
 715                        if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
 716                                val = pll_readl_sdm_din(pll);
 717                                val &= sdm_din_mask(pll);
 718                                cfg->sdm_data = sdin_din_to_data(val);
 719                        }
 720                }
 721        }
 722}
 723
 724static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 725                              struct tegra_clk_pll_freq_table *cfg,
 726                              unsigned long rate)
 727{
 728        u32 val;
 729
 730        val = pll_readl_misc(pll);
 731
 732        val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 733        val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 734
 735        if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 736                val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 737                if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 738                        val |= 1 << PLL_MISC_LFCON_SHIFT;
 739        } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 740                val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 741                if (rate >= (pll->params->vco_max >> 1))
 742                        val |= 1 << PLL_MISC_DCCON_SHIFT;
 743        }
 744
 745        pll_writel_misc(val, pll);
 746}
 747
 748static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 749                        unsigned long rate)
 750{
 751        struct tegra_clk_pll *pll = to_clk_pll(hw);
 752        struct tegra_clk_pll_freq_table old_cfg;
 753        int state, ret = 0;
 754
 755        state = clk_pll_is_enabled(hw);
 756
 757        if (state && pll->params->pre_rate_change) {
 758                ret = pll->params->pre_rate_change();
 759                if (WARN_ON(ret))
 760                        return ret;
 761        }
 762
 763        _get_pll_mnp(pll, &old_cfg);
 764
 765        if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 766                        (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 767                ret = pll->params->dyn_ramp(pll, cfg);
 768                if (!ret)
 769                        goto done;
 770        }
 771
 772        if (state) {
 773                pll_clk_stop_ss(pll);
 774                _clk_pll_disable(hw);
 775        }
 776
 777        if (!pll->params->defaults_set && pll->params->set_defaults)
 778                pll->params->set_defaults(pll);
 779
 780        _update_pll_mnp(pll, cfg);
 781
 782        if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 783                _update_pll_cpcon(pll, cfg, rate);
 784
 785        if (state) {
 786                _clk_pll_enable(hw);
 787                ret = clk_pll_wait_for_lock(pll);
 788                pll_clk_start_ss(pll);
 789        }
 790
 791done:
 792        if (state && pll->params->post_rate_change)
 793                pll->params->post_rate_change();
 794
 795        return ret;
 796}
 797
 798static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 799                        unsigned long parent_rate)
 800{
 801        struct tegra_clk_pll *pll = to_clk_pll(hw);
 802        struct tegra_clk_pll_freq_table cfg, old_cfg;
 803        unsigned long flags = 0;
 804        int ret = 0;
 805
 806        if (pll->params->flags & TEGRA_PLL_FIXED) {
 807                if (rate != pll->params->fixed_rate) {
 808                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 809                                __func__, clk_hw_get_name(hw),
 810                                pll->params->fixed_rate, rate);
 811                        return -EINVAL;
 812                }
 813                return 0;
 814        }
 815
 816        if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 817            pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
 818                pr_err("%s: Failed to set %s rate %lu\n", __func__,
 819                       clk_hw_get_name(hw), rate);
 820                WARN_ON(1);
 821                return -EINVAL;
 822        }
 823        if (pll->lock)
 824                spin_lock_irqsave(pll->lock, flags);
 825
 826        _get_pll_mnp(pll, &old_cfg);
 827        if (pll->params->flags & TEGRA_PLL_VCO_OUT)
 828                cfg.p = old_cfg.p;
 829
 830        if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
 831                old_cfg.sdm_data != cfg.sdm_data)
 832                ret = _program_pll(hw, &cfg, rate);
 833
 834        if (pll->lock)
 835                spin_unlock_irqrestore(pll->lock, flags);
 836
 837        return ret;
 838}
 839
 840static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 841                        unsigned long *prate)
 842{
 843        struct tegra_clk_pll *pll = to_clk_pll(hw);
 844        struct tegra_clk_pll_freq_table cfg;
 845
 846        if (pll->params->flags & TEGRA_PLL_FIXED) {
 847                /* PLLM/MB are used for memory; we do not change rate */
 848                if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
 849                        return clk_hw_get_rate(hw);
 850                return pll->params->fixed_rate;
 851        }
 852
 853        if (_get_table_rate(hw, &cfg, rate, *prate) &&
 854            pll->params->calc_rate(hw, &cfg, rate, *prate))
 855                return -EINVAL;
 856
 857        return cfg.output_rate;
 858}
 859
 860static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 861                                         unsigned long parent_rate)
 862{
 863        struct tegra_clk_pll *pll = to_clk_pll(hw);
 864        struct tegra_clk_pll_freq_table cfg;
 865        u32 val;
 866        u64 rate = parent_rate;
 867        int pdiv;
 868
 869        val = pll_readl_base(pll);
 870
 871        if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 872                return parent_rate;
 873
 874        if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 875            !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 876                        !(val & PLL_BASE_OVERRIDE)) {
 877                struct tegra_clk_pll_freq_table sel;
 878                if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 879                                        parent_rate)) {
 880                        pr_err("Clock %s has unknown fixed frequency\n",
 881                               clk_hw_get_name(hw));
 882                        BUG();
 883                }
 884                return pll->params->fixed_rate;
 885        }
 886
 887        _get_pll_mnp(pll, &cfg);
 888
 889        if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
 890                pdiv = 1;
 891        } else {
 892                pdiv = _hw_to_p_div(hw, cfg.p);
 893                if (pdiv < 0) {
 894                        WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
 895                             clk_hw_get_name(hw), cfg.p);
 896                        pdiv = 1;
 897                }
 898        }
 899
 900        if (pll->params->set_gain)
 901                pll->params->set_gain(&cfg);
 902
 903        cfg.m *= pdiv;
 904
 905        rate *= cfg.n;
 906        do_div(rate, cfg.m);
 907
 908        return rate;
 909}
 910
 911static int clk_plle_training(struct tegra_clk_pll *pll)
 912{
 913        u32 val;
 914        unsigned long timeout;
 915
 916        if (!pll->pmc)
 917                return -ENOSYS;
 918
 919        /*
 920         * PLLE is already disabled, and setup cleared;
 921         * create falling edge on PLLE IDDQ input.
 922         */
 923        val = readl(pll->pmc + PMC_SATA_PWRGT);
 924        val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 925        writel(val, pll->pmc + PMC_SATA_PWRGT);
 926
 927        val = readl(pll->pmc + PMC_SATA_PWRGT);
 928        val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 929        writel(val, pll->pmc + PMC_SATA_PWRGT);
 930
 931        val = readl(pll->pmc + PMC_SATA_PWRGT);
 932        val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 933        writel(val, pll->pmc + PMC_SATA_PWRGT);
 934
 935        val = pll_readl_misc(pll);
 936
 937        timeout = jiffies + msecs_to_jiffies(100);
 938        while (1) {
 939                val = pll_readl_misc(pll);
 940                if (val & PLLE_MISC_READY)
 941                        break;
 942                if (time_after(jiffies, timeout)) {
 943                        pr_err("%s: timeout waiting for PLLE\n", __func__);
 944                        return -EBUSY;
 945                }
 946                udelay(300);
 947        }
 948
 949        return 0;
 950}
 951
 952static int clk_plle_enable(struct clk_hw *hw)
 953{
 954        struct tegra_clk_pll *pll = to_clk_pll(hw);
 955        struct tegra_clk_pll_freq_table sel;
 956        unsigned long input_rate;
 957        u32 val;
 958        int err;
 959
 960        if (clk_pll_is_enabled(hw))
 961                return 0;
 962
 963        input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 964
 965        if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 966                return -EINVAL;
 967
 968        clk_pll_disable(hw);
 969
 970        val = pll_readl_misc(pll);
 971        val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 972        pll_writel_misc(val, pll);
 973
 974        val = pll_readl_misc(pll);
 975        if (!(val & PLLE_MISC_READY)) {
 976                err = clk_plle_training(pll);
 977                if (err)
 978                        return err;
 979        }
 980
 981        if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 982                /* configure dividers */
 983                val = pll_readl_base(pll);
 984                val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 985                         divm_mask_shifted(pll));
 986                val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 987                val |= sel.m << divm_shift(pll);
 988                val |= sel.n << divn_shift(pll);
 989                val |= sel.p << divp_shift(pll);
 990                val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 991                pll_writel_base(val, pll);
 992        }
 993
 994        val = pll_readl_misc(pll);
 995        val |= PLLE_MISC_SETUP_VALUE;
 996        val |= PLLE_MISC_LOCK_ENABLE;
 997        pll_writel_misc(val, pll);
 998
 999        val = readl(pll->clk_base + PLLE_SS_CTRL);
1000        val &= ~PLLE_SS_COEFFICIENTS_MASK;
1001        val |= PLLE_SS_DISABLE;
1002        writel(val, pll->clk_base + PLLE_SS_CTRL);
1003
1004        val = pll_readl_base(pll);
1005        val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1006        pll_writel_base(val, pll);
1007
1008        clk_pll_wait_for_lock(pll);
1009
1010        return 0;
1011}
1012
1013static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
1014                                         unsigned long parent_rate)
1015{
1016        struct tegra_clk_pll *pll = to_clk_pll(hw);
1017        u32 val = pll_readl_base(pll);
1018        u32 divn = 0, divm = 0, divp = 0;
1019        u64 rate = parent_rate;
1020
1021        divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1022        divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1023        divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1024        divm *= divp;
1025
1026        rate *= divn;
1027        do_div(rate, divm);
1028        return rate;
1029}
1030
1031static void tegra_clk_pll_restore_context(struct clk_hw *hw)
1032{
1033        struct tegra_clk_pll *pll = to_clk_pll(hw);
1034        struct clk_hw *parent = clk_hw_get_parent(hw);
1035        unsigned long parent_rate = clk_hw_get_rate(parent);
1036        unsigned long rate = clk_hw_get_rate(hw);
1037
1038        if (clk_pll_is_enabled(hw))
1039                return;
1040
1041        if (pll->params->set_defaults)
1042                pll->params->set_defaults(pll);
1043
1044        clk_pll_set_rate(hw, rate, parent_rate);
1045
1046        if (!__clk_get_enable_count(hw->clk))
1047                clk_pll_disable(hw);
1048        else
1049                clk_pll_enable(hw);
1050}
1051
1052const struct clk_ops tegra_clk_pll_ops = {
1053        .is_enabled = clk_pll_is_enabled,
1054        .enable = clk_pll_enable,
1055        .disable = clk_pll_disable,
1056        .recalc_rate = clk_pll_recalc_rate,
1057        .round_rate = clk_pll_round_rate,
1058        .set_rate = clk_pll_set_rate,
1059        .restore_context = tegra_clk_pll_restore_context,
1060};
1061
1062const struct clk_ops tegra_clk_plle_ops = {
1063        .recalc_rate = clk_plle_recalc_rate,
1064        .is_enabled = clk_pll_is_enabled,
1065        .disable = clk_pll_disable,
1066        .enable = clk_plle_enable,
1067};
1068
1069/*
1070 * Structure defining the fields for USB UTMI clocks Parameters.
1071 */
1072struct utmi_clk_param {
1073        /* Oscillator Frequency in Hz */
1074        u32 osc_frequency;
1075        /* UTMIP PLL Enable Delay Count  */
1076        u8 enable_delay_count;
1077        /* UTMIP PLL Stable count */
1078        u8 stable_count;
1079        /*  UTMIP PLL Active delay count */
1080        u8 active_delay_count;
1081        /* UTMIP PLL Xtal frequency count */
1082        u8 xtal_freq_count;
1083};
1084
1085static const struct utmi_clk_param utmi_parameters[] = {
1086        {
1087                .osc_frequency = 13000000, .enable_delay_count = 0x02,
1088                .stable_count = 0x33, .active_delay_count = 0x05,
1089                .xtal_freq_count = 0x7f
1090        }, {
1091                .osc_frequency = 19200000, .enable_delay_count = 0x03,
1092                .stable_count = 0x4b, .active_delay_count = 0x06,
1093                .xtal_freq_count = 0xbb
1094        }, {
1095                .osc_frequency = 12000000, .enable_delay_count = 0x02,
1096                .stable_count = 0x2f, .active_delay_count = 0x04,
1097                .xtal_freq_count = 0x76
1098        }, {
1099                .osc_frequency = 26000000, .enable_delay_count = 0x04,
1100                .stable_count = 0x66, .active_delay_count = 0x09,
1101                .xtal_freq_count = 0xfe
1102        }, {
1103                .osc_frequency = 16800000, .enable_delay_count = 0x03,
1104                .stable_count = 0x41, .active_delay_count = 0x0a,
1105                .xtal_freq_count = 0xa4
1106        }, {
1107                .osc_frequency = 38400000, .enable_delay_count = 0x0,
1108                .stable_count = 0x0, .active_delay_count = 0x6,
1109                .xtal_freq_count = 0x80
1110        },
1111};
1112
1113static int clk_pllu_enable(struct clk_hw *hw)
1114{
1115        struct tegra_clk_pll *pll = to_clk_pll(hw);
1116        struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1117        struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1118        const struct utmi_clk_param *params = NULL;
1119        unsigned long flags = 0, input_rate;
1120        unsigned int i;
1121        int ret = 0;
1122        u32 value;
1123
1124        if (!osc) {
1125                pr_err("%s: failed to get OSC clock\n", __func__);
1126                return -EINVAL;
1127        }
1128
1129        input_rate = clk_hw_get_rate(osc);
1130
1131        if (pll->lock)
1132                spin_lock_irqsave(pll->lock, flags);
1133
1134        if (!clk_pll_is_enabled(hw))
1135                _clk_pll_enable(hw);
1136
1137        ret = clk_pll_wait_for_lock(pll);
1138        if (ret < 0)
1139                goto out;
1140
1141        for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1142                if (input_rate == utmi_parameters[i].osc_frequency) {
1143                        params = &utmi_parameters[i];
1144                        break;
1145                }
1146        }
1147
1148        if (!params) {
1149                pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1150                       input_rate);
1151                ret = -EINVAL;
1152                goto out;
1153        }
1154
1155        value = pll_readl_base(pll);
1156        value &= ~PLLU_BASE_OVERRIDE;
1157        pll_writel_base(value, pll);
1158
1159        value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1160        /* Program UTMIP PLL stable and active counts */
1161        value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1162        value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1163        value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1164        value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1165        /* Remove power downs from UTMIP PLL control bits */
1166        value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1167        value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1168        value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1169        writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1170
1171        value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1172        /* Program UTMIP PLL delay and oscillator frequency counts */
1173        value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1174        value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1175        value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1176        value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1177        /* Remove power downs from UTMIP PLL control bits */
1178        value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1179        value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1180        value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1181        writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1182
1183out:
1184        if (pll->lock)
1185                spin_unlock_irqrestore(pll->lock, flags);
1186
1187        return ret;
1188}
1189
1190static const struct clk_ops tegra_clk_pllu_ops = {
1191        .is_enabled = clk_pll_is_enabled,
1192        .enable = clk_pllu_enable,
1193        .disable = clk_pll_disable,
1194        .recalc_rate = clk_pll_recalc_rate,
1195        .round_rate = clk_pll_round_rate,
1196        .set_rate = clk_pll_set_rate,
1197};
1198
1199static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1200                           unsigned long parent_rate)
1201{
1202        u16 mdiv = parent_rate / pll_params->cf_min;
1203
1204        if (pll_params->flags & TEGRA_MDIV_NEW)
1205                return (!pll_params->mdiv_default ? mdiv :
1206                        min(mdiv, pll_params->mdiv_default));
1207
1208        if (pll_params->mdiv_default)
1209                return pll_params->mdiv_default;
1210
1211        if (parent_rate > pll_params->cf_max)
1212                return 2;
1213        else
1214                return 1;
1215}
1216
1217static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1218                                struct tegra_clk_pll_freq_table *cfg,
1219                                unsigned long rate, unsigned long parent_rate)
1220{
1221        struct tegra_clk_pll *pll = to_clk_pll(hw);
1222        unsigned int p;
1223        int p_div;
1224
1225        if (!rate)
1226                return -EINVAL;
1227
1228        p = DIV_ROUND_UP(pll->params->vco_min, rate);
1229        cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1230        cfg->output_rate = rate * p;
1231        cfg->n = cfg->output_rate * cfg->m / parent_rate;
1232        cfg->input_rate = parent_rate;
1233
1234        p_div = _p_div_to_hw(hw, p);
1235        if (p_div < 0)
1236                return p_div;
1237
1238        cfg->p = p_div;
1239
1240        if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1241                return -EINVAL;
1242
1243        return 0;
1244}
1245
1246#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1247        defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1248        defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1249        defined(CONFIG_ARCH_TEGRA_210_SOC)
1250
1251u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1252{
1253        struct tegra_clk_pll *pll = to_clk_pll(hw);
1254
1255        return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1256}
1257
1258static unsigned long _clip_vco_min(unsigned long vco_min,
1259                                   unsigned long parent_rate)
1260{
1261        return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1262}
1263
1264static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1265                               void __iomem *clk_base,
1266                               unsigned long parent_rate)
1267{
1268        u32 val;
1269        u32 step_a, step_b;
1270
1271        switch (parent_rate) {
1272        case 12000000:
1273        case 13000000:
1274        case 26000000:
1275                step_a = 0x2B;
1276                step_b = 0x0B;
1277                break;
1278        case 16800000:
1279                step_a = 0x1A;
1280                step_b = 0x09;
1281                break;
1282        case 19200000:
1283                step_a = 0x12;
1284                step_b = 0x08;
1285                break;
1286        default:
1287                pr_err("%s: Unexpected reference rate %lu\n",
1288                        __func__, parent_rate);
1289                WARN_ON(1);
1290                return -EINVAL;
1291        }
1292
1293        val = step_a << pll_params->stepa_shift;
1294        val |= step_b << pll_params->stepb_shift;
1295        writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1296
1297        return 0;
1298}
1299
1300static int _pll_ramp_calc_pll(struct clk_hw *hw,
1301                              struct tegra_clk_pll_freq_table *cfg,
1302                              unsigned long rate, unsigned long parent_rate)
1303{
1304        struct tegra_clk_pll *pll = to_clk_pll(hw);
1305        int err = 0;
1306
1307        err = _get_table_rate(hw, cfg, rate, parent_rate);
1308        if (err < 0)
1309                err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1310        else {
1311                if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1312                        WARN_ON(1);
1313                        err = -EINVAL;
1314                        goto out;
1315                }
1316        }
1317
1318        if (cfg->p >  pll->params->max_p)
1319                err = -EINVAL;
1320
1321out:
1322        return err;
1323}
1324
1325static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1326                                unsigned long parent_rate)
1327{
1328        struct tegra_clk_pll *pll = to_clk_pll(hw);
1329        struct tegra_clk_pll_freq_table cfg, old_cfg;
1330        unsigned long flags = 0;
1331        int ret;
1332
1333        ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1334        if (ret < 0)
1335                return ret;
1336
1337        if (pll->lock)
1338                spin_lock_irqsave(pll->lock, flags);
1339
1340        _get_pll_mnp(pll, &old_cfg);
1341        if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1342                cfg.p = old_cfg.p;
1343
1344        if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1345                ret = _program_pll(hw, &cfg, rate);
1346
1347        if (pll->lock)
1348                spin_unlock_irqrestore(pll->lock, flags);
1349
1350        return ret;
1351}
1352
1353static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1354                                unsigned long *prate)
1355{
1356        struct tegra_clk_pll *pll = to_clk_pll(hw);
1357        struct tegra_clk_pll_freq_table cfg;
1358        int ret, p_div;
1359        u64 output_rate = *prate;
1360
1361        ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1362        if (ret < 0)
1363                return ret;
1364
1365        p_div = _hw_to_p_div(hw, cfg.p);
1366        if (p_div < 0)
1367                return p_div;
1368
1369        if (pll->params->set_gain)
1370                pll->params->set_gain(&cfg);
1371
1372        output_rate *= cfg.n;
1373        do_div(output_rate, cfg.m * p_div);
1374
1375        return output_rate;
1376}
1377
1378static void _pllcx_strobe(struct tegra_clk_pll *pll)
1379{
1380        u32 val;
1381
1382        val = pll_readl_misc(pll);
1383        val |= PLLCX_MISC_STROBE;
1384        pll_writel_misc(val, pll);
1385        udelay(2);
1386
1387        val &= ~PLLCX_MISC_STROBE;
1388        pll_writel_misc(val, pll);
1389}
1390
1391static int clk_pllc_enable(struct clk_hw *hw)
1392{
1393        struct tegra_clk_pll *pll = to_clk_pll(hw);
1394        u32 val;
1395        int ret;
1396        unsigned long flags = 0;
1397
1398        if (clk_pll_is_enabled(hw))
1399                return 0;
1400
1401        if (pll->lock)
1402                spin_lock_irqsave(pll->lock, flags);
1403
1404        _clk_pll_enable(hw);
1405        udelay(2);
1406
1407        val = pll_readl_misc(pll);
1408        val &= ~PLLCX_MISC_RESET;
1409        pll_writel_misc(val, pll);
1410        udelay(2);
1411
1412        _pllcx_strobe(pll);
1413
1414        ret = clk_pll_wait_for_lock(pll);
1415
1416        if (pll->lock)
1417                spin_unlock_irqrestore(pll->lock, flags);
1418
1419        return ret;
1420}
1421
1422static void _clk_pllc_disable(struct clk_hw *hw)
1423{
1424        struct tegra_clk_pll *pll = to_clk_pll(hw);
1425        u32 val;
1426
1427        _clk_pll_disable(hw);
1428
1429        val = pll_readl_misc(pll);
1430        val |= PLLCX_MISC_RESET;
1431        pll_writel_misc(val, pll);
1432        udelay(2);
1433}
1434
1435static void clk_pllc_disable(struct clk_hw *hw)
1436{
1437        struct tegra_clk_pll *pll = to_clk_pll(hw);
1438        unsigned long flags = 0;
1439
1440        if (pll->lock)
1441                spin_lock_irqsave(pll->lock, flags);
1442
1443        _clk_pllc_disable(hw);
1444
1445        if (pll->lock)
1446                spin_unlock_irqrestore(pll->lock, flags);
1447}
1448
1449static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1450                                        unsigned long input_rate, u32 n)
1451{
1452        u32 val, n_threshold;
1453
1454        switch (input_rate) {
1455        case 12000000:
1456                n_threshold = 70;
1457                break;
1458        case 13000000:
1459        case 26000000:
1460                n_threshold = 71;
1461                break;
1462        case 16800000:
1463                n_threshold = 55;
1464                break;
1465        case 19200000:
1466                n_threshold = 48;
1467                break;
1468        default:
1469                pr_err("%s: Unexpected reference rate %lu\n",
1470                        __func__, input_rate);
1471                return -EINVAL;
1472        }
1473
1474        val = pll_readl_misc(pll);
1475        val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1476        val |= n <= n_threshold ?
1477                PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1478        pll_writel_misc(val, pll);
1479
1480        return 0;
1481}
1482
1483static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1484                                unsigned long parent_rate)
1485{
1486        struct tegra_clk_pll_freq_table cfg, old_cfg;
1487        struct tegra_clk_pll *pll = to_clk_pll(hw);
1488        unsigned long flags = 0;
1489        int state, ret = 0;
1490
1491        if (pll->lock)
1492                spin_lock_irqsave(pll->lock, flags);
1493
1494        ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1495        if (ret < 0)
1496                goto out;
1497
1498        _get_pll_mnp(pll, &old_cfg);
1499
1500        if (cfg.m != old_cfg.m) {
1501                WARN_ON(1);
1502                goto out;
1503        }
1504
1505        if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1506                goto out;
1507
1508        state = clk_pll_is_enabled(hw);
1509        if (state)
1510                _clk_pllc_disable(hw);
1511
1512        ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1513        if (ret < 0)
1514                goto out;
1515
1516        _update_pll_mnp(pll, &cfg);
1517
1518        if (state)
1519                ret = clk_pllc_enable(hw);
1520
1521out:
1522        if (pll->lock)
1523                spin_unlock_irqrestore(pll->lock, flags);
1524
1525        return ret;
1526}
1527
1528static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1529                             struct tegra_clk_pll_freq_table *cfg,
1530                             unsigned long rate, unsigned long parent_rate)
1531{
1532        u16 m, n;
1533        u64 output_rate = parent_rate;
1534
1535        m = _pll_fixed_mdiv(pll->params, parent_rate);
1536        n = rate * m / parent_rate;
1537
1538        output_rate *= n;
1539        do_div(output_rate, m);
1540
1541        if (cfg) {
1542                cfg->m = m;
1543                cfg->n = n;
1544        }
1545
1546        return output_rate;
1547}
1548
1549static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1550                                unsigned long parent_rate)
1551{
1552        struct tegra_clk_pll_freq_table cfg, old_cfg;
1553        struct tegra_clk_pll *pll = to_clk_pll(hw);
1554        unsigned long flags = 0;
1555        int state, ret = 0;
1556
1557        if (pll->lock)
1558                spin_lock_irqsave(pll->lock, flags);
1559
1560        _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1561        _get_pll_mnp(pll, &old_cfg);
1562        cfg.p = old_cfg.p;
1563
1564        if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1565                state = clk_pll_is_enabled(hw);
1566                if (state)
1567                        _clk_pll_disable(hw);
1568
1569                _update_pll_mnp(pll, &cfg);
1570
1571                if (state) {
1572                        _clk_pll_enable(hw);
1573                        ret = clk_pll_wait_for_lock(pll);
1574                }
1575        }
1576
1577        if (pll->lock)
1578                spin_unlock_irqrestore(pll->lock, flags);
1579
1580        return ret;
1581}
1582
1583static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1584                                         unsigned long parent_rate)
1585{
1586        struct tegra_clk_pll_freq_table cfg;
1587        struct tegra_clk_pll *pll = to_clk_pll(hw);
1588        u64 rate = parent_rate;
1589
1590        _get_pll_mnp(pll, &cfg);
1591
1592        rate *= cfg.n;
1593        do_div(rate, cfg.m);
1594
1595        return rate;
1596}
1597
1598static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1599                                 unsigned long *prate)
1600{
1601        struct tegra_clk_pll *pll = to_clk_pll(hw);
1602
1603        return _pllre_calc_rate(pll, NULL, rate, *prate);
1604}
1605
1606static int clk_plle_tegra114_enable(struct clk_hw *hw)
1607{
1608        struct tegra_clk_pll *pll = to_clk_pll(hw);
1609        struct tegra_clk_pll_freq_table sel;
1610        u32 val;
1611        int ret;
1612        unsigned long flags = 0;
1613        unsigned long input_rate;
1614
1615        input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1616
1617        if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1618                return -EINVAL;
1619
1620        if (pll->lock)
1621                spin_lock_irqsave(pll->lock, flags);
1622
1623        val = pll_readl_base(pll);
1624        val &= ~BIT(29); /* Disable lock override */
1625        pll_writel_base(val, pll);
1626
1627        val = pll_readl(pll->params->aux_reg, pll);
1628        val |= PLLE_AUX_ENABLE_SWCTL;
1629        val &= ~PLLE_AUX_SEQ_ENABLE;
1630        pll_writel(val, pll->params->aux_reg, pll);
1631        udelay(1);
1632
1633        val = pll_readl_misc(pll);
1634        val |= PLLE_MISC_LOCK_ENABLE;
1635        val |= PLLE_MISC_IDDQ_SW_CTRL;
1636        val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1637        val |= PLLE_MISC_PLLE_PTS;
1638        val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1639        pll_writel_misc(val, pll);
1640        udelay(5);
1641
1642        val = pll_readl(PLLE_SS_CTRL, pll);
1643        val |= PLLE_SS_DISABLE;
1644        pll_writel(val, PLLE_SS_CTRL, pll);
1645
1646        val = pll_readl_base(pll);
1647        val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1648                 divm_mask_shifted(pll));
1649        val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1650        val |= sel.m << divm_shift(pll);
1651        val |= sel.n << divn_shift(pll);
1652        val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1653        pll_writel_base(val, pll);
1654        udelay(1);
1655
1656        _clk_pll_enable(hw);
1657        ret = clk_pll_wait_for_lock(pll);
1658
1659        if (ret < 0)
1660                goto out;
1661
1662        val = pll_readl(PLLE_SS_CTRL, pll);
1663        val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1664        val &= ~PLLE_SS_COEFFICIENTS_MASK;
1665        val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1666        pll_writel(val, PLLE_SS_CTRL, pll);
1667        val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1668        pll_writel(val, PLLE_SS_CTRL, pll);
1669        udelay(1);
1670        val &= ~PLLE_SS_CNTL_INTERP_RESET;
1671        pll_writel(val, PLLE_SS_CTRL, pll);
1672        udelay(1);
1673
1674        /* Enable HW control of XUSB brick PLL */
1675        val = pll_readl_misc(pll);
1676        val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1677        pll_writel_misc(val, pll);
1678
1679        val = pll_readl(pll->params->aux_reg, pll);
1680        val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1681        val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1682        pll_writel(val, pll->params->aux_reg, pll);
1683        udelay(1);
1684        val |= PLLE_AUX_SEQ_ENABLE;
1685        pll_writel(val, pll->params->aux_reg, pll);
1686
1687        val = pll_readl(XUSBIO_PLL_CFG0, pll);
1688        val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1689                XUSBIO_PLL_CFG0_SEQ_START_STATE);
1690        val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1691                 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1692        pll_writel(val, XUSBIO_PLL_CFG0, pll);
1693        udelay(1);
1694        val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1695        pll_writel(val, XUSBIO_PLL_CFG0, pll);
1696
1697        /* Enable HW control of SATA PLL */
1698        val = pll_readl(SATA_PLL_CFG0, pll);
1699        val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1700        val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1701        val |= SATA_PLL_CFG0_SEQ_START_STATE;
1702        pll_writel(val, SATA_PLL_CFG0, pll);
1703
1704        udelay(1);
1705
1706        val = pll_readl(SATA_PLL_CFG0, pll);
1707        val |= SATA_PLL_CFG0_SEQ_ENABLE;
1708        pll_writel(val, SATA_PLL_CFG0, pll);
1709
1710out:
1711        if (pll->lock)
1712                spin_unlock_irqrestore(pll->lock, flags);
1713
1714        return ret;
1715}
1716
1717static void clk_plle_tegra114_disable(struct clk_hw *hw)
1718{
1719        struct tegra_clk_pll *pll = to_clk_pll(hw);
1720        unsigned long flags = 0;
1721        u32 val;
1722
1723        if (pll->lock)
1724                spin_lock_irqsave(pll->lock, flags);
1725
1726        _clk_pll_disable(hw);
1727
1728        val = pll_readl_misc(pll);
1729        val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1730        pll_writel_misc(val, pll);
1731        udelay(1);
1732
1733        if (pll->lock)
1734                spin_unlock_irqrestore(pll->lock, flags);
1735}
1736
1737static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1738{
1739        struct tegra_clk_pll *pll = to_clk_pll(hw);
1740        const struct utmi_clk_param *params = NULL;
1741        struct clk *osc = __clk_lookup("osc");
1742        unsigned long flags = 0, input_rate;
1743        unsigned int i;
1744        int ret = 0;
1745        u32 value;
1746
1747        if (!osc) {
1748                pr_err("%s: failed to get OSC clock\n", __func__);
1749                return -EINVAL;
1750        }
1751
1752        input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1753
1754        if (pll->lock)
1755                spin_lock_irqsave(pll->lock, flags);
1756
1757        if (!clk_pll_is_enabled(hw))
1758                _clk_pll_enable(hw);
1759
1760        ret = clk_pll_wait_for_lock(pll);
1761        if (ret < 0)
1762                goto out;
1763
1764        for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1765                if (input_rate == utmi_parameters[i].osc_frequency) {
1766                        params = &utmi_parameters[i];
1767                        break;
1768                }
1769        }
1770
1771        if (!params) {
1772                pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1773                       input_rate);
1774                ret = -EINVAL;
1775                goto out;
1776        }
1777
1778        value = pll_readl_base(pll);
1779        value &= ~PLLU_BASE_OVERRIDE;
1780        pll_writel_base(value, pll);
1781
1782        value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1783        /* Program UTMIP PLL stable and active counts */
1784        value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1785        value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1786        value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1787        value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1788        /* Remove power downs from UTMIP PLL control bits */
1789        value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1790        value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1791        value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1792        writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1793
1794        value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1795        /* Program UTMIP PLL delay and oscillator frequency counts */
1796        value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1797        value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1798        value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1799        value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1800        /* Remove power downs from UTMIP PLL control bits */
1801        value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1802        value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1803        value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1804        value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1805        writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1806
1807        /* Setup HW control of UTMIPLL */
1808        value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1809        value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1810        value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1811        value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1812        writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1813
1814        value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1815        value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1816        value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1817        writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1818
1819        udelay(1);
1820
1821        /*
1822         * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1823         * to USB2
1824         */
1825        value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1826        value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1827        value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1828        writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1829
1830        udelay(1);
1831
1832        /* Enable HW control of UTMIPLL */
1833        value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1834        value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1835        writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1836
1837out:
1838        if (pll->lock)
1839                spin_unlock_irqrestore(pll->lock, flags);
1840
1841        return ret;
1842}
1843
1844static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
1845{
1846        u32 val, val_aux;
1847
1848        /* ensure parent is set to pll_ref */
1849        val = pll_readl_base(pll);
1850        val_aux = pll_readl(pll->params->aux_reg, pll);
1851
1852        if (val & PLL_BASE_ENABLE) {
1853                if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1854                    (val_aux & PLLE_AUX_PLLP_SEL))
1855                        WARN(1, "pll_e enabled with unsupported parent %s\n",
1856                             (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1857                             "pll_re_vco");
1858        } else {
1859                val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1860                pll_writel(val_aux, pll->params->aux_reg, pll);
1861                fence_udelay(1, pll->clk_base);
1862        }
1863}
1864#endif
1865
1866static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1867                void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1868                spinlock_t *lock)
1869{
1870        struct tegra_clk_pll *pll;
1871
1872        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1873        if (!pll)
1874                return ERR_PTR(-ENOMEM);
1875
1876        pll->clk_base = clk_base;
1877        pll->pmc = pmc;
1878
1879        pll->params = pll_params;
1880        pll->lock = lock;
1881
1882        if (!pll_params->div_nmp)
1883                pll_params->div_nmp = &default_nmp;
1884
1885        return pll;
1886}
1887
1888static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1889                const char *name, const char *parent_name, unsigned long flags,
1890                const struct clk_ops *ops)
1891{
1892        struct clk_init_data init;
1893
1894        init.name = name;
1895        init.ops = ops;
1896        init.flags = flags;
1897        init.parent_names = (parent_name ? &parent_name : NULL);
1898        init.num_parents = (parent_name ? 1 : 0);
1899
1900        /* Default to _calc_rate if unspecified */
1901        if (!pll->params->calc_rate) {
1902                if (pll->params->flags & TEGRA_PLLM)
1903                        pll->params->calc_rate = _calc_dynamic_ramp_rate;
1904                else
1905                        pll->params->calc_rate = _calc_rate;
1906        }
1907
1908        if (pll->params->set_defaults)
1909                pll->params->set_defaults(pll);
1910
1911        /* Data in .init is copied by clk_register(), so stack variable OK */
1912        pll->hw.init = &init;
1913
1914        return clk_register(NULL, &pll->hw);
1915}
1916
1917struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1918                void __iomem *clk_base, void __iomem *pmc,
1919                unsigned long flags, struct tegra_clk_pll_params *pll_params,
1920                spinlock_t *lock)
1921{
1922        struct tegra_clk_pll *pll;
1923        struct clk *clk;
1924
1925        pll_params->flags |= TEGRA_PLL_BYPASS;
1926
1927        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1928        if (IS_ERR(pll))
1929                return ERR_CAST(pll);
1930
1931        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1932                                      &tegra_clk_pll_ops);
1933        if (IS_ERR(clk))
1934                kfree(pll);
1935
1936        return clk;
1937}
1938
1939static struct div_nmp pll_e_nmp = {
1940        .divn_shift = PLLE_BASE_DIVN_SHIFT,
1941        .divn_width = PLLE_BASE_DIVN_WIDTH,
1942        .divm_shift = PLLE_BASE_DIVM_SHIFT,
1943        .divm_width = PLLE_BASE_DIVM_WIDTH,
1944        .divp_shift = PLLE_BASE_DIVP_SHIFT,
1945        .divp_width = PLLE_BASE_DIVP_WIDTH,
1946};
1947
1948struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1949                void __iomem *clk_base, void __iomem *pmc,
1950                unsigned long flags, struct tegra_clk_pll_params *pll_params,
1951                spinlock_t *lock)
1952{
1953        struct tegra_clk_pll *pll;
1954        struct clk *clk;
1955
1956        pll_params->flags |= TEGRA_PLL_BYPASS;
1957
1958        if (!pll_params->div_nmp)
1959                pll_params->div_nmp = &pll_e_nmp;
1960
1961        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1962        if (IS_ERR(pll))
1963                return ERR_CAST(pll);
1964
1965        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1966                                      &tegra_clk_plle_ops);
1967        if (IS_ERR(clk))
1968                kfree(pll);
1969
1970        return clk;
1971}
1972
1973struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1974                void __iomem *clk_base, unsigned long flags,
1975                struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1976{
1977        struct tegra_clk_pll *pll;
1978        struct clk *clk;
1979
1980        pll_params->flags |= TEGRA_PLLU;
1981
1982        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1983        if (IS_ERR(pll))
1984                return ERR_CAST(pll);
1985
1986        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1987                                      &tegra_clk_pllu_ops);
1988        if (IS_ERR(clk))
1989                kfree(pll);
1990
1991        return clk;
1992}
1993
1994#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1995        defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1996        defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1997        defined(CONFIG_ARCH_TEGRA_210_SOC)
1998static const struct clk_ops tegra_clk_pllxc_ops = {
1999        .is_enabled = clk_pll_is_enabled,
2000        .enable = clk_pll_enable,
2001        .disable = clk_pll_disable,
2002        .recalc_rate = clk_pll_recalc_rate,
2003        .round_rate = clk_pll_ramp_round_rate,
2004        .set_rate = clk_pllxc_set_rate,
2005};
2006
2007static const struct clk_ops tegra_clk_pllc_ops = {
2008        .is_enabled = clk_pll_is_enabled,
2009        .enable = clk_pllc_enable,
2010        .disable = clk_pllc_disable,
2011        .recalc_rate = clk_pll_recalc_rate,
2012        .round_rate = clk_pll_ramp_round_rate,
2013        .set_rate = clk_pllc_set_rate,
2014};
2015
2016static const struct clk_ops tegra_clk_pllre_ops = {
2017        .is_enabled = clk_pll_is_enabled,
2018        .enable = clk_pll_enable,
2019        .disable = clk_pll_disable,
2020        .recalc_rate = clk_pllre_recalc_rate,
2021        .round_rate = clk_pllre_round_rate,
2022        .set_rate = clk_pllre_set_rate,
2023};
2024
2025static const struct clk_ops tegra_clk_plle_tegra114_ops = {
2026        .is_enabled =  clk_pll_is_enabled,
2027        .enable = clk_plle_tegra114_enable,
2028        .disable = clk_plle_tegra114_disable,
2029        .recalc_rate = clk_pll_recalc_rate,
2030};
2031
2032static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
2033        .is_enabled =  clk_pll_is_enabled,
2034        .enable = clk_pllu_tegra114_enable,
2035        .disable = clk_pll_disable,
2036        .recalc_rate = clk_pll_recalc_rate,
2037};
2038
2039struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
2040                          void __iomem *clk_base, void __iomem *pmc,
2041                          unsigned long flags,
2042                          struct tegra_clk_pll_params *pll_params,
2043                          spinlock_t *lock)
2044{
2045        struct tegra_clk_pll *pll;
2046        struct clk *clk, *parent;
2047        unsigned long parent_rate;
2048        u32 val, val_iddq;
2049
2050        parent = __clk_lookup(parent_name);
2051        if (!parent) {
2052                WARN(1, "parent clk %s of %s must be registered first\n",
2053                        parent_name, name);
2054                return ERR_PTR(-EINVAL);
2055        }
2056
2057        if (!pll_params->pdiv_tohw)
2058                return ERR_PTR(-EINVAL);
2059
2060        parent_rate = clk_get_rate(parent);
2061
2062        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2063
2064        if (pll_params->adjust_vco)
2065                pll_params->vco_min = pll_params->adjust_vco(pll_params,
2066                                                             parent_rate);
2067
2068        /*
2069         * If the pll has a set_defaults callback, it will take care of
2070         * configuring dynamic ramping and setting IDDQ in that path.
2071         */
2072        if (!pll_params->set_defaults) {
2073                int err;
2074
2075                err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2076                if (err)
2077                        return ERR_PTR(err);
2078
2079                val = readl_relaxed(clk_base + pll_params->base_reg);
2080                val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2081
2082                if (val & PLL_BASE_ENABLE)
2083                        WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2084                else {
2085                        val_iddq |= BIT(pll_params->iddq_bit_idx);
2086                        writel_relaxed(val_iddq,
2087                                       clk_base + pll_params->iddq_reg);
2088                }
2089        }
2090
2091        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2092        if (IS_ERR(pll))
2093                return ERR_CAST(pll);
2094
2095        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2096                                      &tegra_clk_pllxc_ops);
2097        if (IS_ERR(clk))
2098                kfree(pll);
2099
2100        return clk;
2101}
2102
2103struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2104                          void __iomem *clk_base, void __iomem *pmc,
2105                          unsigned long flags,
2106                          struct tegra_clk_pll_params *pll_params,
2107                          spinlock_t *lock, unsigned long parent_rate)
2108{
2109        u32 val;
2110        struct tegra_clk_pll *pll;
2111        struct clk *clk;
2112
2113        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2114
2115        if (pll_params->adjust_vco)
2116                pll_params->vco_min = pll_params->adjust_vco(pll_params,
2117                                                             parent_rate);
2118
2119        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2120        if (IS_ERR(pll))
2121                return ERR_CAST(pll);
2122
2123        /* program minimum rate by default */
2124
2125        val = pll_readl_base(pll);
2126        if (val & PLL_BASE_ENABLE)
2127                WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2128                                BIT(pll_params->iddq_bit_idx));
2129        else {
2130                int m;
2131
2132                m = _pll_fixed_mdiv(pll_params, parent_rate);
2133                val = m << divm_shift(pll);
2134                val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2135                pll_writel_base(val, pll);
2136        }
2137
2138        /* disable lock override */
2139
2140        val = pll_readl_misc(pll);
2141        val &= ~BIT(29);
2142        pll_writel_misc(val, pll);
2143
2144        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2145                                      &tegra_clk_pllre_ops);
2146        if (IS_ERR(clk))
2147                kfree(pll);
2148
2149        return clk;
2150}
2151
2152struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2153                          void __iomem *clk_base, void __iomem *pmc,
2154                          unsigned long flags,
2155                          struct tegra_clk_pll_params *pll_params,
2156                          spinlock_t *lock)
2157{
2158        struct tegra_clk_pll *pll;
2159        struct clk *clk, *parent;
2160        unsigned long parent_rate;
2161
2162        if (!pll_params->pdiv_tohw)
2163                return ERR_PTR(-EINVAL);
2164
2165        parent = __clk_lookup(parent_name);
2166        if (!parent) {
2167                WARN(1, "parent clk %s of %s must be registered first\n",
2168                        parent_name, name);
2169                return ERR_PTR(-EINVAL);
2170        }
2171
2172        parent_rate = clk_get_rate(parent);
2173
2174        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2175
2176        if (pll_params->adjust_vco)
2177                pll_params->vco_min = pll_params->adjust_vco(pll_params,
2178                                                             parent_rate);
2179
2180        pll_params->flags |= TEGRA_PLL_BYPASS;
2181        pll_params->flags |= TEGRA_PLLM;
2182        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2183        if (IS_ERR(pll))
2184                return ERR_CAST(pll);
2185
2186        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2187                                      &tegra_clk_pll_ops);
2188        if (IS_ERR(clk))
2189                kfree(pll);
2190
2191        return clk;
2192}
2193
2194struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2195                          void __iomem *clk_base, void __iomem *pmc,
2196                          unsigned long flags,
2197                          struct tegra_clk_pll_params *pll_params,
2198                          spinlock_t *lock)
2199{
2200        struct clk *parent, *clk;
2201        const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2202        struct tegra_clk_pll *pll;
2203        struct tegra_clk_pll_freq_table cfg;
2204        unsigned long parent_rate;
2205
2206        if (!p_tohw)
2207                return ERR_PTR(-EINVAL);
2208
2209        parent = __clk_lookup(parent_name);
2210        if (!parent) {
2211                WARN(1, "parent clk %s of %s must be registered first\n",
2212                        parent_name, name);
2213                return ERR_PTR(-EINVAL);
2214        }
2215
2216        parent_rate = clk_get_rate(parent);
2217
2218        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2219
2220        pll_params->flags |= TEGRA_PLL_BYPASS;
2221        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2222        if (IS_ERR(pll))
2223                return ERR_CAST(pll);
2224
2225        /*
2226         * Most of PLLC register fields are shadowed, and can not be read
2227         * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2228         * Initialize PLL to default state: disabled, reset; shadow registers
2229         * loaded with default parameters; dividers are preset for half of
2230         * minimum VCO rate (the latter assured that shadowed divider settings
2231         * are within supported range).
2232         */
2233
2234        cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2235        cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2236
2237        while (p_tohw->pdiv) {
2238                if (p_tohw->pdiv == 2) {
2239                        cfg.p = p_tohw->hw_val;
2240                        break;
2241                }
2242                p_tohw++;
2243        }
2244
2245        if (!p_tohw->pdiv) {
2246                WARN_ON(1);
2247                return ERR_PTR(-EINVAL);
2248        }
2249
2250        pll_writel_base(0, pll);
2251        _update_pll_mnp(pll, &cfg);
2252
2253        pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2254        pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2255        pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2256        pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2257
2258        _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2259
2260        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2261                                      &tegra_clk_pllc_ops);
2262        if (IS_ERR(clk))
2263                kfree(pll);
2264
2265        return clk;
2266}
2267
2268struct clk *tegra_clk_register_plle_tegra114(const char *name,
2269                                const char *parent_name,
2270                                void __iomem *clk_base, unsigned long flags,
2271                                struct tegra_clk_pll_params *pll_params,
2272                                spinlock_t *lock)
2273{
2274        struct tegra_clk_pll *pll;
2275        struct clk *clk;
2276
2277        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2278        if (IS_ERR(pll))
2279                return ERR_CAST(pll);
2280
2281        _clk_plle_tegra_init_parent(pll);
2282
2283        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2284                                      &tegra_clk_plle_tegra114_ops);
2285        if (IS_ERR(clk))
2286                kfree(pll);
2287
2288        return clk;
2289}
2290
2291struct clk *
2292tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2293                                 void __iomem *clk_base, unsigned long flags,
2294                                 struct tegra_clk_pll_params *pll_params,
2295                                 spinlock_t *lock)
2296{
2297        struct tegra_clk_pll *pll;
2298        struct clk *clk;
2299
2300        pll_params->flags |= TEGRA_PLLU;
2301
2302        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2303        if (IS_ERR(pll))
2304                return ERR_CAST(pll);
2305
2306        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2307                                      &tegra_clk_pllu_tegra114_ops);
2308        if (IS_ERR(clk))
2309                kfree(pll);
2310
2311        return clk;
2312}
2313#endif
2314
2315#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2316static const struct clk_ops tegra_clk_pllss_ops = {
2317        .is_enabled = clk_pll_is_enabled,
2318        .enable = clk_pll_enable,
2319        .disable = clk_pll_disable,
2320        .recalc_rate = clk_pll_recalc_rate,
2321        .round_rate = clk_pll_ramp_round_rate,
2322        .set_rate = clk_pllxc_set_rate,
2323        .restore_context = tegra_clk_pll_restore_context,
2324};
2325
2326struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2327                                void __iomem *clk_base, unsigned long flags,
2328                                struct tegra_clk_pll_params *pll_params,
2329                                spinlock_t *lock)
2330{
2331        struct tegra_clk_pll *pll;
2332        struct clk *clk, *parent;
2333        struct tegra_clk_pll_freq_table cfg;
2334        unsigned long parent_rate;
2335        u32 val, val_iddq;
2336        int i;
2337
2338        if (!pll_params->div_nmp)
2339                return ERR_PTR(-EINVAL);
2340
2341        parent = __clk_lookup(parent_name);
2342        if (!parent) {
2343                WARN(1, "parent clk %s of %s must be registered first\n",
2344                        parent_name, name);
2345                return ERR_PTR(-EINVAL);
2346        }
2347
2348        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2349        if (IS_ERR(pll))
2350                return ERR_CAST(pll);
2351
2352        val = pll_readl_base(pll);
2353        val &= ~PLLSS_REF_SRC_SEL_MASK;
2354        pll_writel_base(val, pll);
2355
2356        parent_rate = clk_get_rate(parent);
2357
2358        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2359
2360        /* initialize PLL to minimum rate */
2361
2362        cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2363        cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2364
2365        for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2366                ;
2367        if (!i) {
2368                kfree(pll);
2369                return ERR_PTR(-EINVAL);
2370        }
2371
2372        cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2373
2374        _update_pll_mnp(pll, &cfg);
2375
2376        pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2377        pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2378        pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2379        pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2380
2381        val = pll_readl_base(pll);
2382        val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2383        if (val & PLL_BASE_ENABLE) {
2384                if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2385                        WARN(1, "%s is on but IDDQ set\n", name);
2386                        kfree(pll);
2387                        return ERR_PTR(-EINVAL);
2388                }
2389        } else {
2390                val_iddq |= BIT(pll_params->iddq_bit_idx);
2391                writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2392        }
2393
2394        val &= ~PLLSS_LOCK_OVERRIDE;
2395        pll_writel_base(val, pll);
2396
2397        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2398                                        &tegra_clk_pllss_ops);
2399
2400        if (IS_ERR(clk))
2401                kfree(pll);
2402
2403        return clk;
2404}
2405#endif
2406
2407#if defined(CONFIG_ARCH_TEGRA_210_SOC)
2408struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2409                          const char *parent_name, void __iomem *clk_base,
2410                          void __iomem *pmc, unsigned long flags,
2411                          struct tegra_clk_pll_params *pll_params,
2412                          spinlock_t *lock, unsigned long parent_rate)
2413{
2414        struct tegra_clk_pll *pll;
2415        struct clk *clk;
2416
2417        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2418
2419        if (pll_params->adjust_vco)
2420                pll_params->vco_min = pll_params->adjust_vco(pll_params,
2421                                                             parent_rate);
2422
2423        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2424        if (IS_ERR(pll))
2425                return ERR_CAST(pll);
2426
2427        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2428                                      &tegra_clk_pll_ops);
2429        if (IS_ERR(clk))
2430                kfree(pll);
2431
2432        return clk;
2433}
2434
2435static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2436{
2437        struct tegra_clk_pll *pll = to_clk_pll(hw);
2438        u32 val;
2439
2440        val = pll_readl_base(pll);
2441
2442        return val & PLLE_BASE_ENABLE ? 1 : 0;
2443}
2444
2445static int clk_plle_tegra210_enable(struct clk_hw *hw)
2446{
2447        struct tegra_clk_pll *pll = to_clk_pll(hw);
2448        struct tegra_clk_pll_freq_table sel;
2449        u32 val;
2450        int ret = 0;
2451        unsigned long flags = 0;
2452        unsigned long input_rate;
2453
2454        if (clk_plle_tegra210_is_enabled(hw))
2455                return 0;
2456
2457        input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2458
2459        if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2460                return -EINVAL;
2461
2462        if (pll->lock)
2463                spin_lock_irqsave(pll->lock, flags);
2464
2465        val = pll_readl(pll->params->aux_reg, pll);
2466        if (val & PLLE_AUX_SEQ_ENABLE)
2467                goto out;
2468
2469        val = pll_readl_base(pll);
2470        val &= ~BIT(30); /* Disable lock override */
2471        pll_writel_base(val, pll);
2472
2473        val = pll_readl_misc(pll);
2474        val |= PLLE_MISC_LOCK_ENABLE;
2475        val |= PLLE_MISC_IDDQ_SW_CTRL;
2476        val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2477        val |= PLLE_MISC_PLLE_PTS;
2478        val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2479        pll_writel_misc(val, pll);
2480        udelay(5);
2481
2482        val = pll_readl(PLLE_SS_CTRL, pll);
2483        val |= PLLE_SS_DISABLE;
2484        pll_writel(val, PLLE_SS_CTRL, pll);
2485
2486        val = pll_readl_base(pll);
2487        val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2488                 divm_mask_shifted(pll));
2489        val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2490        val |= sel.m << divm_shift(pll);
2491        val |= sel.n << divn_shift(pll);
2492        val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2493        pll_writel_base(val, pll);
2494        udelay(1);
2495
2496        val = pll_readl_base(pll);
2497        val |= PLLE_BASE_ENABLE;
2498        pll_writel_base(val, pll);
2499
2500        ret = clk_pll_wait_for_lock(pll);
2501
2502        if (ret < 0)
2503                goto out;
2504
2505        val = pll_readl(PLLE_SS_CTRL, pll);
2506        val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2507        val &= ~PLLE_SS_COEFFICIENTS_MASK;
2508        val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2509        pll_writel(val, PLLE_SS_CTRL, pll);
2510        val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2511        pll_writel(val, PLLE_SS_CTRL, pll);
2512        udelay(1);
2513        val &= ~PLLE_SS_CNTL_INTERP_RESET;
2514        pll_writel(val, PLLE_SS_CTRL, pll);
2515        udelay(1);
2516
2517out:
2518        if (pll->lock)
2519                spin_unlock_irqrestore(pll->lock, flags);
2520
2521        return ret;
2522}
2523
2524static void clk_plle_tegra210_disable(struct clk_hw *hw)
2525{
2526        struct tegra_clk_pll *pll = to_clk_pll(hw);
2527        unsigned long flags = 0;
2528        u32 val;
2529
2530        if (pll->lock)
2531                spin_lock_irqsave(pll->lock, flags);
2532
2533        /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2534        val = pll_readl(pll->params->aux_reg, pll);
2535        if (val & PLLE_AUX_SEQ_ENABLE)
2536                goto out;
2537
2538        val = pll_readl_base(pll);
2539        val &= ~PLLE_BASE_ENABLE;
2540        pll_writel_base(val, pll);
2541
2542        val = pll_readl(pll->params->aux_reg, pll);
2543        val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2544        pll_writel(val, pll->params->aux_reg, pll);
2545
2546        val = pll_readl_misc(pll);
2547        val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2548        pll_writel_misc(val, pll);
2549        udelay(1);
2550
2551out:
2552        if (pll->lock)
2553                spin_unlock_irqrestore(pll->lock, flags);
2554}
2555
2556static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
2557{
2558        struct tegra_clk_pll *pll = to_clk_pll(hw);
2559
2560        _clk_plle_tegra_init_parent(pll);
2561}
2562
2563static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2564        .is_enabled =  clk_plle_tegra210_is_enabled,
2565        .enable = clk_plle_tegra210_enable,
2566        .disable = clk_plle_tegra210_disable,
2567        .recalc_rate = clk_pll_recalc_rate,
2568        .restore_context = tegra_clk_plle_t210_restore_context,
2569};
2570
2571struct clk *tegra_clk_register_plle_tegra210(const char *name,
2572                                const char *parent_name,
2573                                void __iomem *clk_base, unsigned long flags,
2574                                struct tegra_clk_pll_params *pll_params,
2575                                spinlock_t *lock)
2576{
2577        struct tegra_clk_pll *pll;
2578        struct clk *clk;
2579
2580        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2581        if (IS_ERR(pll))
2582                return ERR_CAST(pll);
2583
2584        _clk_plle_tegra_init_parent(pll);
2585
2586        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2587                                      &tegra_clk_plle_tegra210_ops);
2588        if (IS_ERR(clk))
2589                kfree(pll);
2590
2591        return clk;
2592}
2593
2594struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2595                        const char *parent_name, void __iomem *clk_base,
2596                        void __iomem *pmc, unsigned long flags,
2597                        struct tegra_clk_pll_params *pll_params,
2598                        spinlock_t *lock)
2599{
2600        struct clk *parent, *clk;
2601        const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2602        struct tegra_clk_pll *pll;
2603        unsigned long parent_rate;
2604
2605        if (!p_tohw)
2606                return ERR_PTR(-EINVAL);
2607
2608        parent = __clk_lookup(parent_name);
2609        if (!parent) {
2610                WARN(1, "parent clk %s of %s must be registered first\n",
2611                        name, parent_name);
2612                return ERR_PTR(-EINVAL);
2613        }
2614
2615        parent_rate = clk_get_rate(parent);
2616
2617        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2618
2619        if (pll_params->adjust_vco)
2620                pll_params->vco_min = pll_params->adjust_vco(pll_params,
2621                                                             parent_rate);
2622
2623        pll_params->flags |= TEGRA_PLL_BYPASS;
2624        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2625        if (IS_ERR(pll))
2626                return ERR_CAST(pll);
2627
2628        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2629                                      &tegra_clk_pll_ops);
2630        if (IS_ERR(clk))
2631                kfree(pll);
2632
2633        return clk;
2634}
2635
2636struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2637                                const char *parent_name, void __iomem *clk_base,
2638                                unsigned long flags,
2639                                struct tegra_clk_pll_params *pll_params,
2640                                spinlock_t *lock)
2641{
2642        struct tegra_clk_pll *pll;
2643        struct clk *clk, *parent;
2644        unsigned long parent_rate;
2645        u32 val;
2646
2647        if (!pll_params->div_nmp)
2648                return ERR_PTR(-EINVAL);
2649
2650        parent = __clk_lookup(parent_name);
2651        if (!parent) {
2652                WARN(1, "parent clk %s of %s must be registered first\n",
2653                        name, parent_name);
2654                return ERR_PTR(-EINVAL);
2655        }
2656
2657        val = readl_relaxed(clk_base + pll_params->base_reg);
2658        if (val & PLLSS_REF_SRC_SEL_MASK) {
2659                WARN(1, "not supported reference clock for %s\n", name);
2660                return ERR_PTR(-EINVAL);
2661        }
2662
2663        parent_rate = clk_get_rate(parent);
2664
2665        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2666
2667        if (pll_params->adjust_vco)
2668                pll_params->vco_min = pll_params->adjust_vco(pll_params,
2669                                                             parent_rate);
2670
2671        pll_params->flags |= TEGRA_PLL_BYPASS;
2672        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2673        if (IS_ERR(pll))
2674                return ERR_CAST(pll);
2675
2676        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2677                                        &tegra_clk_pll_ops);
2678
2679        if (IS_ERR(clk))
2680                kfree(pll);
2681
2682        return clk;
2683}
2684
2685struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2686                          void __iomem *clk_base, void __iomem *pmc,
2687                          unsigned long flags,
2688                          struct tegra_clk_pll_params *pll_params,
2689                          spinlock_t *lock)
2690{
2691        struct tegra_clk_pll *pll;
2692        struct clk *clk, *parent;
2693        unsigned long parent_rate;
2694
2695        if (!pll_params->pdiv_tohw)
2696                return ERR_PTR(-EINVAL);
2697
2698        parent = __clk_lookup(parent_name);
2699        if (!parent) {
2700                WARN(1, "parent clk %s of %s must be registered first\n",
2701                        parent_name, name);
2702                return ERR_PTR(-EINVAL);
2703        }
2704
2705        parent_rate = clk_get_rate(parent);
2706
2707        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2708
2709        if (pll_params->adjust_vco)
2710                pll_params->vco_min = pll_params->adjust_vco(pll_params,
2711                                                             parent_rate);
2712
2713        pll_params->flags |= TEGRA_PLL_BYPASS;
2714        pll_params->flags |= TEGRA_PLLMB;
2715        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2716        if (IS_ERR(pll))
2717                return ERR_CAST(pll);
2718
2719        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2720                                      &tegra_clk_pll_ops);
2721        if (IS_ERR(clk))
2722                kfree(pll);
2723
2724        return clk;
2725}
2726
2727#endif
2728