linux/drivers/clk/mvebu/dove.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Marvell Dove SoC clocks
   4 *
   5 * Copyright (C) 2012 Marvell
   6 *
   7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   9 * Andrew Lunn <andrew@lunn.ch>
  10 *
  11 */
  12
  13#include <linux/kernel.h>
  14#include <linux/clk-provider.h>
  15#include <linux/io.h>
  16#include <linux/of.h>
  17#include "common.h"
  18#include "dove-divider.h"
  19
  20/*
  21 * Core Clocks
  22 *
  23 * Dove PLL sample-at-reset configuration
  24 *
  25 * SAR0[8:5]   : CPU frequency
  26 *               5  = 1000 MHz
  27 *               6  =  933 MHz
  28 *               7  =  933 MHz
  29 *               8  =  800 MHz
  30 *               9  =  800 MHz
  31 *               10 =  800 MHz
  32 *               11 = 1067 MHz
  33 *               12 =  667 MHz
  34 *               13 =  533 MHz
  35 *               14 =  400 MHz
  36 *               15 =  333 MHz
  37 *               others reserved.
  38 *
  39 * SAR0[11:9]  : CPU to L2 Clock divider ratio
  40 *               0 = (1/1) * CPU
  41 *               2 = (1/2) * CPU
  42 *               4 = (1/3) * CPU
  43 *               6 = (1/4) * CPU
  44 *               others reserved.
  45 *
  46 * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
  47 *               0  = (1/1) * CPU
  48 *               2  = (1/2) * CPU
  49 *               3  = (2/5) * CPU
  50 *               4  = (1/3) * CPU
  51 *               6  = (1/4) * CPU
  52 *               8  = (1/5) * CPU
  53 *               10 = (1/6) * CPU
  54 *               12 = (1/7) * CPU
  55 *               14 = (1/8) * CPU
  56 *               15 = (1/10) * CPU
  57 *               others reserved.
  58 *
  59 * SAR0[24:23] : TCLK frequency
  60 *               0 = 166 MHz
  61 *               1 = 125 MHz
  62 *               others reserved.
  63 */
  64
  65#define SAR_DOVE_CPU_FREQ               5
  66#define SAR_DOVE_CPU_FREQ_MASK          0xf
  67#define SAR_DOVE_L2_RATIO               9
  68#define SAR_DOVE_L2_RATIO_MASK          0x7
  69#define SAR_DOVE_DDR_RATIO              12
  70#define SAR_DOVE_DDR_RATIO_MASK         0xf
  71#define SAR_DOVE_TCLK_FREQ              23
  72#define SAR_DOVE_TCLK_FREQ_MASK         0x3
  73
  74enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
  75
  76static const struct coreclk_ratio dove_coreclk_ratios[] __initconst = {
  77        { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
  78        { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
  79};
  80
  81static const u32 dove_tclk_freqs[] __initconst = {
  82        166666667,
  83        125000000,
  84        0, 0
  85};
  86
  87static u32 __init dove_get_tclk_freq(void __iomem *sar)
  88{
  89        u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
  90                SAR_DOVE_TCLK_FREQ_MASK;
  91        return dove_tclk_freqs[opt];
  92}
  93
  94static const u32 dove_cpu_freqs[] __initconst = {
  95        0, 0, 0, 0, 0,
  96        1000000000,
  97        933333333, 933333333,
  98        800000000, 800000000, 800000000,
  99        1066666667,
 100        666666667,
 101        533333333,
 102        400000000,
 103        333333333
 104};
 105
 106static u32 __init dove_get_cpu_freq(void __iomem *sar)
 107{
 108        u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
 109                SAR_DOVE_CPU_FREQ_MASK;
 110        return dove_cpu_freqs[opt];
 111}
 112
 113static const int dove_cpu_l2_ratios[8][2] __initconst = {
 114        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
 115        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
 116};
 117
 118static const int dove_cpu_ddr_ratios[16][2] __initconst = {
 119        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
 120        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
 121        { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
 122        { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
 123};
 124
 125static void __init dove_get_clk_ratio(
 126        void __iomem *sar, int id, int *mult, int *div)
 127{
 128        switch (id) {
 129        case DOVE_CPU_TO_L2:
 130        {
 131                u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
 132                        SAR_DOVE_L2_RATIO_MASK;
 133                *mult = dove_cpu_l2_ratios[opt][0];
 134                *div = dove_cpu_l2_ratios[opt][1];
 135                break;
 136        }
 137        case DOVE_CPU_TO_DDR:
 138        {
 139                u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
 140                        SAR_DOVE_DDR_RATIO_MASK;
 141                *mult = dove_cpu_ddr_ratios[opt][0];
 142                *div = dove_cpu_ddr_ratios[opt][1];
 143                break;
 144        }
 145        }
 146}
 147
 148static const struct coreclk_soc_desc dove_coreclks = {
 149        .get_tclk_freq = dove_get_tclk_freq,
 150        .get_cpu_freq = dove_get_cpu_freq,
 151        .get_clk_ratio = dove_get_clk_ratio,
 152        .ratios = dove_coreclk_ratios,
 153        .num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
 154};
 155
 156/*
 157 * Clock Gating Control
 158 */
 159
 160static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = {
 161        { "usb0", NULL, 0, 0 },
 162        { "usb1", NULL, 1, 0 },
 163        { "ge", "gephy", 2, 0 },
 164        { "sata", NULL, 3, 0 },
 165        { "pex0", NULL, 4, 0 },
 166        { "pex1", NULL, 5, 0 },
 167        { "sdio0", NULL, 8, 0 },
 168        { "sdio1", NULL, 9, 0 },
 169        { "nand", NULL, 10, 0 },
 170        { "camera", NULL, 11, 0 },
 171        { "i2s0", NULL, 12, 0 },
 172        { "i2s1", NULL, 13, 0 },
 173        { "crypto", NULL, 15, 0 },
 174        { "ac97", NULL, 21, 0 },
 175        { "pdma", NULL, 22, 0 },
 176        { "xor0", NULL, 23, 0 },
 177        { "xor1", NULL, 24, 0 },
 178        { "gephy", NULL, 30, 0 },
 179        { }
 180};
 181
 182static void __init dove_clk_init(struct device_node *np)
 183{
 184        struct device_node *cgnp =
 185                of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock");
 186        struct device_node *ddnp =
 187                of_find_compatible_node(NULL, NULL, "marvell,dove-divider-clock");
 188
 189        mvebu_coreclk_setup(np, &dove_coreclks);
 190
 191        if (ddnp) {
 192                dove_divider_clk_init(ddnp);
 193                of_node_put(ddnp);
 194        }
 195
 196        if (cgnp) {
 197                mvebu_clk_gating_setup(cgnp, dove_gating_desc);
 198                of_node_put(cgnp);
 199        }
 200}
 201CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);
 202