linux/drivers/clk/ingenic/jz4725b-cgu.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Ingenic JZ4725B SoC CGU driver
   4 *
   5 * Copyright (C) 2018 Paul Cercueil
   6 * Author: Paul Cercueil <paul@crapouillou.net>
   7 */
   8
   9#include <linux/clk-provider.h>
  10#include <linux/delay.h>
  11#include <linux/of.h>
  12
  13#include <dt-bindings/clock/jz4725b-cgu.h>
  14
  15#include "cgu.h"
  16#include "pm.h"
  17
  18/* CGU register offsets */
  19#define CGU_REG_CPCCR           0x00
  20#define CGU_REG_LCR             0x04
  21#define CGU_REG_CPPCR           0x10
  22#define CGU_REG_CLKGR           0x20
  23#define CGU_REG_OPCR            0x24
  24#define CGU_REG_I2SCDR          0x60
  25#define CGU_REG_LPCDR           0x64
  26#define CGU_REG_MSCCDR          0x68
  27#define CGU_REG_SSICDR          0x74
  28#define CGU_REG_CIMCDR          0x78
  29
  30/* bits within the LCR register */
  31#define LCR_SLEEP               BIT(0)
  32
  33static struct ingenic_cgu *cgu;
  34
  35static const s8 pll_od_encoding[4] = {
  36        0x0, 0x1, -1, 0x3,
  37};
  38
  39static const u8 jz4725b_cgu_cpccr_div_table[] = {
  40        1, 2, 3, 4, 6, 8,
  41};
  42
  43static const u8 jz4725b_cgu_pll_half_div_table[] = {
  44        2, 1,
  45};
  46
  47static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
  48
  49        /* External clocks */
  50
  51        [JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
  52        [JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
  53
  54        [JZ4725B_CLK_PLL] = {
  55                "pll", CGU_CLK_PLL,
  56                .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
  57                .pll = {
  58                        .reg = CGU_REG_CPPCR,
  59                        .rate_multiplier = 1,
  60                        .m_shift = 23,
  61                        .m_bits = 9,
  62                        .m_offset = 2,
  63                        .n_shift = 18,
  64                        .n_bits = 5,
  65                        .n_offset = 2,
  66                        .od_shift = 16,
  67                        .od_bits = 2,
  68                        .od_max = 4,
  69                        .od_encoding = pll_od_encoding,
  70                        .stable_bit = 10,
  71                        .bypass_reg = CGU_REG_CPPCR,
  72                        .bypass_bit = 9,
  73                        .enable_bit = 8,
  74                },
  75        },
  76
  77        /* Muxes & dividers */
  78
  79        [JZ4725B_CLK_PLL_HALF] = {
  80                "pll half", CGU_CLK_DIV,
  81                .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
  82                .div = {
  83                        CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
  84                        jz4725b_cgu_pll_half_div_table,
  85                },
  86        },
  87
  88        [JZ4725B_CLK_CCLK] = {
  89                "cclk", CGU_CLK_DIV,
  90                .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
  91                .div = {
  92                        CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
  93                        jz4725b_cgu_cpccr_div_table,
  94                },
  95        },
  96
  97        [JZ4725B_CLK_HCLK] = {
  98                "hclk", CGU_CLK_DIV,
  99                .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
 100                .div = {
 101                        CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
 102                        jz4725b_cgu_cpccr_div_table,
 103                },
 104        },
 105
 106        [JZ4725B_CLK_PCLK] = {
 107                "pclk", CGU_CLK_DIV,
 108                .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
 109                .div = {
 110                        CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
 111                        jz4725b_cgu_cpccr_div_table,
 112                },
 113        },
 114
 115        [JZ4725B_CLK_MCLK] = {
 116                "mclk", CGU_CLK_DIV,
 117                .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
 118                .div = {
 119                        CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
 120                        jz4725b_cgu_cpccr_div_table,
 121                },
 122        },
 123
 124        [JZ4725B_CLK_IPU] = {
 125                "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
 126                .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
 127                .div = {
 128                        CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
 129                        jz4725b_cgu_cpccr_div_table,
 130                },
 131                .gate = { CGU_REG_CLKGR, 13 },
 132        },
 133
 134        [JZ4725B_CLK_LCD] = {
 135                "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
 136                .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
 137                .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
 138                .gate = { CGU_REG_CLKGR, 9 },
 139        },
 140
 141        [JZ4725B_CLK_I2S] = {
 142                "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
 143                .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
 144                .mux = { CGU_REG_CPCCR, 31, 1 },
 145                .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
 146                .gate = { CGU_REG_CLKGR, 6 },
 147        },
 148
 149        [JZ4725B_CLK_SPI] = {
 150                "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
 151                .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
 152                .mux = { CGU_REG_SSICDR, 31, 1 },
 153                .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
 154                .gate = { CGU_REG_CLKGR, 4 },
 155        },
 156
 157        [JZ4725B_CLK_MMC_MUX] = {
 158                "mmc_mux", CGU_CLK_DIV,
 159                .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
 160                .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
 161        },
 162
 163        [JZ4725B_CLK_UDC] = {
 164                "udc", CGU_CLK_MUX | CGU_CLK_DIV,
 165                .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
 166                .mux = { CGU_REG_CPCCR, 29, 1 },
 167                .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
 168        },
 169
 170        /* Gate-only clocks */
 171
 172        [JZ4725B_CLK_UART] = {
 173                "uart", CGU_CLK_GATE,
 174                .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
 175                .gate = { CGU_REG_CLKGR, 0 },
 176        },
 177
 178        [JZ4725B_CLK_DMA] = {
 179                "dma", CGU_CLK_GATE,
 180                .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
 181                .gate = { CGU_REG_CLKGR, 12 },
 182        },
 183
 184        [JZ4725B_CLK_ADC] = {
 185                "adc", CGU_CLK_GATE,
 186                .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
 187                .gate = { CGU_REG_CLKGR, 7 },
 188        },
 189
 190        [JZ4725B_CLK_I2C] = {
 191                "i2c", CGU_CLK_GATE,
 192                .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
 193                .gate = { CGU_REG_CLKGR, 3 },
 194        },
 195
 196        [JZ4725B_CLK_AIC] = {
 197                "aic", CGU_CLK_GATE,
 198                .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
 199                .gate = { CGU_REG_CLKGR, 5 },
 200        },
 201
 202        [JZ4725B_CLK_MMC0] = {
 203                "mmc0", CGU_CLK_GATE,
 204                .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
 205                .gate = { CGU_REG_CLKGR, 6 },
 206        },
 207
 208        [JZ4725B_CLK_MMC1] = {
 209                "mmc1", CGU_CLK_GATE,
 210                .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
 211                .gate = { CGU_REG_CLKGR, 16 },
 212        },
 213
 214        [JZ4725B_CLK_BCH] = {
 215                "bch", CGU_CLK_GATE,
 216                .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
 217                .gate = { CGU_REG_CLKGR, 11 },
 218        },
 219
 220        [JZ4725B_CLK_TCU] = {
 221                "tcu", CGU_CLK_GATE,
 222                .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
 223                .gate = { CGU_REG_CLKGR, 1 },
 224        },
 225
 226        [JZ4725B_CLK_EXT512] = {
 227                "ext/512", CGU_CLK_FIXDIV,
 228                .parents = { JZ4725B_CLK_EXT },
 229
 230                /* Doc calls it EXT512, but it seems to be /256... */
 231                .fixdiv = { 256 },
 232        },
 233
 234        [JZ4725B_CLK_RTC] = {
 235                "rtc", CGU_CLK_MUX,
 236                .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
 237                .mux = { CGU_REG_OPCR, 2, 1},
 238        },
 239
 240        [JZ4725B_CLK_UDC_PHY] = {
 241                "udc_phy", CGU_CLK_GATE,
 242                .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
 243                .gate = { CGU_REG_OPCR, 6, true },
 244        },
 245};
 246
 247static void __init jz4725b_cgu_init(struct device_node *np)
 248{
 249        int retval;
 250
 251        cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
 252                              ARRAY_SIZE(jz4725b_cgu_clocks), np);
 253        if (!cgu) {
 254                pr_err("%s: failed to initialise CGU\n", __func__);
 255                return;
 256        }
 257
 258        retval = ingenic_cgu_register_clocks(cgu);
 259        if (retval)
 260                pr_err("%s: failed to register CGU Clocks\n", __func__);
 261
 262        ingenic_cgu_register_syscore_ops(cgu);
 263}
 264CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
 265