linux/drivers/clk/imx/clk-imx8qxp.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2018 NXP
   4 *      Dong Aisheng <aisheng.dong@nxp.com>
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/err.h>
   9#include <linux/io.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/platform_device.h>
  13#include <linux/slab.h>
  14
  15#include "clk-scu.h"
  16
  17#include <dt-bindings/clock/imx8-clock.h>
  18#include <dt-bindings/firmware/imx/rsrc.h>
  19
  20static const char *dc0_sels[] = {
  21        "clk_dummy",
  22        "clk_dummy",
  23        "dc0_pll0_clk",
  24        "dc0_pll1_clk",
  25        "dc0_bypass0_clk",
  26};
  27
  28static int imx8qxp_clk_probe(struct platform_device *pdev)
  29{
  30        struct device_node *ccm_node = pdev->dev.of_node;
  31        struct clk_hw_onecell_data *clk_data;
  32        struct clk_hw **clks;
  33        u32 clk_cells;
  34        int ret, i;
  35
  36        ret = imx_clk_scu_init(ccm_node);
  37        if (ret)
  38                return ret;
  39
  40        clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
  41                                IMX_SCU_CLK_END), GFP_KERNEL);
  42        if (!clk_data)
  43                return -ENOMEM;
  44
  45        if (of_property_read_u32(ccm_node, "#clock-cells", &clk_cells))
  46                return -EINVAL;
  47
  48        clk_data->num = IMX_SCU_CLK_END;
  49        clks = clk_data->hws;
  50
  51        /* Fixed clocks */
  52        clks[IMX_CLK_DUMMY]             = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
  53        clks[IMX_ADMA_IPG_CLK_ROOT]     = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000);
  54        clks[IMX_CONN_AXI_CLK_ROOT]     = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333);
  55        clks[IMX_CONN_AHB_CLK_ROOT]     = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666);
  56        clks[IMX_CONN_IPG_CLK_ROOT]     = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333);
  57        clks[IMX_DC_AXI_EXT_CLK]        = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000);
  58        clks[IMX_DC_AXI_INT_CLK]        = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000);
  59        clks[IMX_DC_CFG_CLK]            = clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000);
  60        clks[IMX_MIPI_IPG_CLK]          = clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000);
  61        clks[IMX_IMG_AXI_CLK]           = clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000);
  62        clks[IMX_IMG_IPG_CLK]           = clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000);
  63        clks[IMX_IMG_PXL_CLK]           = clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000);
  64        clks[IMX_HSIO_AXI_CLK]          = clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000);
  65        clks[IMX_HSIO_PER_CLK]          = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
  66        clks[IMX_LSIO_MEM_CLK]          = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
  67        clks[IMX_LSIO_BUS_CLK]          = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
  68
  69        /* ARM core */
  70        clks[IMX_A35_CLK]               = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU, clk_cells);
  71
  72        /* LSIO SS */
  73        clks[IMX_LSIO_PWM0_CLK]         = imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
  74        clks[IMX_LSIO_PWM1_CLK]         = imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER, clk_cells);
  75        clks[IMX_LSIO_PWM2_CLK]         = imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER, clk_cells);
  76        clks[IMX_LSIO_PWM3_CLK]         = imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER, clk_cells);
  77        clks[IMX_LSIO_PWM4_CLK]         = imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER, clk_cells);
  78        clks[IMX_LSIO_PWM5_CLK]         = imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER, clk_cells);
  79        clks[IMX_LSIO_PWM6_CLK]         = imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER, clk_cells);
  80        clks[IMX_LSIO_PWM7_CLK]         = imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER, clk_cells);
  81        clks[IMX_LSIO_GPT0_CLK]         = imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER, clk_cells);
  82        clks[IMX_LSIO_GPT1_CLK]         = imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER, clk_cells);
  83        clks[IMX_LSIO_GPT2_CLK]         = imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER, clk_cells);
  84        clks[IMX_LSIO_GPT3_CLK]         = imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER, clk_cells);
  85        clks[IMX_LSIO_GPT4_CLK]         = imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER, clk_cells);
  86        clks[IMX_LSIO_FSPI0_CLK]        = imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER, clk_cells);
  87        clks[IMX_LSIO_FSPI1_CLK]        = imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER, clk_cells);
  88
  89        /* ADMA SS */
  90        clks[IMX_ADMA_UART0_CLK]        = imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER, clk_cells);
  91        clks[IMX_ADMA_UART1_CLK]        = imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER, clk_cells);
  92        clks[IMX_ADMA_UART2_CLK]        = imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER, clk_cells);
  93        clks[IMX_ADMA_UART3_CLK]        = imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER, clk_cells);
  94        clks[IMX_ADMA_SPI0_CLK]         = imx_clk_scu("spi0_clk",  IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER, clk_cells);
  95        clks[IMX_ADMA_SPI1_CLK]         = imx_clk_scu("spi1_clk",  IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER, clk_cells);
  96        clks[IMX_ADMA_SPI2_CLK]         = imx_clk_scu("spi2_clk",  IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER, clk_cells);
  97        clks[IMX_ADMA_SPI3_CLK]         = imx_clk_scu("spi3_clk",  IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER, clk_cells);
  98        clks[IMX_ADMA_CAN0_CLK]         = imx_clk_scu("can0_clk",  IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER, clk_cells);
  99        clks[IMX_ADMA_I2C0_CLK]         = imx_clk_scu("i2c0_clk",  IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
 100        clks[IMX_ADMA_I2C1_CLK]         = imx_clk_scu("i2c1_clk",  IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER, clk_cells);
 101        clks[IMX_ADMA_I2C2_CLK]         = imx_clk_scu("i2c2_clk",  IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER, clk_cells);
 102        clks[IMX_ADMA_I2C3_CLK]         = imx_clk_scu("i2c3_clk",  IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER, clk_cells);
 103        clks[IMX_ADMA_FTM0_CLK]         = imx_clk_scu("ftm0_clk",  IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells);
 104        clks[IMX_ADMA_FTM1_CLK]         = imx_clk_scu("ftm1_clk",  IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER, clk_cells);
 105        clks[IMX_ADMA_ADC0_CLK]         = imx_clk_scu("adc0_clk",  IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER, clk_cells);
 106        clks[IMX_ADMA_PWM_CLK]          = imx_clk_scu("pwm_clk",   IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
 107        clks[IMX_ADMA_LCD_CLK]          = imx_clk_scu("lcd_clk",   IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER, clk_cells);
 108
 109        /* Connectivity */
 110        clks[IMX_CONN_SDHC0_CLK]        = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER, clk_cells);
 111        clks[IMX_CONN_SDHC1_CLK]        = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER, clk_cells);
 112        clks[IMX_CONN_SDHC2_CLK]        = imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER, clk_cells);
 113        clks[IMX_CONN_ENET0_ROOT_CLK]   = imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER, clk_cells);
 114        clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
 115        clks[IMX_CONN_ENET0_RGMII_CLK]  = imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0, clk_cells);
 116        clks[IMX_CONN_ENET1_ROOT_CLK]   = imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER, clk_cells);
 117        clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
 118        clks[IMX_CONN_ENET1_RGMII_CLK]  = imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0, clk_cells);
 119        clks[IMX_CONN_GPMI_BCH_IO_CLK]  = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS, clk_cells);
 120        clks[IMX_CONN_GPMI_BCH_CLK]     = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER, clk_cells);
 121        clks[IMX_CONN_USB2_ACLK]        = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER, clk_cells);
 122        clks[IMX_CONN_USB2_BUS_CLK]     = imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS, clk_cells);
 123        clks[IMX_CONN_USB2_LPM_CLK]     = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
 124
 125        /* Display controller SS */
 126        clks[IMX_DC0_DISP0_CLK]         = imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
 127        clks[IMX_DC0_DISP1_CLK]         = imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
 128        clks[IMX_DC0_PLL0_CLK]          = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
 129        clks[IMX_DC0_PLL1_CLK]          = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
 130        clks[IMX_DC0_BYPASS0_CLK]       = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
 131        clks[IMX_DC0_BYPASS1_CLK]       = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
 132
 133        /* MIPI-LVDS SS */
 134        clks[IMX_MIPI0_LVDS_PIXEL_CLK]  = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
 135        clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
 136        clks[IMX_MIPI0_LVDS_PHY_CLK]    = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
 137        clks[IMX_MIPI0_I2C0_CLK]        = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
 138        clks[IMX_MIPI0_I2C1_CLK]        = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
 139        clks[IMX_MIPI0_PWM0_CLK]        = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
 140        clks[IMX_MIPI1_LVDS_PIXEL_CLK]  = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
 141        clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
 142        clks[IMX_MIPI1_LVDS_PHY_CLK]    = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
 143        clks[IMX_MIPI1_I2C0_CLK]        = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
 144        clks[IMX_MIPI1_I2C1_CLK]        = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
 145        clks[IMX_MIPI1_PWM0_CLK]        = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
 146
 147        /* MIPI CSI SS */
 148        clks[IMX_CSI0_CORE_CLK]         = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
 149        clks[IMX_CSI0_ESC_CLK]          = imx_clk_scu("mipi_csi0_esc_clk",  IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC, clk_cells);
 150        clks[IMX_CSI0_I2C0_CLK]         = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
 151        clks[IMX_CSI0_PWM0_CLK]         = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
 152
 153        /* GPU SS */
 154        clks[IMX_GPU0_CORE_CLK]         = imx_clk_scu("gpu_core0_clk",   IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER, clk_cells);
 155        clks[IMX_GPU0_SHADER_CLK]       = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC, clk_cells);
 156
 157        for (i = 0; i < clk_data->num; i++) {
 158                if (IS_ERR(clks[i]))
 159                        pr_warn("i.MX clk %u: register failed with %ld\n",
 160                                i, PTR_ERR(clks[i]));
 161        }
 162
 163        if (clk_cells == 2) {
 164                ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
 165                if (ret)
 166                        imx_clk_scu_unregister();
 167        } else {
 168                /*
 169                 * legacy binding code path doesn't unregister here because
 170                 * it will be removed later.
 171                 */
 172                ret = of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
 173        }
 174
 175        return ret;
 176}
 177
 178static const struct of_device_id imx8qxp_match[] = {
 179        { .compatible = "fsl,scu-clk", },
 180        { .compatible = "fsl,imx8qxp-clk", },
 181        { /* sentinel */ }
 182};
 183
 184static struct platform_driver imx8qxp_clk_driver = {
 185        .driver = {
 186                .name = "imx8qxp-clk",
 187                .of_match_table = imx8qxp_match,
 188                .suppress_bind_attrs = true,
 189        },
 190        .probe = imx8qxp_clk_probe,
 191};
 192builtin_platform_driver(imx8qxp_clk_driver);
 193
 194MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
 195MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
 196MODULE_LICENSE("GPL v2");
 197