linux/drivers/clk/imx/clk-imx6sll.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4 * Copyright 2017-2018 NXP.
   5 */
   6
   7#include <dt-bindings/clock/imx6sll-clock.h>
   8#include <linux/clk.h>
   9#include <linux/clkdev.h>
  10#include <linux/clk-provider.h>
  11#include <linux/err.h>
  12#include <linux/init.h>
  13#include <linux/io.h>
  14#include <linux/of.h>
  15#include <linux/of_address.h>
  16
  17#include "clk.h"
  18
  19#define CCM_ANALOG_PLL_BYPASS           (0x1 << 16)
  20#define xPLL_CLR(offset)                (offset + 0x8)
  21
  22static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
  23static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
  24static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
  25static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
  26static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
  27static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
  28static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
  29static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
  30static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
  31static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
  32static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
  33static const char *axi_sels[] = {"periph", "axi_alt_sel", };
  34static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
  35static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
  36static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
  37static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
  38static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
  39static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
  40static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
  41static const char *ssi_sels[] = {"pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", "dummy",};
  42static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
  43static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
  44static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
  45static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
  46static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
  47static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
  48static const char *ecspi_sels[] = { "pll3_60m", "osc", };
  49static const char *uart_sels[] = { "pll3_80m", "osc", };
  50static const char *perclk_sels[] = { "ipg", "osc", };
  51static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
  52
  53static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
  54static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
  55
  56static struct clk_hw **hws;
  57static struct clk_hw_onecell_data *clk_hw_data;
  58
  59static const struct clk_div_table post_div_table[] = {
  60        { .val = 2, .div = 1, },
  61        { .val = 1, .div = 2, },
  62        { .val = 0, .div = 4, },
  63        { }
  64};
  65
  66static const struct clk_div_table video_div_table[] = {
  67        { .val = 0, .div = 1, },
  68        { .val = 1, .div = 2, },
  69        { .val = 2, .div = 1, },
  70        { .val = 3, .div = 4, },
  71        { }
  72};
  73
  74static u32 share_count_audio;
  75static u32 share_count_ssi1;
  76static u32 share_count_ssi2;
  77static u32 share_count_ssi3;
  78
  79static void __init imx6sll_clocks_init(struct device_node *ccm_node)
  80{
  81        struct device_node *np;
  82        void __iomem *base;
  83
  84        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
  85                                          IMX6SLL_CLK_END), GFP_KERNEL);
  86        if (WARN_ON(!clk_hw_data))
  87                return;
  88
  89        clk_hw_data->num = IMX6SLL_CLK_END;
  90        hws = clk_hw_data->hws;
  91
  92        hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
  93
  94        hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
  95        hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
  96
  97        /* ipp_di clock is external input */
  98        hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
  99        hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
 100
 101        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");
 102        base = of_iomap(np, 0);
 103        of_node_put(np);
 104        WARN_ON(!base);
 105
 106        /* Do not bypass PLLs initially */
 107        writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0));
 108        writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10));
 109        writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20));
 110        writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30));
 111        writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70));
 112        writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0));
 113        writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0));
 114
 115        hws[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 116        hws[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 117        hws[IMX6SLL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 118        hws[IMX6SLL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 119        hws[IMX6SLL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 120        hws[IMX6SLL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 121        hws[IMX6SLL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 122
 123        hws[IMX6SLL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,  "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
 124        hws[IMX6SLL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
 125        hws[IMX6SLL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,  "pll3", "pll3_bypass_src", base + 0x10, 0x3);
 126        hws[IMX6SLL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,   "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
 127        hws[IMX6SLL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,   "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
 128        hws[IMX6SLL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,         "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
 129        hws[IMX6SLL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,  "pll7", "pll7_bypass_src", base + 0x20, 0x3);
 130
 131        hws[IMX6SLL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
 132        hws[IMX6SLL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
 133        hws[IMX6SLL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
 134        hws[IMX6SLL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
 135        hws[IMX6SLL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
 136        hws[IMX6SLL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
 137        hws[IMX6SLL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
 138
 139        hws[IMX6SLL_CLK_PLL1_SYS]       = imx_clk_hw_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
 140        hws[IMX6SLL_CLK_PLL2_BUS]       = imx_clk_hw_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
 141        hws[IMX6SLL_CLK_PLL3_USB_OTG]   = imx_clk_hw_gate("pll3_usb_otg",          "pll3_bypass", base + 0x10, 13);
 142        hws[IMX6SLL_CLK_PLL4_AUDIO]     = imx_clk_hw_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);
 143        hws[IMX6SLL_CLK_PLL5_VIDEO]     = imx_clk_hw_gate("pll5_video",    "pll5_bypass", base + 0xa0, 13);
 144        hws[IMX6SLL_CLK_PLL6_ENET]      = imx_clk_hw_gate("pll6_enet",     "pll6_bypass", base + 0xe0, 13);
 145        hws[IMX6SLL_CLK_PLL7_USB_HOST]  = imx_clk_hw_gate("pll7_usb_host",         "pll7_bypass", base + 0x20, 13);
 146
 147        /*
 148         * Bit 20 is the reserved and read-only bit, we do this only for:
 149         * - Do nothing for usbphy clk_enable/disable
 150         * - Keep refcount when do usbphy clk_enable/disable, in that case,
 151         * the clk framework many need to enable/disable usbphy's parent
 152         */
 153        hws[IMX6SLL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg",  base + 0x10, 20);
 154        hws[IMX6SLL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
 155
 156        /*
 157         * usbphy*_gate needs to be on after system boots up, and software
 158         * never needs to control it anymore.
 159         */
 160        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
 161                hws[IMX6SLL_CLK_USBPHY1_GATE] = imx_clk_hw_gate_flags("usbphy1_gate", "dummy", base + 0x10, 6, CLK_IS_CRITICAL);
 162                hws[IMX6SLL_CLK_USBPHY2_GATE] = imx_clk_hw_gate_flags("usbphy2_gate", "dummy", base + 0x20, 6, CLK_IS_CRITICAL);
 163        }
 164
 165        /*                                      name               parent_name     reg          idx */
 166        hws[IMX6SLL_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
 167        hws[IMX6SLL_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
 168        hws[IMX6SLL_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
 169        hws[IMX6SLL_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3_594m", "pll2_bus",       base + 0x100, 3);
 170        hws[IMX6SLL_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
 171        hws[IMX6SLL_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
 172        hws[IMX6SLL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
 173        hws[IMX6SLL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
 174
 175        hws[IMX6SLL_CLK_PLL4_POST_DIV]  = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
 176                 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
 177        hws[IMX6SLL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
 178                 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
 179        hws[IMX6SLL_CLK_PLL5_POST_DIV]  = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video",
 180                 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
 181        hws[IMX6SLL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
 182                 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 183
 184        /*                                                 name         parent_name      mult  div */
 185        hws[IMX6SLL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
 186        hws[IMX6SLL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
 187        hws[IMX6SLL_CLK_PLL3_80M]  = imx_clk_hw_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
 188        hws[IMX6SLL_CLK_PLL3_60M]  = imx_clk_hw_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
 189
 190        np = ccm_node;
 191        base = of_iomap(np, 0);
 192        WARN_ON(!base);
 193
 194        hws[IMX6SLL_CLK_STEP]             = imx_clk_hw_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
 195        hws[IMX6SLL_CLK_PLL1_SW]          = imx_clk_hw_mux_flags("pll1_sw",   base + 0x0c, 2,  1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
 196        hws[IMX6SLL_CLK_AXI_ALT_SEL]      = imx_clk_hw_mux("axi_alt_sel",          base + 0x14, 7,  1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
 197        hws[IMX6SLL_CLK_AXI_SEL]          = imx_clk_hw_mux_flags("axi_sel",   base + 0x14, 6,  1, axi_sels, ARRAY_SIZE(axi_sels), 0);
 198        hws[IMX6SLL_CLK_PERIPH_PRE]       = imx_clk_hw_mux("periph_pre",      base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
 199        hws[IMX6SLL_CLK_PERIPH2_PRE]      = imx_clk_hw_mux("periph2_pre",     base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
 200        hws[IMX6SLL_CLK_PERIPH_CLK2_SEL]  = imx_clk_hw_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
 201        hws[IMX6SLL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
 202        hws[IMX6SLL_CLK_USDHC1_SEL]       = imx_clk_hw_mux("usdhc1_sel",   base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
 203        hws[IMX6SLL_CLK_USDHC2_SEL]       = imx_clk_hw_mux("usdhc2_sel",   base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
 204        hws[IMX6SLL_CLK_USDHC3_SEL]       = imx_clk_hw_mux("usdhc3_sel",   base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
 205        hws[IMX6SLL_CLK_SSI1_SEL]         = imx_clk_hw_mux("ssi1_sel",     base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
 206        hws[IMX6SLL_CLK_SSI2_SEL]         = imx_clk_hw_mux("ssi2_sel",     base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
 207        hws[IMX6SLL_CLK_SSI3_SEL]         = imx_clk_hw_mux("ssi3_sel",     base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
 208        hws[IMX6SLL_CLK_PERCLK_SEL]       = imx_clk_hw_mux("perclk_sel",   base + 0x1c, 6,  1, perclk_sels, ARRAY_SIZE(perclk_sels));
 209        hws[IMX6SLL_CLK_UART_SEL]         = imx_clk_hw_mux("uart_sel",  base + 0x24, 6,  1, uart_sels, ARRAY_SIZE(uart_sels));
 210        hws[IMX6SLL_CLK_SPDIF_SEL]        = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
 211        hws[IMX6SLL_CLK_EXTERN_AUDIO_SEL] = imx_clk_hw_mux("extern_audio_sel", base + 0x30, 7,  2, spdif_sels, ARRAY_SIZE(spdif_sels));
 212        hws[IMX6SLL_CLK_EPDC_PRE_SEL]     = imx_clk_hw_mux("epdc_pre_sel",      base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels));
 213        hws[IMX6SLL_CLK_EPDC_SEL]         = imx_clk_hw_mux("epdc_sel",  base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
 214        hws[IMX6SLL_CLK_ECSPI_SEL]        = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
 215        hws[IMX6SLL_CLK_LCDIF_PRE_SEL]    = imx_clk_hw_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
 216        hws[IMX6SLL_CLK_LCDIF_SEL]        = imx_clk_hw_mux("lcdif_sel",     base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
 217
 218        hws[IMX6SLL_CLK_PERIPH]  = imx_clk_hw_busy_mux("periph",  base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
 219        hws[IMX6SLL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
 220
 221        hws[IMX6SLL_CLK_PERIPH_CLK2]    = imx_clk_hw_divider("periph_clk2",   "periph_clk2_sel",        base + 0x14, 27, 3);
 222        hws[IMX6SLL_CLK_PERIPH2_CLK2]   = imx_clk_hw_divider("periph2_clk2",  "periph2_clk2_sel",       base + 0x14, 0,  3);
 223        hws[IMX6SLL_CLK_IPG]            = imx_clk_hw_divider("ipg",        "ahb",       base + 0x14, 8, 2);
 224        hws[IMX6SLL_CLK_LCDIF_PODF]     = imx_clk_hw_divider("lcdif_podf",         "lcdif_pred",        base + 0x18, 23, 3);
 225        hws[IMX6SLL_CLK_PERCLK] = imx_clk_hw_divider("perclk",     "perclk_sel",        base + 0x1c, 0,  6);
 226        hws[IMX6SLL_CLK_USDHC3_PODF]   = imx_clk_hw_divider("usdhc3_podf",   "usdhc3_sel",      base + 0x24, 19, 3);
 227        hws[IMX6SLL_CLK_USDHC2_PODF]    = imx_clk_hw_divider("usdhc2_podf",   "usdhc2_sel",     base + 0x24, 16, 3);
 228        hws[IMX6SLL_CLK_USDHC1_PODF]    = imx_clk_hw_divider("usdhc1_podf",   "usdhc1_sel",     base + 0x24, 11, 3);
 229        hws[IMX6SLL_CLK_UART_PODF]      = imx_clk_hw_divider("uart_podf",          "uart_sel",          base + 0x24, 0,  6);
 230        hws[IMX6SLL_CLK_SSI3_PRED]      = imx_clk_hw_divider("ssi3_pred",          "ssi3_sel",          base + 0x28, 22, 3);
 231        hws[IMX6SLL_CLK_SSI3_PODF]      = imx_clk_hw_divider("ssi3_podf",          "ssi3_pred",         base + 0x28, 16, 6);
 232        hws[IMX6SLL_CLK_SSI1_PRED]      = imx_clk_hw_divider("ssi1_pred",          "ssi1_sel",          base + 0x28, 6,  3);
 233        hws[IMX6SLL_CLK_SSI1_PODF]      = imx_clk_hw_divider("ssi1_podf",          "ssi1_pred",         base + 0x28, 0,  6);
 234        hws[IMX6SLL_CLK_SSI2_PRED]      = imx_clk_hw_divider("ssi2_pred",          "ssi2_sel",          base + 0x2c, 6,  3);
 235        hws[IMX6SLL_CLK_SSI2_PODF]      = imx_clk_hw_divider("ssi2_podf",          "ssi2_pred",         base + 0x2c, 0,  6);
 236        hws[IMX6SLL_CLK_SPDIF_PRED]     = imx_clk_hw_divider("spdif_pred",         "spdif_sel",         base + 0x30, 25, 3);
 237        hws[IMX6SLL_CLK_SPDIF_PODF]     = imx_clk_hw_divider("spdif_podf",         "spdif_pred",        base + 0x30, 22, 3);
 238        hws[IMX6SLL_CLK_EXTERN_AUDIO_PRED] = imx_clk_hw_divider("extern_audio_pred", "extern_audio_sel",  base + 0x30, 12, 3);
 239        hws[IMX6SLL_CLK_EXTERN_AUDIO_PODF] = imx_clk_hw_divider("extern_audio_podf", "extern_audio_pred", base + 0x30, 9,  3);
 240        hws[IMX6SLL_CLK_EPDC_PODF]  = imx_clk_hw_divider("epdc_podf",  "epdc_pre_sel",  base + 0x34, 12, 3);
 241        hws[IMX6SLL_CLK_ECSPI_PODF] = imx_clk_hw_divider("ecspi_podf", "ecspi_sel",     base + 0x38, 19, 6);
 242        hws[IMX6SLL_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
 243
 244        hws[IMX6SLL_CLK_ARM]            = imx_clk_hw_busy_divider("arm",        "pll1_sw",      base +  0x10, 0,  3,  base + 0x48, 16);
 245        hws[IMX6SLL_CLK_MMDC_PODF]      = imx_clk_hw_busy_divider("mmdc_podf",  "periph2",      base +  0x14, 3,  3,  base + 0x48, 2);
 246        hws[IMX6SLL_CLK_AXI_PODF]       = imx_clk_hw_busy_divider("axi",        "axi_sel",      base +  0x14, 16, 3,  base + 0x48, 0);
 247        hws[IMX6SLL_CLK_AHB]            = imx_clk_hw_busy_divider("ahb",        "periph",       base +  0x14, 10, 3,  base + 0x48, 1);
 248
 249        hws[IMX6SLL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
 250        hws[IMX6SLL_CLK_LDB_DI0_DIV_7]    = imx_clk_hw_fixed_factor("ldb_di0_div_7",   "ldb_di0_sel", 1, 7);
 251        hws[IMX6SLL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
 252        hws[IMX6SLL_CLK_LDB_DI1_DIV_7]    = imx_clk_hw_fixed_factor("ldb_di1_div_7",   "ldb_di1_sel", 1, 7);
 253
 254        hws[IMX6SLL_CLK_LDB_DI0_SEL]    = imx_clk_hw_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
 255        hws[IMX6SLL_CLK_LDB_DI1_SEL]   = imx_clk_hw_mux("ldb_di1_sel", base + 0x1c, 7, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels));
 256        hws[IMX6SLL_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
 257        hws[IMX6SLL_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux("ldb_di1_div_sel", base + 0x20, 10, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
 258
 259        /* CCGR0 */
 260        hws[IMX6SLL_CLK_AIPSTZ1]        = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
 261        hws[IMX6SLL_CLK_AIPSTZ2]        = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
 262        hws[IMX6SLL_CLK_DCP]            = imx_clk_hw_gate2("dcp", "ahb", base + 0x68, 10);
 263        hws[IMX6SLL_CLK_UART2_IPG]      = imx_clk_hw_gate2("uart2_ipg", "ipg", base + 0x68, 28);
 264        hws[IMX6SLL_CLK_UART2_SERIAL]   = imx_clk_hw_gate2("uart2_serial",      "uart_podf", base + 0x68, 28);
 265        hws[IMX6SLL_CLK_GPIO2]          = imx_clk_hw_gate2("gpio2", "ipg", base + 0x68, 30);
 266
 267        /* CCGR1 */
 268        hws[IMX6SLL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1",    "ecspi_podf", base + 0x6c, 0);
 269        hws[IMX6SLL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2",    "ecspi_podf", base + 0x6c, 2);
 270        hws[IMX6SLL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3",    "ecspi_podf", base + 0x6c, 4);
 271        hws[IMX6SLL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4",    "ecspi_podf", base + 0x6c, 6);
 272        hws[IMX6SLL_CLK_UART3_IPG]      = imx_clk_hw_gate2("uart3_ipg", "ipg", base + 0x6c, 10);
 273        hws[IMX6SLL_CLK_UART3_SERIAL]   = imx_clk_hw_gate2("uart3_serial",      "uart_podf", base + 0x6c, 10);
 274        hws[IMX6SLL_CLK_EPIT1]          = imx_clk_hw_gate2("epit1",     "perclk", base + 0x6c, 12);
 275        hws[IMX6SLL_CLK_EPIT2]          = imx_clk_hw_gate2("epit2",     "perclk", base + 0x6c, 14);
 276        hws[IMX6SLL_CLK_GPT_BUS]        = imx_clk_hw_gate2("gpt1_bus",  "perclk", base + 0x6c, 20);
 277        hws[IMX6SLL_CLK_GPT_SERIAL]     = imx_clk_hw_gate2("gpt1_serial",       "perclk", base + 0x6c, 22);
 278        hws[IMX6SLL_CLK_UART4_IPG]      = imx_clk_hw_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
 279        hws[IMX6SLL_CLK_UART4_SERIAL]   = imx_clk_hw_gate2("uart4_serial",      "uart_podf", base + 0x6c, 24);
 280        hws[IMX6SLL_CLK_GPIO1]          = imx_clk_hw_gate2("gpio1",     "ipg", base + 0x6c, 26);
 281        hws[IMX6SLL_CLK_GPIO5]          = imx_clk_hw_gate2("gpio5",     "ipg", base + 0x6c, 30);
 282
 283        /* CCGR2 */
 284        hws[IMX6SLL_CLK_GPIO6]          = imx_clk_hw_gate2("gpio6",     "ipg",    base + 0x70, 0);
 285        hws[IMX6SLL_CLK_CSI]            = imx_clk_hw_gate2("csi",               "axi",    base + 0x70,  2);
 286        hws[IMX6SLL_CLK_I2C1]           = imx_clk_hw_gate2("i2c1",              "perclk", base + 0x70,  6);
 287        hws[IMX6SLL_CLK_I2C2]           = imx_clk_hw_gate2("i2c2",              "perclk", base + 0x70,  8);
 288        hws[IMX6SLL_CLK_I2C3]           = imx_clk_hw_gate2("i2c3",              "perclk", base + 0x70,  10);
 289        hws[IMX6SLL_CLK_OCOTP]          = imx_clk_hw_gate2("ocotp",     "ipg",    base + 0x70,  12);
 290        hws[IMX6SLL_CLK_GPIO3]          = imx_clk_hw_gate2("gpio3",     "ipg",    base + 0x70,  26);
 291        hws[IMX6SLL_CLK_LCDIF_APB]      = imx_clk_hw_gate2("lcdif_apb", "axi",    base + 0x70,  28);
 292        hws[IMX6SLL_CLK_PXP]            = imx_clk_hw_gate2("pxp",               "axi",    base + 0x70,  30);
 293
 294        /* CCGR3 */
 295        hws[IMX6SLL_CLK_UART5_IPG]      = imx_clk_hw_gate2("uart5_ipg", "ipg",          base + 0x74, 2);
 296        hws[IMX6SLL_CLK_UART5_SERIAL]   = imx_clk_hw_gate2("uart5_serial",      "uart_podf",    base + 0x74, 2);
 297        hws[IMX6SLL_CLK_EPDC_AXI]       = imx_clk_hw_gate2("epdc_aclk", "axi",          base + 0x74, 4);
 298        hws[IMX6SLL_CLK_EPDC_PIX]       = imx_clk_hw_gate2("epdc_pix",  "epdc_podf",    base + 0x74, 4);
 299        hws[IMX6SLL_CLK_LCDIF_PIX]      = imx_clk_hw_gate2("lcdif_pix", "lcdif_podf",   base + 0x74, 10);
 300        hws[IMX6SLL_CLK_GPIO4]          = imx_clk_hw_gate2("gpio4",     "ipg",          base + 0x74, 12);
 301        hws[IMX6SLL_CLK_WDOG1]          = imx_clk_hw_gate2("wdog1",     "ipg",          base + 0x74, 16);
 302        hws[IMX6SLL_CLK_MMDC_P0_FAST]   = imx_clk_hw_gate_flags("mmdc_p0_fast", "mmdc_podf",  base + 0x74,      20, CLK_IS_CRITICAL);
 303        hws[IMX6SLL_CLK_MMDC_P0_IPG]    = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg",     base + 0x74, 24, CLK_IS_CRITICAL);
 304        hws[IMX6SLL_CLK_MMDC_P1_IPG]    = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg",     base + 0x74, 26, CLK_IS_CRITICAL);
 305        hws[IMX6SLL_CLK_OCRAM]          = imx_clk_hw_gate_flags("ocram", "ahb",            base + 0x74, 28, CLK_IS_CRITICAL);
 306
 307        /* CCGR4 */
 308        hws[IMX6SLL_CLK_PWM1]           = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16);
 309        hws[IMX6SLL_CLK_PWM2]           = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18);
 310        hws[IMX6SLL_CLK_PWM3]           = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20);
 311        hws[IMX6SLL_CLK_PWM4]           = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22);
 312
 313        /* CCGR5 */
 314        hws[IMX6SLL_CLK_ROM]            = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
 315        hws[IMX6SLL_CLK_SDMA]           = imx_clk_hw_gate2("sdma",       "ahb", base + 0x7c, 6);
 316        hws[IMX6SLL_CLK_WDOG2]          = imx_clk_hw_gate2("wdog2", "ipg",      base + 0x7c, 10);
 317        hws[IMX6SLL_CLK_SPBA]           = imx_clk_hw_gate2("spba",       "ipg", base + 0x7c, 12);
 318        hws[IMX6SLL_CLK_EXTERN_AUDIO]   = imx_clk_hw_gate2_shared("extern_audio",  "extern_audio_podf", base + 0x7c, 14, &share_count_audio);
 319        hws[IMX6SLL_CLK_SPDIF]          = imx_clk_hw_gate2_shared("spdif",              "spdif_podf",   base + 0x7c, 14, &share_count_audio);
 320        hws[IMX6SLL_CLK_SPDIF_GCLK]     = imx_clk_hw_gate2_shared("spdif_gclk", "ipg",          base + 0x7c, 14, &share_count_audio);
 321        hws[IMX6SLL_CLK_SSI1]           = imx_clk_hw_gate2_shared("ssi1",               "ssi1_podf",    base + 0x7c, 18, &share_count_ssi1);
 322        hws[IMX6SLL_CLK_SSI1_IPG]       = imx_clk_hw_gate2_shared("ssi1_ipg",   "ipg",          base + 0x7c, 18, &share_count_ssi1);
 323        hws[IMX6SLL_CLK_SSI2]           = imx_clk_hw_gate2_shared("ssi2",               "ssi2_podf",    base + 0x7c, 20, &share_count_ssi2);
 324        hws[IMX6SLL_CLK_SSI2_IPG]       = imx_clk_hw_gate2_shared("ssi2_ipg",   "ipg",          base + 0x7c, 20, &share_count_ssi2);
 325        hws[IMX6SLL_CLK_SSI3]           = imx_clk_hw_gate2_shared("ssi3",               "ssi3_podf",    base + 0x7c, 22, &share_count_ssi3);
 326        hws[IMX6SLL_CLK_SSI3_IPG]       = imx_clk_hw_gate2_shared("ssi3_ipg",   "ipg",          base + 0x7c, 22, &share_count_ssi3);
 327        hws[IMX6SLL_CLK_UART1_IPG]      = imx_clk_hw_gate2("uart1_ipg", "ipg",          base + 0x7c, 24);
 328        hws[IMX6SLL_CLK_UART1_SERIAL]   = imx_clk_hw_gate2("uart1_serial",      "uart_podf",    base + 0x7c, 24);
 329
 330        /* CCGR6 */
 331        hws[IMX6SLL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg",       base + 0x80,  0);
 332        hws[IMX6SLL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf",  base + 0x80,       2);
 333        hws[IMX6SLL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf",  base + 0x80,       4);
 334        hws[IMX6SLL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf",  base + 0x80,       6);
 335
 336        /* mask handshake of mmdc */
 337        imx_mmdc_mask_handshake(base, 0);
 338
 339        imx_check_clk_hws(hws, IMX6SLL_CLK_END);
 340
 341        of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
 342
 343        imx_register_uart_clocks(5);
 344
 345        /* Lower the AHB clock rate before changing the clock source. */
 346        clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000);
 347
 348        /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
 349        clk_set_parent(hws[IMX6SLL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6SLL_CLK_PLL3_USB_OTG]->clk);
 350        clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_CLK2]->clk);
 351        clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk);
 352        clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_PRE]->clk);
 353
 354        clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 132000000);
 355}
 356CLK_OF_DECLARE_DRIVER(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init);
 357