linux/drivers/clk/bcm/clk-nsp.c
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   1/*
   2 * Copyright (C) 2015 Broadcom Corporation
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License as
   6 * published by the Free Software Foundation version 2.
   7 *
   8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9 * kind, whether express or implied; without even the implied warranty
  10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/err.h>
  16#include <linux/clk-provider.h>
  17#include <linux/io.h>
  18#include <linux/of.h>
  19#include <linux/of_address.h>
  20
  21#include <dt-bindings/clock/bcm-nsp.h>
  22#include "clk-iproc.h"
  23
  24#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
  25
  26#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
  27        .pwr_shift = ps, .iso_shift = is }
  28
  29#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
  30        .p_reset_shift = prs }
  31
  32#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
  33        .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,    \
  34        .ka_width = kaw }
  35
  36#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
  37        .hold_shift = hs, .bypass_shift = bs }
  38
  39static void __init nsp_armpll_init(struct device_node *node)
  40{
  41        iproc_armpll_setup(node);
  42}
  43CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
  44
  45static const struct iproc_pll_ctrl genpll = {
  46        .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
  47        .aon = AON_VAL(0x0, 1, 12, 0),
  48        .reset = RESET_VAL(0x0, 11, 10),
  49        .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
  50        .ndiv_int = REG_VAL(0x14, 20, 10),
  51        .ndiv_frac = REG_VAL(0x14, 0, 20),
  52        .pdiv = REG_VAL(0x18, 24, 3),
  53        .status = REG_VAL(0x20, 12, 1),
  54};
  55
  56static const struct iproc_clk_ctrl genpll_clk[] = {
  57        [BCM_NSP_GENPLL_PHY_CLK] = {
  58                .channel = BCM_NSP_GENPLL_PHY_CLK,
  59                .flags = IPROC_CLK_AON,
  60                .enable = ENABLE_VAL(0x4, 12, 6, 18),
  61                .mdiv = REG_VAL(0x18, 16, 8),
  62        },
  63        [BCM_NSP_GENPLL_ENET_SW_CLK] = {
  64                .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
  65                .flags = IPROC_CLK_AON,
  66                .enable = ENABLE_VAL(0x4, 13, 7, 19),
  67                .mdiv = REG_VAL(0x18, 8, 8),
  68        },
  69        [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = {
  70                .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
  71                .flags = IPROC_CLK_AON,
  72                .enable = ENABLE_VAL(0x4, 14, 8, 20),
  73                .mdiv = REG_VAL(0x18, 0, 8),
  74        },
  75        [BCM_NSP_GENPLL_IPROCFAST_CLK] = {
  76                .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
  77                .flags = IPROC_CLK_AON,
  78                .enable = ENABLE_VAL(0x4, 15, 9, 21),
  79                .mdiv = REG_VAL(0x1c, 16, 8),
  80        },
  81        [BCM_NSP_GENPLL_SATA1_CLK] = {
  82                .channel = BCM_NSP_GENPLL_SATA1_CLK,
  83                .flags = IPROC_CLK_AON,
  84                .enable = ENABLE_VAL(0x4, 16, 10, 22),
  85                .mdiv = REG_VAL(0x1c, 8, 8),
  86        },
  87        [BCM_NSP_GENPLL_SATA2_CLK] = {
  88                .channel = BCM_NSP_GENPLL_SATA2_CLK,
  89                .flags = IPROC_CLK_AON,
  90                .enable = ENABLE_VAL(0x4, 17, 11, 23),
  91                .mdiv = REG_VAL(0x1c, 0, 8),
  92        },
  93};
  94
  95static void __init nsp_genpll_clk_init(struct device_node *node)
  96{
  97        iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
  98                            ARRAY_SIZE(genpll_clk));
  99}
 100CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
 101
 102static const struct iproc_pll_ctrl lcpll0 = {
 103        .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
 104        .aon = AON_VAL(0x0, 1, 24, 0),
 105        .reset = RESET_VAL(0x0, 23, 22),
 106        .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4),
 107        .ndiv_int = REG_VAL(0x4, 20, 8),
 108        .ndiv_frac = REG_VAL(0x4, 0, 20),
 109        .pdiv = REG_VAL(0x4, 28, 3),
 110        .status = REG_VAL(0x10, 12, 1),
 111};
 112
 113static const struct iproc_clk_ctrl lcpll0_clk[] = {
 114        [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = {
 115                .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK,
 116                .flags = IPROC_CLK_AON,
 117                .enable = ENABLE_VAL(0x0, 6, 3, 9),
 118                .mdiv = REG_VAL(0x8, 24, 8),
 119        },
 120        [BCM_NSP_LCPLL0_SDIO_CLK] = {
 121                .channel = BCM_NSP_LCPLL0_SDIO_CLK,
 122                .flags = IPROC_CLK_AON,
 123                .enable = ENABLE_VAL(0x0, 7, 4, 10),
 124                .mdiv = REG_VAL(0x8, 16, 8),
 125        },
 126        [BCM_NSP_LCPLL0_DDR_PHY_CLK] = {
 127                .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK,
 128                .flags = IPROC_CLK_AON,
 129                .enable = ENABLE_VAL(0x0, 8, 5, 11),
 130                .mdiv = REG_VAL(0x8, 8, 8),
 131        },
 132};
 133
 134static void __init nsp_lcpll0_clk_init(struct device_node *node)
 135{
 136        iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
 137                            ARRAY_SIZE(lcpll0_clk));
 138}
 139CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);
 140