linux/drivers/clk/at91/sama5d2.c
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   1// SPDX-License-Identifier: GPL-2.0
   2#include <linux/clk-provider.h>
   3#include <linux/mfd/syscon.h>
   4#include <linux/slab.h>
   5
   6#include <dt-bindings/clock/at91.h>
   7
   8#include "pmc.h"
   9
  10static DEFINE_SPINLOCK(mck_lock);
  11
  12static const struct clk_master_characteristics mck_characteristics = {
  13        .output = { .min = 124000000, .max = 166000000 },
  14        .divisors = { 1, 2, 4, 3 },
  15};
  16
  17static u8 plla_out[] = { 0 };
  18
  19static u16 plla_icpll[] = { 0 };
  20
  21static const struct clk_range plla_outputs[] = {
  22        { .min = 600000000, .max = 1200000000 },
  23};
  24
  25static const struct clk_pll_characteristics plla_characteristics = {
  26        .input = { .min = 12000000, .max = 24000000 },
  27        .num_output = ARRAY_SIZE(plla_outputs),
  28        .output = plla_outputs,
  29        .icpll = plla_icpll,
  30        .out = plla_out,
  31};
  32
  33static const struct clk_pcr_layout sama5d2_pcr_layout = {
  34        .offset = 0x10c,
  35        .cmd = BIT(12),
  36        .gckcss_mask = GENMASK(10, 8),
  37        .pid_mask = GENMASK(6, 0),
  38};
  39
  40static const struct {
  41        char *n;
  42        char *p;
  43        u8 id;
  44} sama5d2_systemck[] = {
  45        { .n = "ddrck", .p = "masterck_div", .id = 2 },
  46        { .n = "lcdck", .p = "masterck_div", .id = 3 },
  47        { .n = "uhpck", .p = "usbck",        .id = 6 },
  48        { .n = "udpck", .p = "usbck",        .id = 7 },
  49        { .n = "pck0",  .p = "prog0",        .id = 8 },
  50        { .n = "pck1",  .p = "prog1",        .id = 9 },
  51        { .n = "pck2",  .p = "prog2",        .id = 10 },
  52        { .n = "iscck", .p = "masterck_div", .id = 18 },
  53};
  54
  55static const struct {
  56        char *n;
  57        u8 id;
  58        struct clk_range r;
  59} sama5d2_periph32ck[] = {
  60        { .n = "macb0_clk",   .id = 5,  .r = { .min = 0, .max = 83000000 }, },
  61        { .n = "tdes_clk",    .id = 11, .r = { .min = 0, .max = 83000000 }, },
  62        { .n = "matrix1_clk", .id = 14, },
  63        { .n = "hsmc_clk",    .id = 17, },
  64        { .n = "pioA_clk",    .id = 18, .r = { .min = 0, .max = 83000000 }, },
  65        { .n = "flx0_clk",    .id = 19, .r = { .min = 0, .max = 83000000 }, },
  66        { .n = "flx1_clk",    .id = 20, .r = { .min = 0, .max = 83000000 }, },
  67        { .n = "flx2_clk",    .id = 21, .r = { .min = 0, .max = 83000000 }, },
  68        { .n = "flx3_clk",    .id = 22, .r = { .min = 0, .max = 83000000 }, },
  69        { .n = "flx4_clk",    .id = 23, .r = { .min = 0, .max = 83000000 }, },
  70        { .n = "uart0_clk",   .id = 24, .r = { .min = 0, .max = 83000000 }, },
  71        { .n = "uart1_clk",   .id = 25, .r = { .min = 0, .max = 83000000 }, },
  72        { .n = "uart2_clk",   .id = 26, .r = { .min = 0, .max = 83000000 }, },
  73        { .n = "uart3_clk",   .id = 27, .r = { .min = 0, .max = 83000000 }, },
  74        { .n = "uart4_clk",   .id = 28, .r = { .min = 0, .max = 83000000 }, },
  75        { .n = "twi0_clk",    .id = 29, .r = { .min = 0, .max = 83000000 }, },
  76        { .n = "twi1_clk",    .id = 30, .r = { .min = 0, .max = 83000000 }, },
  77        { .n = "spi0_clk",    .id = 33, .r = { .min = 0, .max = 83000000 }, },
  78        { .n = "spi1_clk",    .id = 34, .r = { .min = 0, .max = 83000000 }, },
  79        { .n = "tcb0_clk",    .id = 35, .r = { .min = 0, .max = 83000000 }, },
  80        { .n = "tcb1_clk",    .id = 36, .r = { .min = 0, .max = 83000000 }, },
  81        { .n = "pwm_clk",     .id = 38, .r = { .min = 0, .max = 83000000 }, },
  82        { .n = "adc_clk",     .id = 40, .r = { .min = 0, .max = 83000000 }, },
  83        { .n = "uhphs_clk",   .id = 41, .r = { .min = 0, .max = 83000000 }, },
  84        { .n = "udphs_clk",   .id = 42, .r = { .min = 0, .max = 83000000 }, },
  85        { .n = "ssc0_clk",    .id = 43, .r = { .min = 0, .max = 83000000 }, },
  86        { .n = "ssc1_clk",    .id = 44, .r = { .min = 0, .max = 83000000 }, },
  87        { .n = "trng_clk",    .id = 47, .r = { .min = 0, .max = 83000000 }, },
  88        { .n = "pdmic_clk",   .id = 48, .r = { .min = 0, .max = 83000000 }, },
  89        { .n = "securam_clk", .id = 51, },
  90        { .n = "i2s0_clk",    .id = 54, .r = { .min = 0, .max = 83000000 }, },
  91        { .n = "i2s1_clk",    .id = 55, .r = { .min = 0, .max = 83000000 }, },
  92        { .n = "can0_clk",    .id = 56, .r = { .min = 0, .max = 83000000 }, },
  93        { .n = "can1_clk",    .id = 57, .r = { .min = 0, .max = 83000000 }, },
  94        { .n = "ptc_clk",     .id = 58, .r = { .min = 0, .max = 83000000 }, },
  95        { .n = "classd_clk",  .id = 59, .r = { .min = 0, .max = 83000000 }, },
  96};
  97
  98static const struct {
  99        char *n;
 100        u8 id;
 101} sama5d2_periphck[] = {
 102        { .n = "dma0_clk",    .id = 6, },
 103        { .n = "dma1_clk",    .id = 7, },
 104        { .n = "aes_clk",     .id = 9, },
 105        { .n = "aesb_clk",    .id = 10, },
 106        { .n = "sha_clk",     .id = 12, },
 107        { .n = "mpddr_clk",   .id = 13, },
 108        { .n = "matrix0_clk", .id = 15, },
 109        { .n = "sdmmc0_hclk", .id = 31, },
 110        { .n = "sdmmc1_hclk", .id = 32, },
 111        { .n = "lcdc_clk",    .id = 45, },
 112        { .n = "isc_clk",     .id = 46, },
 113        { .n = "qspi0_clk",   .id = 52, },
 114        { .n = "qspi1_clk",   .id = 53, },
 115};
 116
 117static const struct {
 118        char *n;
 119        u8 id;
 120        struct clk_range r;
 121        int chg_pid;
 122} sama5d2_gck[] = {
 123        { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
 124        { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
 125        { .n = "tcb0_gclk",   .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
 126        { .n = "tcb1_gclk",   .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
 127        { .n = "pwm_gclk",    .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
 128        { .n = "isc_gclk",    .id = 46, .chg_pid = INT_MIN, },
 129        { .n = "pdmic_gclk",  .id = 48, .chg_pid = INT_MIN, },
 130        { .n = "i2s0_gclk",   .id = 54, .chg_pid = 5, },
 131        { .n = "i2s1_gclk",   .id = 55, .chg_pid = 5, },
 132        { .n = "can0_gclk",   .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
 133        { .n = "can1_gclk",   .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
 134        { .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, },
 135};
 136
 137static const struct clk_programmable_layout sama5d2_programmable_layout = {
 138        .pres_mask = 0xff,
 139        .pres_shift = 4,
 140        .css_mask = 0x7,
 141        .have_slck_mck = 0,
 142        .is_pres_direct = 1,
 143};
 144
 145static void __init sama5d2_pmc_setup(struct device_node *np)
 146{
 147        struct clk_range range = CLK_RANGE(0, 0);
 148        const char *slck_name, *mainxtal_name;
 149        struct pmc_data *sama5d2_pmc;
 150        const char *parent_names[6];
 151        struct regmap *regmap, *regmap_sfr;
 152        struct clk_hw *hw;
 153        int i;
 154        bool bypass;
 155
 156        i = of_property_match_string(np, "clock-names", "slow_clk");
 157        if (i < 0)
 158                return;
 159
 160        slck_name = of_clk_get_parent_name(np, i);
 161
 162        i = of_property_match_string(np, "clock-names", "main_xtal");
 163        if (i < 0)
 164                return;
 165        mainxtal_name = of_clk_get_parent_name(np, i);
 166
 167        regmap = device_node_to_regmap(np);
 168        if (IS_ERR(regmap))
 169                return;
 170
 171        sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPLLCK + 1,
 172                                        nck(sama5d2_systemck),
 173                                        nck(sama5d2_periph32ck),
 174                                        nck(sama5d2_gck), 3);
 175        if (!sama5d2_pmc)
 176                return;
 177
 178        hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
 179                                           100000000);
 180        if (IS_ERR(hw))
 181                goto err_free;
 182
 183        bypass = of_property_read_bool(np, "atmel,osc-bypass");
 184
 185        hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
 186                                        bypass);
 187        if (IS_ERR(hw))
 188                goto err_free;
 189
 190        parent_names[0] = "main_rc_osc";
 191        parent_names[1] = "main_osc";
 192        hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
 193        if (IS_ERR(hw))
 194                goto err_free;
 195
 196        sama5d2_pmc->chws[PMC_MAIN] = hw;
 197
 198        hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
 199                                   &sama5d3_pll_layout, &plla_characteristics);
 200        if (IS_ERR(hw))
 201                goto err_free;
 202
 203        hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
 204        if (IS_ERR(hw))
 205                goto err_free;
 206
 207        sama5d2_pmc->chws[PMC_PLLACK] = hw;
 208
 209        hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
 210                                              "mainck");
 211        if (IS_ERR(hw))
 212                goto err_free;
 213
 214        hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
 215                                             "audiopll_fracck");
 216        if (IS_ERR(hw))
 217                goto err_free;
 218
 219        hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
 220                                             "audiopll_fracck");
 221        if (IS_ERR(hw))
 222                goto err_free;
 223
 224        sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw;
 225
 226        regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
 227        if (IS_ERR(regmap_sfr))
 228                regmap_sfr = NULL;
 229
 230        hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
 231        if (IS_ERR(hw))
 232                goto err_free;
 233
 234        sama5d2_pmc->chws[PMC_UTMI] = hw;
 235
 236        parent_names[0] = slck_name;
 237        parent_names[1] = "mainck";
 238        parent_names[2] = "plladivck";
 239        parent_names[3] = "utmick";
 240        hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
 241                                           parent_names,
 242                                           &at91sam9x5_master_layout,
 243                                           &mck_characteristics, &mck_lock,
 244                                           CLK_SET_RATE_GATE, INT_MIN);
 245        if (IS_ERR(hw))
 246                goto err_free;
 247
 248        hw = at91_clk_register_master_div(regmap, "masterck_div",
 249                                          "masterck_pres",
 250                                          &at91sam9x5_master_layout,
 251                                          &mck_characteristics, &mck_lock,
 252                                          CLK_SET_RATE_GATE);
 253        if (IS_ERR(hw))
 254                goto err_free;
 255
 256        sama5d2_pmc->chws[PMC_MCK] = hw;
 257
 258        hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");
 259        if (IS_ERR(hw))
 260                goto err_free;
 261
 262        sama5d2_pmc->chws[PMC_MCK2] = hw;
 263
 264        parent_names[0] = "plladivck";
 265        parent_names[1] = "utmick";
 266        hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
 267        if (IS_ERR(hw))
 268                goto err_free;
 269
 270        parent_names[0] = slck_name;
 271        parent_names[1] = "mainck";
 272        parent_names[2] = "plladivck";
 273        parent_names[3] = "utmick";
 274        parent_names[4] = "masterck_div";
 275        parent_names[5] = "audiopll_pmcck";
 276        for (i = 0; i < 3; i++) {
 277                char name[6];
 278
 279                snprintf(name, sizeof(name), "prog%d", i);
 280
 281                hw = at91_clk_register_programmable(regmap, name,
 282                                                    parent_names, 6, i,
 283                                                    &sama5d2_programmable_layout,
 284                                                    NULL);
 285                if (IS_ERR(hw))
 286                        goto err_free;
 287
 288                sama5d2_pmc->pchws[i] = hw;
 289        }
 290
 291        for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
 292                hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
 293                                              sama5d2_systemck[i].p,
 294                                              sama5d2_systemck[i].id);
 295                if (IS_ERR(hw))
 296                        goto err_free;
 297
 298                sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
 299        }
 300
 301        for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
 302                hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
 303                                                         &sama5d2_pcr_layout,
 304                                                         sama5d2_periphck[i].n,
 305                                                         "masterck_div",
 306                                                         sama5d2_periphck[i].id,
 307                                                         &range, INT_MIN);
 308                if (IS_ERR(hw))
 309                        goto err_free;
 310
 311                sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
 312        }
 313
 314        for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
 315                hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
 316                                                         &sama5d2_pcr_layout,
 317                                                         sama5d2_periph32ck[i].n,
 318                                                         "h32mxck",
 319                                                         sama5d2_periph32ck[i].id,
 320                                                         &sama5d2_periph32ck[i].r,
 321                                                         INT_MIN);
 322                if (IS_ERR(hw))
 323                        goto err_free;
 324
 325                sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
 326        }
 327
 328        parent_names[0] = slck_name;
 329        parent_names[1] = "mainck";
 330        parent_names[2] = "plladivck";
 331        parent_names[3] = "utmick";
 332        parent_names[4] = "masterck_div";
 333        parent_names[5] = "audiopll_pmcck";
 334        for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
 335                hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
 336                                                 &sama5d2_pcr_layout,
 337                                                 sama5d2_gck[i].n,
 338                                                 parent_names, NULL, 6,
 339                                                 sama5d2_gck[i].id,
 340                                                 &sama5d2_gck[i].r,
 341                                                 sama5d2_gck[i].chg_pid);
 342                if (IS_ERR(hw))
 343                        goto err_free;
 344
 345                sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
 346        }
 347
 348        if (regmap_sfr) {
 349                parent_names[0] = "i2s0_clk";
 350                parent_names[1] = "i2s0_gclk";
 351                hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
 352                                               parent_names, 2, 0);
 353                if (IS_ERR(hw))
 354                        goto err_free;
 355
 356                sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
 357
 358                parent_names[0] = "i2s1_clk";
 359                parent_names[1] = "i2s1_gclk";
 360                hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
 361                                               parent_names, 2, 1);
 362                if (IS_ERR(hw))
 363                        goto err_free;
 364
 365                sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
 366        }
 367
 368        of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
 369
 370        return;
 371
 372err_free:
 373        kfree(sama5d2_pmc);
 374}
 375
 376CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
 377