linux/include/media/hevc-ctrls.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * These are the HEVC state controls for use with stateless HEVC
   4 * codec drivers.
   5 *
   6 * It turns out that these structs are not stable yet and will undergo
   7 * more changes. So keep them private until they are stable and ready to
   8 * become part of the official public API.
   9 */
  10
  11#ifndef _HEVC_CTRLS_H_
  12#define _HEVC_CTRLS_H_
  13
  14#include <linux/videodev2.h>
  15
  16/* The pixel format isn't stable at the moment and will likely be renamed. */
  17#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */
  18
  19#define V4L2_CID_MPEG_VIDEO_HEVC_SPS            (V4L2_CID_CODEC_BASE + 1008)
  20#define V4L2_CID_MPEG_VIDEO_HEVC_PPS            (V4L2_CID_CODEC_BASE + 1009)
  21#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS   (V4L2_CID_CODEC_BASE + 1010)
  22#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE    (V4L2_CID_CODEC_BASE + 1015)
  23#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE     (V4L2_CID_CODEC_BASE + 1016)
  24
  25/* enum v4l2_ctrl_type type values */
  26#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120
  27#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121
  28#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122
  29
  30enum v4l2_mpeg_video_hevc_decode_mode {
  31        V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
  32        V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
  33};
  34
  35enum v4l2_mpeg_video_hevc_start_code {
  36        V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
  37        V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
  38};
  39
  40#define V4L2_HEVC_SLICE_TYPE_B  0
  41#define V4L2_HEVC_SLICE_TYPE_P  1
  42#define V4L2_HEVC_SLICE_TYPE_I  2
  43
  44#define V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE                (1ULL << 0)
  45#define V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED                 (1ULL << 1)
  46#define V4L2_HEVC_SPS_FLAG_AMP_ENABLED                          (1ULL << 2)
  47#define V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET               (1ULL << 3)
  48#define V4L2_HEVC_SPS_FLAG_PCM_ENABLED                          (1ULL << 4)
  49#define V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED             (1ULL << 5)
  50#define V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT           (1ULL << 6)
  51#define V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED             (1ULL << 7)
  52#define V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED       (1ULL << 8)
  53
  54/* The controls are not stable at the moment and will likely be reworked. */
  55struct v4l2_ctrl_hevc_sps {
  56        /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
  57        __u16   pic_width_in_luma_samples;
  58        __u16   pic_height_in_luma_samples;
  59        __u8    bit_depth_luma_minus8;
  60        __u8    bit_depth_chroma_minus8;
  61        __u8    log2_max_pic_order_cnt_lsb_minus4;
  62        __u8    sps_max_dec_pic_buffering_minus1;
  63        __u8    sps_max_num_reorder_pics;
  64        __u8    sps_max_latency_increase_plus1;
  65        __u8    log2_min_luma_coding_block_size_minus3;
  66        __u8    log2_diff_max_min_luma_coding_block_size;
  67        __u8    log2_min_luma_transform_block_size_minus2;
  68        __u8    log2_diff_max_min_luma_transform_block_size;
  69        __u8    max_transform_hierarchy_depth_inter;
  70        __u8    max_transform_hierarchy_depth_intra;
  71        __u8    pcm_sample_bit_depth_luma_minus1;
  72        __u8    pcm_sample_bit_depth_chroma_minus1;
  73        __u8    log2_min_pcm_luma_coding_block_size_minus3;
  74        __u8    log2_diff_max_min_pcm_luma_coding_block_size;
  75        __u8    num_short_term_ref_pic_sets;
  76        __u8    num_long_term_ref_pics_sps;
  77        __u8    chroma_format_idc;
  78
  79        __u8    padding;
  80
  81        __u64   flags;
  82};
  83
  84#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED      (1ULL << 0)
  85#define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT                  (1ULL << 1)
  86#define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED             (1ULL << 2)
  87#define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT                   (1ULL << 3)
  88#define V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED               (1ULL << 4)
  89#define V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED               (1ULL << 5)
  90#define V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED                  (1ULL << 6)
  91#define V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT  (1ULL << 7)
  92#define V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED                        (1ULL << 8)
  93#define V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED                      (1ULL << 9)
  94#define V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED            (1ULL << 10)
  95#define V4L2_HEVC_PPS_FLAG_TILES_ENABLED                        (1ULL << 11)
  96#define V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED          (1ULL << 12)
  97#define V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED     (1ULL << 13)
  98#define V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 14)
  99#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED   (1ULL << 15)
 100#define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER        (1ULL << 16)
 101#define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT           (1ULL << 17)
 102#define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18)
 103
 104struct v4l2_ctrl_hevc_pps {
 105        /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
 106        __u8    num_extra_slice_header_bits;
 107        __s8    init_qp_minus26;
 108        __u8    diff_cu_qp_delta_depth;
 109        __s8    pps_cb_qp_offset;
 110        __s8    pps_cr_qp_offset;
 111        __u8    num_tile_columns_minus1;
 112        __u8    num_tile_rows_minus1;
 113        __u8    column_width_minus1[20];
 114        __u8    row_height_minus1[22];
 115        __s8    pps_beta_offset_div2;
 116        __s8    pps_tc_offset_div2;
 117        __u8    log2_parallel_merge_level_minus2;
 118
 119        __u8    padding[4];
 120        __u64   flags;
 121};
 122
 123#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE  0x01
 124#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER   0x02
 125#define V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR         0x03
 126
 127#define V4L2_HEVC_DPB_ENTRIES_NUM_MAX           16
 128
 129struct v4l2_hevc_dpb_entry {
 130        __u64   timestamp;
 131        __u8    rps;
 132        __u8    field_pic;
 133        __u16   pic_order_cnt[2];
 134        __u8    padding[2];
 135};
 136
 137struct v4l2_hevc_pred_weight_table {
 138        __s8    delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 139        __s8    luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 140        __s8    delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
 141        __s8    chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
 142
 143        __s8    delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 144        __s8    luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 145        __s8    delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
 146        __s8    chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
 147
 148        __u8    padding[6];
 149
 150        __u8    luma_log2_weight_denom;
 151        __s8    delta_chroma_log2_weight_denom;
 152};
 153
 154#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA              (1ULL << 0)
 155#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA            (1ULL << 1)
 156#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED  (1ULL << 2)
 157#define V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO                 (1ULL << 3)
 158#define V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT                  (1ULL << 4)
 159#define V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0          (1ULL << 5)
 160#define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV              (1ULL << 6)
 161#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7)
 162#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8)
 163#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT     (1ULL << 9)
 164
 165struct v4l2_ctrl_hevc_slice_params {
 166        __u32   bit_size;
 167        __u32   data_bit_offset;
 168
 169        /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */
 170        __u8    nal_unit_type;
 171        __u8    nuh_temporal_id_plus1;
 172
 173        /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
 174        __u8    slice_type;
 175        __u8    colour_plane_id;
 176        __u16   slice_pic_order_cnt;
 177        __u8    num_ref_idx_l0_active_minus1;
 178        __u8    num_ref_idx_l1_active_minus1;
 179        __u8    collocated_ref_idx;
 180        __u8    five_minus_max_num_merge_cand;
 181        __s8    slice_qp_delta;
 182        __s8    slice_cb_qp_offset;
 183        __s8    slice_cr_qp_offset;
 184        __s8    slice_act_y_qp_offset;
 185        __s8    slice_act_cb_qp_offset;
 186        __s8    slice_act_cr_qp_offset;
 187        __s8    slice_beta_offset_div2;
 188        __s8    slice_tc_offset_div2;
 189
 190        /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */
 191        __u8    pic_struct;
 192
 193        /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
 194        __u8    num_active_dpb_entries;
 195        __u8    ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 196        __u8    ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 197
 198        __u8    num_rps_poc_st_curr_before;
 199        __u8    num_rps_poc_st_curr_after;
 200        __u8    num_rps_poc_lt_curr;
 201
 202        __u8    padding;
 203
 204        /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
 205        struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 206
 207        /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
 208        struct v4l2_hevc_pred_weight_table pred_weight_table;
 209
 210        __u64   flags;
 211};
 212
 213#endif
 214