linux/drivers/misc/cardreader/rts5227.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/* Driver for Realtek PCI-Express card reader
   3 *
   4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5 *
   6 * Author:
   7 *   Wei WANG <wei_wang@realsil.com.cn>
   8 *   Roger Tseng <rogerable@realtek.com>
   9 */
  10
  11#include <linux/module.h>
  12#include <linux/delay.h>
  13#include <linux/rtsx_pci.h>
  14
  15#include "rtsx_pcr.h"
  16
  17static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
  18{
  19        u8 val;
  20
  21        rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  22        return val & 0x0F;
  23}
  24
  25static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  26{
  27        u8 driving_3v3[4][3] = {
  28                {0x13, 0x13, 0x13},
  29                {0x96, 0x96, 0x96},
  30                {0x7F, 0x7F, 0x7F},
  31                {0x96, 0x96, 0x96},
  32        };
  33        u8 driving_1v8[4][3] = {
  34                {0x99, 0x99, 0x99},
  35                {0xAA, 0xAA, 0xAA},
  36                {0xFE, 0xFE, 0xFE},
  37                {0xB3, 0xB3, 0xB3},
  38        };
  39        u8 (*driving)[3], drive_sel;
  40
  41        if (voltage == OUTPUT_3V3) {
  42                driving = driving_3v3;
  43                drive_sel = pcr->sd30_drive_sel_3v3;
  44        } else {
  45                driving = driving_1v8;
  46                drive_sel = pcr->sd30_drive_sel_1v8;
  47        }
  48
  49        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  50                        0xFF, driving[drive_sel][0]);
  51        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  52                        0xFF, driving[drive_sel][1]);
  53        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  54                        0xFF, driving[drive_sel][2]);
  55}
  56
  57static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
  58{
  59        struct pci_dev *pdev = pcr->pci;
  60        u32 reg;
  61
  62        pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  63        pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  64
  65        if (!rtsx_vendor_setting_valid(reg))
  66                return;
  67
  68        pcr->aspm_en = rtsx_reg_to_aspm(reg);
  69        pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  70        pcr->card_drive_sel &= 0x3F;
  71        pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  72
  73        pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  74        pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  75        if (rtsx_check_mmc_support(reg))
  76                pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  77        pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  78        if (rtsx_reg_check_reverse_socket(reg))
  79                pcr->flags |= PCR_REVERSE_SOCKET;
  80}
  81
  82static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
  83{
  84        struct pci_dev *pdev = pcr->pci;
  85        int l1ss;
  86        u32 lval;
  87        struct rtsx_cr_option *option = &pcr->option;
  88
  89        l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  90        if (!l1ss)
  91                return;
  92
  93        pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  94
  95        if (CHK_PCI_PID(pcr, 0x522A)) {
  96                if (0 == (lval & 0x0F))
  97                        rtsx_pci_enable_oobs_polling(pcr);
  98                else
  99                        rtsx_pci_disable_oobs_polling(pcr);
 100        }
 101
 102        if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
 103                rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 104        else
 105                rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
 106
 107        if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
 108                rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 109        else
 110                rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
 111
 112        if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
 113                rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 114        else
 115                rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
 116
 117        if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
 118                rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 119        else
 120                rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
 121
 122        if (option->ltr_en) {
 123                u16 val;
 124
 125                pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
 126                if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 127                        option->ltr_enabled = true;
 128                        option->ltr_active = true;
 129                        rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 130                } else {
 131                        option->ltr_enabled = false;
 132                }
 133        }
 134
 135        if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
 136                                | PM_L1_1_EN | PM_L1_2_EN))
 137                option->force_clkreq_0 = false;
 138        else
 139                option->force_clkreq_0 = true;
 140
 141}
 142
 143static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
 144{
 145        u16 cap;
 146        struct rtsx_cr_option *option = &pcr->option;
 147
 148        rts5227_init_from_cfg(pcr);
 149        rtsx_pci_init_cmd(pcr);
 150
 151        /* Configure GPIO as output */
 152        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 153        /* Reset ASPM state to default value */
 154        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 155        /* Switch LDO3318 source from DV33 to card_3v3 */
 156        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 157        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 158        /* LED shine disabled, set initial shine cycle period */
 159        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 160        /* Configure LTR */
 161        pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
 162        if (cap & PCI_EXP_DEVCTL2_LTR_EN)
 163                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
 164        /* Configure OBFF */
 165        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
 166        /* Configure driving */
 167        rts5227_fill_driving(pcr, OUTPUT_3V3);
 168        /* Configure force_clock_req */
 169        if (pcr->flags & PCR_REVERSE_SOCKET)
 170                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
 171        else
 172                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
 173
 174        if (option->force_clkreq_0)
 175                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
 176                                FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
 177        else
 178                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
 179                                FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 180
 181        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
 182
 183        return rtsx_pci_send_cmd(pcr, 100);
 184}
 185
 186static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
 187{
 188        int err;
 189
 190        err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 191        if (err < 0)
 192                return err;
 193
 194        /* Optimize RX sensitivity */
 195        return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
 196}
 197
 198static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
 199{
 200        return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 201}
 202
 203static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
 204{
 205        return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 206}
 207
 208static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
 209{
 210        return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 211}
 212
 213static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
 214{
 215        return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 216}
 217
 218static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
 219{
 220        int err;
 221
 222        if (pcr->option.ocp_en)
 223                rtsx_pci_enable_ocp(pcr);
 224
 225        rtsx_pci_init_cmd(pcr);
 226        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 227                        SD_POWER_MASK, SD_PARTIAL_POWER_ON);
 228
 229        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 230                        LDO3318_PWR_MASK, 0x02);
 231
 232        err = rtsx_pci_send_cmd(pcr, 100);
 233        if (err < 0)
 234                return err;
 235
 236        /* To avoid too large in-rush current */
 237        msleep(20);
 238        rtsx_pci_init_cmd(pcr);
 239        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 240                        SD_POWER_MASK, SD_POWER_ON);
 241
 242        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 243                        LDO3318_PWR_MASK, 0x06);
 244
 245        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
 246                        SD_OUTPUT_EN, SD_OUTPUT_EN);
 247        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
 248                        MS_OUTPUT_EN, MS_OUTPUT_EN);
 249        return rtsx_pci_send_cmd(pcr, 100);
 250}
 251
 252static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
 253{
 254        if (pcr->option.ocp_en)
 255                rtsx_pci_disable_ocp(pcr);
 256
 257        rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
 258                        PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
 259        rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
 260
 261        return 0;
 262}
 263
 264static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 265{
 266        int err;
 267
 268        if (voltage == OUTPUT_3V3) {
 269                err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
 270                if (err < 0)
 271                        return err;
 272        } else if (voltage == OUTPUT_1V8) {
 273                err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
 274                if (err < 0)
 275                        return err;
 276                err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
 277                if (err < 0)
 278                        return err;
 279        } else {
 280                return -EINVAL;
 281        }
 282
 283        /* set pad drive */
 284        rtsx_pci_init_cmd(pcr);
 285        rts5227_fill_driving(pcr, voltage);
 286        return rtsx_pci_send_cmd(pcr, 100);
 287}
 288
 289static const struct pcr_ops rts5227_pcr_ops = {
 290        .fetch_vendor_settings = rts5227_fetch_vendor_settings,
 291        .extra_init_hw = rts5227_extra_init_hw,
 292        .optimize_phy = rts5227_optimize_phy,
 293        .turn_on_led = rts5227_turn_on_led,
 294        .turn_off_led = rts5227_turn_off_led,
 295        .enable_auto_blink = rts5227_enable_auto_blink,
 296        .disable_auto_blink = rts5227_disable_auto_blink,
 297        .card_power_on = rts5227_card_power_on,
 298        .card_power_off = rts5227_card_power_off,
 299        .switch_output_voltage = rts5227_switch_output_voltage,
 300        .cd_deglitch = NULL,
 301        .conv_clk_and_div_n = NULL,
 302};
 303
 304/* SD Pull Control Enable:
 305 *     SD_DAT[3:0] ==> pull up
 306 *     SD_CD       ==> pull up
 307 *     SD_WP       ==> pull up
 308 *     SD_CMD      ==> pull up
 309 *     SD_CLK      ==> pull down
 310 */
 311static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
 312        RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 313        RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 314        0,
 315};
 316
 317/* SD Pull Control Disable:
 318 *     SD_DAT[3:0] ==> pull down
 319 *     SD_CD       ==> pull up
 320 *     SD_WP       ==> pull down
 321 *     SD_CMD      ==> pull down
 322 *     SD_CLK      ==> pull down
 323 */
 324static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
 325        RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 326        RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 327        0,
 328};
 329
 330/* MS Pull Control Enable:
 331 *     MS CD       ==> pull up
 332 *     others      ==> pull down
 333 */
 334static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
 335        RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 336        RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 337        0,
 338};
 339
 340/* MS Pull Control Disable:
 341 *     MS CD       ==> pull up
 342 *     others      ==> pull down
 343 */
 344static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
 345        RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 346        RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 347        0,
 348};
 349
 350void rts5227_init_params(struct rtsx_pcr *pcr)
 351{
 352        pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 353        pcr->num_slots = 2;
 354        pcr->ops = &rts5227_pcr_ops;
 355
 356        pcr->flags = 0;
 357        pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 358        pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 359        pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 360        pcr->aspm_en = ASPM_L1_EN;
 361        pcr->aspm_mode = ASPM_MODE_CFG;
 362        pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
 363        pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
 364
 365        pcr->ic_version = rts5227_get_ic_version(pcr);
 366        pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
 367        pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
 368        pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
 369        pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
 370
 371        pcr->reg_pm_ctrl3 = PM_CTRL3;
 372}
 373
 374static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
 375{
 376        int err;
 377
 378        err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
 379                0x00);
 380        if (err < 0)
 381                return err;
 382
 383        if (is_version(pcr, 0x522A, IC_VER_A)) {
 384                err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 385                        PHY_RCR2_INIT_27S);
 386                if (err)
 387                        return err;
 388
 389                rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
 390                rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
 391                rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
 392                rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
 393        }
 394
 395        return 0;
 396}
 397
 398static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
 399{
 400        rts5227_extra_init_hw(pcr);
 401
 402        /* Power down OCP for power consumption */
 403        if (!pcr->card_exist)
 404                rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
 405                                OC_POWER_DOWN);
 406
 407        rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
 408                FUNC_FORCE_UPME_XMT_DBG);
 409        rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
 410        rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 411        rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
 412
 413        return 0;
 414}
 415
 416static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 417{
 418        int err;
 419
 420        if (voltage == OUTPUT_3V3) {
 421                err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
 422                if (err < 0)
 423                        return err;
 424        } else if (voltage == OUTPUT_1V8) {
 425                err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
 426                if (err < 0)
 427                        return err;
 428                err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
 429                if (err < 0)
 430                        return err;
 431        } else {
 432                return -EINVAL;
 433        }
 434
 435        /* set pad drive */
 436        rtsx_pci_init_cmd(pcr);
 437        rts5227_fill_driving(pcr, voltage);
 438        return rtsx_pci_send_cmd(pcr, 100);
 439}
 440
 441static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 442{
 443        struct rtsx_cr_option *option = &pcr->option;
 444        int aspm_L1_1, aspm_L1_2;
 445        u8 val = 0;
 446
 447        aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 448        aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 449
 450        if (active) {
 451                /* run, latency: 60us */
 452                if (aspm_L1_1)
 453                        val = option->ltr_l1off_snooze_sspwrgate;
 454        } else {
 455                /* l1off, latency: 300us */
 456                if (aspm_L1_2)
 457                        val = option->ltr_l1off_sspwrgate;
 458        }
 459
 460        rtsx_set_l1off_sub(pcr, val);
 461}
 462
 463/* rts522a operations mainly derived from rts5227, except phy/hw init setting.
 464 */
 465static const struct pcr_ops rts522a_pcr_ops = {
 466        .fetch_vendor_settings = rts5227_fetch_vendor_settings,
 467        .extra_init_hw = rts522a_extra_init_hw,
 468        .optimize_phy = rts522a_optimize_phy,
 469        .turn_on_led = rts5227_turn_on_led,
 470        .turn_off_led = rts5227_turn_off_led,
 471        .enable_auto_blink = rts5227_enable_auto_blink,
 472        .disable_auto_blink = rts5227_disable_auto_blink,
 473        .card_power_on = rts5227_card_power_on,
 474        .card_power_off = rts5227_card_power_off,
 475        .switch_output_voltage = rts522a_switch_output_voltage,
 476        .cd_deglitch = NULL,
 477        .conv_clk_and_div_n = NULL,
 478        .set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
 479};
 480
 481void rts522a_init_params(struct rtsx_pcr *pcr)
 482{
 483        struct rtsx_cr_option *option = &pcr->option;
 484
 485        rts5227_init_params(pcr);
 486        pcr->ops = &rts522a_pcr_ops;
 487        pcr->aspm_mode = ASPM_MODE_REG;
 488        pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
 489        pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
 490
 491        option->dev_flags = LTR_L1SS_PWR_GATE_EN;
 492        option->ltr_en = true;
 493
 494        /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 495        option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 496        option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 497        option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 498        option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 499        option->ltr_l1off_sspwrgate = 0x7F;
 500        option->ltr_l1off_snooze_sspwrgate = 0x78;
 501
 502        pcr->option.ocp_en = 1;
 503        if (pcr->option.ocp_en)
 504                pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 505        pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 506        pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
 507
 508}
 509