linux/drivers/media/tuners/qm1d1c0042.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Sharp QM1D1C0042 8PSK tuner driver
   4 *
   5 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
   6 */
   7
   8/*
   9 * NOTICE:
  10 * As the disclosed information on the chip is very limited,
  11 * this driver lacks some features, including chip config like IF freq.
  12 * It assumes that users of this driver (such as a PCI bridge of
  13 * DTV receiver cards) know the relevant info and
  14 * configure the chip via I2C if necessary.
  15 *
  16 * Currently, PT3 driver is the only one that uses this driver,
  17 * and contains init/config code in its firmware.
  18 * Thus some part of the code might be dependent on PT3 specific config.
  19 */
  20
  21#include <linux/kernel.h>
  22#include <linux/math64.h>
  23#include "qm1d1c0042.h"
  24
  25#define QM1D1C0042_NUM_REGS 0x20
  26#define QM1D1C0042_NUM_REG_ROWS 2
  27
  28static const u8
  29reg_initval[QM1D1C0042_NUM_REG_ROWS][QM1D1C0042_NUM_REGS] = { {
  30                0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33,
  31                0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
  32                0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86,
  33                0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00
  34        }, {
  35                0x68, 0x1c, 0xc0, 0x10, 0xbc, 0xc1, 0x11, 0x33,
  36                0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
  37                0x00, 0xff, 0xf3, 0x00, 0x3f, 0x25, 0x5c, 0xd6,
  38                0x55, 0xcf, 0x95, 0xf6, 0x36, 0xf2, 0x09, 0x00
  39        }
  40};
  41
  42static int reg_index;
  43
  44static const struct qm1d1c0042_config default_cfg = {
  45        .xtal_freq = 16000,
  46        .lpf = 1,
  47        .fast_srch = 0,
  48        .lpf_wait = 20,
  49        .fast_srch_wait = 4,
  50        .normal_srch_wait = 15,
  51};
  52
  53struct qm1d1c0042_state {
  54        struct qm1d1c0042_config cfg;
  55        struct i2c_client *i2c;
  56        u8 regs[QM1D1C0042_NUM_REGS];
  57};
  58
  59static struct qm1d1c0042_state *cfg_to_state(struct qm1d1c0042_config *c)
  60{
  61        return container_of(c, struct qm1d1c0042_state, cfg);
  62}
  63
  64static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val)
  65{
  66        u8 wbuf[2] = { reg, val };
  67        int ret;
  68
  69        ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf));
  70        if (ret >= 0 && ret < sizeof(wbuf))
  71                ret = -EIO;
  72        return (ret == sizeof(wbuf)) ? 0 : ret;
  73}
  74
  75static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val)
  76{
  77        struct i2c_msg msgs[2] = {
  78                {
  79                        .addr = state->i2c->addr,
  80                        .flags = 0,
  81                        .buf = &reg,
  82                        .len = 1,
  83                },
  84                {
  85                        .addr = state->i2c->addr,
  86                        .flags = I2C_M_RD,
  87                        .buf = val,
  88                        .len = 1,
  89                },
  90        };
  91        int ret;
  92
  93        ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs));
  94        if (ret >= 0 && ret < ARRAY_SIZE(msgs))
  95                ret = -EIO;
  96        return (ret == ARRAY_SIZE(msgs)) ? 0 : ret;
  97}
  98
  99
 100static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast)
 101{
 102        if (fast)
 103                state->regs[0x03] |= 0x01; /* set fast search mode */
 104        else
 105                state->regs[0x03] &= ~0x01 & 0xff;
 106
 107        return reg_write(state, 0x03, state->regs[0x03]);
 108}
 109
 110static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state)
 111{
 112        int ret;
 113
 114        state->regs[0x01] |= 1 << 3;             /* BB_Reg_enable */
 115        state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */
 116        state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */
 117        ret = reg_write(state, 0x01, state->regs[0x01]);
 118        if (ret == 0)
 119                ret = reg_write(state, 0x05, state->regs[0x05]);
 120
 121        if (ret < 0)
 122                dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
 123                        __func__, state->cfg.fe->dvb->num, state->cfg.fe->id);
 124        return ret;
 125}
 126
 127/* tuner_ops */
 128
 129static int qm1d1c0042_set_config(struct dvb_frontend *fe, void *priv_cfg)
 130{
 131        struct qm1d1c0042_state *state;
 132        struct qm1d1c0042_config *cfg;
 133
 134        state = fe->tuner_priv;
 135        cfg = priv_cfg;
 136
 137        if (cfg->fe)
 138                state->cfg.fe = cfg->fe;
 139
 140        if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT)
 141                dev_warn(&state->i2c->dev,
 142                        "(%s) changing xtal_freq not supported. ", __func__);
 143        state->cfg.xtal_freq = default_cfg.xtal_freq;
 144
 145        state->cfg.lpf = cfg->lpf;
 146        state->cfg.fast_srch = cfg->fast_srch;
 147
 148        if (cfg->lpf_wait != QM1D1C0042_CFG_WAIT_DFLT)
 149                state->cfg.lpf_wait = cfg->lpf_wait;
 150        else
 151                state->cfg.lpf_wait = default_cfg.lpf_wait;
 152
 153        if (cfg->fast_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
 154                state->cfg.fast_srch_wait = cfg->fast_srch_wait;
 155        else
 156                state->cfg.fast_srch_wait = default_cfg.fast_srch_wait;
 157
 158        if (cfg->normal_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
 159                state->cfg.normal_srch_wait = cfg->normal_srch_wait;
 160        else
 161                state->cfg.normal_srch_wait = default_cfg.normal_srch_wait;
 162        return 0;
 163}
 164
 165/* divisor, vco_band parameters */
 166/*  {maxfreq,  param1(band?), param2(div?) */
 167static const u32 conv_table[9][3] = {
 168        { 2151000, 1, 7 },
 169        { 1950000, 1, 6 },
 170        { 1800000, 1, 5 },
 171        { 1600000, 1, 4 },
 172        { 1450000, 1, 3 },
 173        { 1250000, 1, 2 },
 174        { 1200000, 0, 7 },
 175        {  975000, 0, 6 },
 176        {  950000, 0, 0 }
 177};
 178
 179static int qm1d1c0042_set_params(struct dvb_frontend *fe)
 180{
 181        struct qm1d1c0042_state *state;
 182        u32 freq;
 183        int i, ret;
 184        u8 val, mask;
 185        u32 a, sd;
 186        s32 b;
 187
 188        state = fe->tuner_priv;
 189        freq = fe->dtv_property_cache.frequency;
 190
 191        state->regs[0x08] &= 0xf0;
 192        state->regs[0x08] |= 0x09;
 193
 194        state->regs[0x13] &= 0x9f;
 195        state->regs[0x13] |= 0x20;
 196
 197        /* div2/vco_band */
 198        val = state->regs[0x02] & 0x0f;
 199        for (i = 0; i < 8; i++)
 200                if (freq < conv_table[i][0] && freq >= conv_table[i + 1][0]) {
 201                        val |= conv_table[i][1] << 7;
 202                        val |= conv_table[i][2] << 4;
 203                        break;
 204                }
 205        ret = reg_write(state, 0x02, val);
 206        if (ret < 0)
 207                return ret;
 208
 209        a = DIV_ROUND_CLOSEST(freq, state->cfg.xtal_freq);
 210
 211        state->regs[0x06] &= 0x40;
 212        state->regs[0x06] |= (a - 12) / 4;
 213        ret = reg_write(state, 0x06, state->regs[0x06]);
 214        if (ret < 0)
 215                return ret;
 216
 217        state->regs[0x07] &= 0xf0;
 218        state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f;
 219        ret = reg_write(state, 0x07, state->regs[0x07]);
 220        if (ret < 0)
 221                return ret;
 222
 223        /* LPF */
 224        val = state->regs[0x08];
 225        if (state->cfg.lpf) {
 226                /* LPF_CLK, LPF_FC */
 227                val &= 0xf0;
 228                val |= 0x02;
 229        }
 230        ret = reg_write(state, 0x08, val);
 231        if (ret < 0)
 232                return ret;
 233
 234        /*
 235         * b = (freq / state->cfg.xtal_freq - a) << 20;
 236         * sd = b          (b >= 0)
 237         *      1<<22 + b  (b < 0)
 238         */
 239        b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq)
 240                           - (((s64) a) << 20);
 241
 242        if (b >= 0)
 243                sd = b;
 244        else
 245                sd = (1 << 22) + b;
 246
 247        state->regs[0x09] &= 0xc0;
 248        state->regs[0x09] |= (sd >> 16) & 0x3f;
 249        state->regs[0x0a] = (sd >> 8) & 0xff;
 250        state->regs[0x0b] = sd & 0xff;
 251        ret = reg_write(state, 0x09, state->regs[0x09]);
 252        if (ret == 0)
 253                ret = reg_write(state, 0x0a, state->regs[0x0a]);
 254        if (ret == 0)
 255                ret = reg_write(state, 0x0b, state->regs[0x0b]);
 256        if (ret != 0)
 257                return ret;
 258
 259        if (!state->cfg.lpf) {
 260                /* CSEL_Offset */
 261                ret = reg_write(state, 0x13, state->regs[0x13]);
 262                if (ret < 0)
 263                        return ret;
 264        }
 265
 266        /* VCO_TM, LPF_TM */
 267        mask = state->cfg.lpf ? 0x3f : 0x7f;
 268        val = state->regs[0x0c] & mask;
 269        ret = reg_write(state, 0x0c, val);
 270        if (ret < 0)
 271                return ret;
 272        usleep_range(2000, 3000);
 273        val = state->regs[0x0c] | ~mask;
 274        ret = reg_write(state, 0x0c, val);
 275        if (ret < 0)
 276                return ret;
 277
 278        if (state->cfg.lpf)
 279                msleep(state->cfg.lpf_wait);
 280        else if (state->regs[0x03] & 0x01)
 281                msleep(state->cfg.fast_srch_wait);
 282        else
 283                msleep(state->cfg.normal_srch_wait);
 284
 285        if (state->cfg.lpf) {
 286                /* LPF_FC */
 287                ret = reg_write(state, 0x08, 0x09);
 288                if (ret < 0)
 289                        return ret;
 290
 291                /* CSEL_Offset */
 292                ret = reg_write(state, 0x13, state->regs[0x13]);
 293                if (ret < 0)
 294                        return ret;
 295        }
 296        return 0;
 297}
 298
 299static int qm1d1c0042_sleep(struct dvb_frontend *fe)
 300{
 301        struct qm1d1c0042_state *state;
 302        int ret;
 303
 304        state = fe->tuner_priv;
 305        state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */
 306        state->regs[0x01] |= 1 << 0;             /* STDBY */
 307        state->regs[0x05] |= 1 << 3;             /* pfd_rst STANDBY */
 308        ret = reg_write(state, 0x05, state->regs[0x05]);
 309        if (ret == 0)
 310                ret = reg_write(state, 0x01, state->regs[0x01]);
 311        if (ret < 0)
 312                dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
 313                        __func__, fe->dvb->num, fe->id);
 314        return ret;
 315}
 316
 317static int qm1d1c0042_init(struct dvb_frontend *fe)
 318{
 319        struct qm1d1c0042_state *state;
 320        u8 val;
 321        int i, ret;
 322
 323        state = fe->tuner_priv;
 324
 325        reg_write(state, 0x01, 0x0c);
 326        reg_write(state, 0x01, 0x0c);
 327
 328        ret = reg_write(state, 0x01, 0x0c); /* soft reset on */
 329        if (ret < 0)
 330                goto failed;
 331        usleep_range(2000, 3000);
 332
 333        ret = reg_write(state, 0x01, 0x1c); /* soft reset off */
 334        if (ret < 0)
 335                goto failed;
 336
 337        /* check ID and choose initial registers corresponding ID */
 338        ret = reg_read(state, 0x00, &val);
 339        if (ret < 0)
 340                goto failed;
 341        for (reg_index = 0; reg_index < QM1D1C0042_NUM_REG_ROWS;
 342             reg_index++) {
 343                if (val == reg_initval[reg_index][0x00])
 344                        break;
 345        }
 346        if (reg_index >= QM1D1C0042_NUM_REG_ROWS) {
 347                ret = -EINVAL;
 348                goto failed;
 349        }
 350        memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS);
 351        usleep_range(2000, 3000);
 352
 353        state->regs[0x0c] |= 0x40;
 354        ret = reg_write(state, 0x0c, state->regs[0x0c]);
 355        if (ret < 0)
 356                goto failed;
 357        msleep(state->cfg.lpf_wait);
 358
 359        /* set all writable registers */
 360        for (i = 1; i <= 0x0c ; i++) {
 361                ret = reg_write(state, i, state->regs[i]);
 362                if (ret < 0)
 363                        goto failed;
 364        }
 365        for (i = 0x11; i < QM1D1C0042_NUM_REGS; i++) {
 366                ret = reg_write(state, i, state->regs[i]);
 367                if (ret < 0)
 368                        goto failed;
 369        }
 370
 371        ret = qm1d1c0042_wakeup(state);
 372        if (ret < 0)
 373                goto failed;
 374
 375        ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch);
 376        if (ret < 0)
 377                goto failed;
 378
 379        return ret;
 380
 381failed:
 382        dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
 383                __func__, fe->dvb->num, fe->id);
 384        return ret;
 385}
 386
 387/* I2C driver functions */
 388
 389static const struct dvb_tuner_ops qm1d1c0042_ops = {
 390        .info = {
 391                .name = "Sharp QM1D1C0042",
 392
 393                .frequency_min_hz =  950 * MHz,
 394                .frequency_max_hz = 2150 * MHz,
 395        },
 396
 397        .init = qm1d1c0042_init,
 398        .sleep = qm1d1c0042_sleep,
 399        .set_config = qm1d1c0042_set_config,
 400        .set_params = qm1d1c0042_set_params,
 401};
 402
 403
 404static int qm1d1c0042_probe(struct i2c_client *client,
 405                            const struct i2c_device_id *id)
 406{
 407        struct qm1d1c0042_state *state;
 408        struct qm1d1c0042_config *cfg;
 409        struct dvb_frontend *fe;
 410
 411        state = kzalloc(sizeof(*state), GFP_KERNEL);
 412        if (!state)
 413                return -ENOMEM;
 414        state->i2c = client;
 415
 416        cfg = client->dev.platform_data;
 417        fe = cfg->fe;
 418        fe->tuner_priv = state;
 419        qm1d1c0042_set_config(fe, cfg);
 420        memcpy(&fe->ops.tuner_ops, &qm1d1c0042_ops, sizeof(qm1d1c0042_ops));
 421
 422        i2c_set_clientdata(client, &state->cfg);
 423        dev_info(&client->dev, "Sharp QM1D1C0042 attached.\n");
 424        return 0;
 425}
 426
 427static int qm1d1c0042_remove(struct i2c_client *client)
 428{
 429        struct qm1d1c0042_state *state;
 430
 431        state = cfg_to_state(i2c_get_clientdata(client));
 432        state->cfg.fe->tuner_priv = NULL;
 433        kfree(state);
 434        return 0;
 435}
 436
 437
 438static const struct i2c_device_id qm1d1c0042_id[] = {
 439        {"qm1d1c0042", 0},
 440        {}
 441};
 442MODULE_DEVICE_TABLE(i2c, qm1d1c0042_id);
 443
 444static struct i2c_driver qm1d1c0042_driver = {
 445        .driver = {
 446                .name   = "qm1d1c0042",
 447        },
 448        .probe          = qm1d1c0042_probe,
 449        .remove         = qm1d1c0042_remove,
 450        .id_table       = qm1d1c0042_id,
 451};
 452
 453module_i2c_driver(qm1d1c0042_driver);
 454
 455MODULE_DESCRIPTION("Sharp QM1D1C0042 tuner");
 456MODULE_AUTHOR("Akihiro TSUKADA");
 457MODULE_LICENSE("GPL");
 458