linux/arch/powerpc/platforms/powermac/pic.c
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   1/*
   2 *  Support for the interrupt controllers found on Power Macintosh,
   3 *  currently Apple's "Grand Central" interrupt controller in all
   4 *  it's incarnations. OpenPIC support used on newer machines is
   5 *  in a separate file
   6 *
   7 *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
   8 *  Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   9 *                     IBM, Corp.
  10 *
  11 *  This program is free software; you can redistribute it and/or
  12 *  modify it under the terms of the GNU General Public License
  13 *  as published by the Free Software Foundation; either version
  14 *  2 of the License, or (at your option) any later version.
  15 *
  16 */
  17
  18#include <linux/stddef.h>
  19#include <linux/init.h>
  20#include <linux/sched.h>
  21#include <linux/signal.h>
  22#include <linux/pci.h>
  23#include <linux/interrupt.h>
  24#include <linux/syscore_ops.h>
  25#include <linux/adb.h>
  26#include <linux/pmu.h>
  27
  28#include <asm/sections.h>
  29#include <asm/io.h>
  30#include <asm/smp.h>
  31#include <asm/prom.h>
  32#include <asm/pci-bridge.h>
  33#include <asm/time.h>
  34#include <asm/pmac_feature.h>
  35#include <asm/mpic.h>
  36#include <asm/xmon.h>
  37
  38#include "pmac.h"
  39
  40#ifdef CONFIG_PPC32
  41struct pmac_irq_hw {
  42        unsigned int    event;
  43        unsigned int    enable;
  44        unsigned int    ack;
  45        unsigned int    level;
  46};
  47
  48/* Workaround flags for 32bit powermac machines */
  49unsigned int of_irq_workarounds;
  50struct device_node *of_irq_dflt_pic;
  51
  52/* Default addresses */
  53static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
  54
  55static int max_irqs;
  56static int max_real_irqs;
  57
  58static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
  59
  60#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
  61static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
  62static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  63static int pmac_irq_cascade = -1;
  64static struct irq_host *pmac_pic_host;
  65
  66static void __pmac_retrigger(unsigned int irq_nr)
  67{
  68        if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
  69                __set_bit(irq_nr, ppc_lost_interrupts);
  70                irq_nr = pmac_irq_cascade;
  71                mb();
  72        }
  73        if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
  74                atomic_inc(&ppc_n_lost_interrupts);
  75                set_dec(1);
  76        }
  77}
  78
  79static void pmac_mask_and_ack_irq(struct irq_data *d)
  80{
  81        unsigned int src = irqd_to_hwirq(d);
  82        unsigned long bit = 1UL << (src & 0x1f);
  83        int i = src >> 5;
  84        unsigned long flags;
  85
  86        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
  87        __clear_bit(src, ppc_cached_irq_mask);
  88        if (__test_and_clear_bit(src, ppc_lost_interrupts))
  89                atomic_dec(&ppc_n_lost_interrupts);
  90        out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
  91        out_le32(&pmac_irq_hw[i]->ack, bit);
  92        do {
  93                /* make sure ack gets to controller before we enable
  94                   interrupts */
  95                mb();
  96        } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
  97                != (ppc_cached_irq_mask[i] & bit));
  98        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
  99}
 100
 101static void pmac_ack_irq(struct irq_data *d)
 102{
 103        unsigned int src = irqd_to_hwirq(d);
 104        unsigned long bit = 1UL << (src & 0x1f);
 105        int i = src >> 5;
 106        unsigned long flags;
 107
 108        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 109        if (__test_and_clear_bit(src, ppc_lost_interrupts))
 110                atomic_dec(&ppc_n_lost_interrupts);
 111        out_le32(&pmac_irq_hw[i]->ack, bit);
 112        (void)in_le32(&pmac_irq_hw[i]->ack);
 113        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 114}
 115
 116static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
 117{
 118        unsigned long bit = 1UL << (irq_nr & 0x1f);
 119        int i = irq_nr >> 5;
 120
 121        if ((unsigned)irq_nr >= max_irqs)
 122                return;
 123
 124        /* enable unmasked interrupts */
 125        out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 126
 127        do {
 128                /* make sure mask gets to controller before we
 129                   return to user */
 130                mb();
 131        } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 132                != (ppc_cached_irq_mask[i] & bit));
 133
 134        /*
 135         * Unfortunately, setting the bit in the enable register
 136         * when the device interrupt is already on *doesn't* set
 137         * the bit in the flag register or request another interrupt.
 138         */
 139        if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
 140                __pmac_retrigger(irq_nr);
 141}
 142
 143/* When an irq gets requested for the first client, if it's an
 144 * edge interrupt, we clear any previous one on the controller
 145 */
 146static unsigned int pmac_startup_irq(struct irq_data *d)
 147{
 148        unsigned long flags;
 149        unsigned int src = irqd_to_hwirq(d);
 150        unsigned long bit = 1UL << (src & 0x1f);
 151        int i = src >> 5;
 152
 153        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 154        if (!irqd_is_level_type(d))
 155                out_le32(&pmac_irq_hw[i]->ack, bit);
 156        __set_bit(src, ppc_cached_irq_mask);
 157        __pmac_set_irq_mask(src, 0);
 158        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 159
 160        return 0;
 161}
 162
 163static void pmac_mask_irq(struct irq_data *d)
 164{
 165        unsigned long flags;
 166        unsigned int src = irqd_to_hwirq(d);
 167
 168        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 169        __clear_bit(src, ppc_cached_irq_mask);
 170        __pmac_set_irq_mask(src, 1);
 171        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 172}
 173
 174static void pmac_unmask_irq(struct irq_data *d)
 175{
 176        unsigned long flags;
 177        unsigned int src = irqd_to_hwirq(d);
 178
 179        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 180        __set_bit(src, ppc_cached_irq_mask);
 181        __pmac_set_irq_mask(src, 0);
 182        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 183}
 184
 185static int pmac_retrigger(struct irq_data *d)
 186{
 187        unsigned long flags;
 188
 189        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 190        __pmac_retrigger(irqd_to_hwirq(d));
 191        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 192        return 1;
 193}
 194
 195static struct irq_chip pmac_pic = {
 196        .name           = "PMAC-PIC",
 197        .irq_startup    = pmac_startup_irq,
 198        .irq_mask       = pmac_mask_irq,
 199        .irq_ack        = pmac_ack_irq,
 200        .irq_mask_ack   = pmac_mask_and_ack_irq,
 201        .irq_unmask     = pmac_unmask_irq,
 202        .irq_retrigger  = pmac_retrigger,
 203};
 204
 205static irqreturn_t gatwick_action(int cpl, void *dev_id)
 206{
 207        unsigned long flags;
 208        int irq, bits;
 209        int rc = IRQ_NONE;
 210
 211        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 212        for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
 213                int i = irq >> 5;
 214                bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 215                bits |= in_le32(&pmac_irq_hw[i]->level);
 216                bits &= ppc_cached_irq_mask[i];
 217                if (bits == 0)
 218                        continue;
 219                irq += __ilog2(bits);
 220                raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 221                generic_handle_irq(irq);
 222                raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 223                rc = IRQ_HANDLED;
 224        }
 225        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 226        return rc;
 227}
 228
 229static unsigned int pmac_pic_get_irq(void)
 230{
 231        int irq;
 232        unsigned long bits = 0;
 233        unsigned long flags;
 234
 235#ifdef CONFIG_PPC_PMAC32_PSURGE
 236        /* IPI's are a hack on the powersurge -- Cort */
 237        if (smp_processor_id() != 0) {
 238                return  psurge_secondary_virq;
 239        }
 240#endif /* CONFIG_PPC_PMAC32_PSURGE */
 241        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 242        for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
 243                int i = irq >> 5;
 244                bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 245                bits |= in_le32(&pmac_irq_hw[i]->level);
 246                bits &= ppc_cached_irq_mask[i];
 247                if (bits == 0)
 248                        continue;
 249                irq += __ilog2(bits);
 250                break;
 251        }
 252        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 253        if (unlikely(irq < 0))
 254                return NO_IRQ;
 255        return irq_linear_revmap(pmac_pic_host, irq);
 256}
 257
 258#ifdef CONFIG_XMON
 259static struct irqaction xmon_action = {
 260        .handler        = xmon_irq,
 261        .flags          = 0,
 262        .name           = "NMI - XMON"
 263};
 264#endif
 265
 266static struct irqaction gatwick_cascade_action = {
 267        .handler        = gatwick_action,
 268        .name           = "cascade",
 269};
 270
 271static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
 272{
 273        /* We match all, we don't always have a node anyway */
 274        return 1;
 275}
 276
 277static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
 278                             irq_hw_number_t hw)
 279{
 280        if (hw >= max_irqs)
 281                return -EINVAL;
 282
 283        /* Mark level interrupts, set delayed disable for edge ones and set
 284         * handlers
 285         */
 286        irq_set_status_flags(virq, IRQ_LEVEL);
 287        irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
 288        return 0;
 289}
 290
 291static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct,
 292                               const u32 *intspec, unsigned int intsize,
 293                               irq_hw_number_t *out_hwirq,
 294                               unsigned int *out_flags)
 295
 296{
 297        *out_flags = IRQ_TYPE_NONE;
 298        *out_hwirq = *intspec;
 299        return 0;
 300}
 301
 302static struct irq_host_ops pmac_pic_host_ops = {
 303        .match = pmac_pic_host_match,
 304        .map = pmac_pic_host_map,
 305        .xlate = pmac_pic_host_xlate,
 306};
 307
 308static void __init pmac_pic_probe_oldstyle(void)
 309{
 310        int i;
 311        struct device_node *master = NULL;
 312        struct device_node *slave = NULL;
 313        u8 __iomem *addr;
 314        struct resource r;
 315
 316        /* Set our get_irq function */
 317        ppc_md.get_irq = pmac_pic_get_irq;
 318
 319        /*
 320         * Find the interrupt controller type & node
 321         */
 322
 323        if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
 324                max_irqs = max_real_irqs = 32;
 325        } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
 326                max_irqs = max_real_irqs = 32;
 327                /* We might have a second cascaded ohare */
 328                slave = of_find_node_by_name(NULL, "pci106b,7");
 329                if (slave)
 330                        max_irqs = 64;
 331        } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
 332                max_irqs = max_real_irqs = 64;
 333
 334                /* We might have a second cascaded heathrow */
 335                slave = of_find_node_by_name(master, "mac-io");
 336
 337                /* Check ordering of master & slave */
 338                if (of_device_is_compatible(master, "gatwick")) {
 339                        struct device_node *tmp;
 340                        BUG_ON(slave == NULL);
 341                        tmp = master;
 342                        master = slave;
 343                        slave = tmp;
 344                }
 345
 346                /* We found a slave */
 347                if (slave)
 348                        max_irqs = 128;
 349        }
 350        BUG_ON(master == NULL);
 351
 352        /*
 353         * Allocate an irq host
 354         */
 355        pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs,
 356                                       &pmac_pic_host_ops,
 357                                       max_irqs);
 358        BUG_ON(pmac_pic_host == NULL);
 359        irq_set_default_host(pmac_pic_host);
 360
 361        /* Get addresses of first controller if we have a node for it */
 362        BUG_ON(of_address_to_resource(master, 0, &r));
 363
 364        /* Map interrupts of primary controller */
 365        addr = (u8 __iomem *) ioremap(r.start, 0x40);
 366        i = 0;
 367        pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
 368                (addr + 0x20);
 369        if (max_real_irqs > 32)
 370                pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
 371                        (addr + 0x10);
 372        of_node_put(master);
 373
 374        printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n",
 375               master->full_name, max_real_irqs);
 376
 377        /* Map interrupts of cascaded controller */
 378        if (slave && !of_address_to_resource(slave, 0, &r)) {
 379                addr = (u8 __iomem *)ioremap(r.start, 0x40);
 380                pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
 381                        (addr + 0x20);
 382                if (max_irqs > 64)
 383                        pmac_irq_hw[i++] =
 384                                (volatile struct pmac_irq_hw __iomem *)
 385                                (addr + 0x10);
 386                pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
 387
 388                printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
 389                       " cascade: %d\n", slave->full_name,
 390                       max_irqs - max_real_irqs, pmac_irq_cascade);
 391        }
 392        of_node_put(slave);
 393
 394        /* Disable all interrupts in all controllers */
 395        for (i = 0; i * 32 < max_irqs; ++i)
 396                out_le32(&pmac_irq_hw[i]->enable, 0);
 397
 398        /* Hookup cascade irq */
 399        if (slave && pmac_irq_cascade != NO_IRQ)
 400                setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
 401
 402        printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
 403#ifdef CONFIG_XMON
 404        setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
 405#endif
 406}
 407
 408int of_irq_map_oldworld(struct device_node *device, int index,
 409                        struct of_irq *out_irq)
 410{
 411        const u32 *ints = NULL;
 412        int intlen;
 413
 414        /*
 415         * Old machines just have a list of interrupt numbers
 416         * and no interrupt-controller nodes. We also have dodgy
 417         * cases where the APPL,interrupts property is completely
 418         * missing behind pci-pci bridges and we have to get it
 419         * from the parent (the bridge itself, as apple just wired
 420         * everything together on these)
 421         */
 422        while (device) {
 423                ints = of_get_property(device, "AAPL,interrupts", &intlen);
 424                if (ints != NULL)
 425                        break;
 426                device = device->parent;
 427                if (device && strcmp(device->type, "pci") != 0)
 428                        break;
 429        }
 430        if (ints == NULL)
 431                return -EINVAL;
 432        intlen /= sizeof(u32);
 433
 434        if (index >= intlen)
 435                return -EINVAL;
 436
 437        out_irq->controller = NULL;
 438        out_irq->specifier[0] = ints[index];
 439        out_irq->size = 1;
 440
 441        return 0;
 442}
 443#endif /* CONFIG_PPC32 */
 444
 445static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
 446{
 447#if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
 448        struct device_node* pswitch;
 449        int nmi_irq;
 450
 451        pswitch = of_find_node_by_name(NULL, "programmer-switch");
 452        if (pswitch) {
 453                nmi_irq = irq_of_parse_and_map(pswitch, 0);
 454                if (nmi_irq != NO_IRQ) {
 455                        mpic_irq_set_priority(nmi_irq, 9);
 456                        setup_irq(nmi_irq, &xmon_action);
 457                }
 458                of_node_put(pswitch);
 459        }
 460#endif  /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
 461}
 462
 463static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
 464                                                int master)
 465{
 466        const char *name = master ? " MPIC 1   " : " MPIC 2   ";
 467        struct mpic *mpic;
 468        unsigned int flags = master ? 0 : MPIC_SECONDARY;
 469
 470        pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
 471
 472        flags |= MPIC_WANTS_RESET;
 473        if (of_get_property(np, "big-endian", NULL))
 474                flags |= MPIC_BIG_ENDIAN;
 475
 476        /* Primary Big Endian means HT interrupts. This is quite dodgy
 477         * but works until I find a better way
 478         */
 479        if (master && (flags & MPIC_BIG_ENDIAN))
 480                flags |= MPIC_U3_HT_IRQS;
 481
 482        mpic = mpic_alloc(np, 0, flags, 0, 0, name);
 483        if (mpic == NULL)
 484                return NULL;
 485
 486        mpic_init(mpic);
 487
 488        return mpic;
 489 }
 490
 491static int __init pmac_pic_probe_mpic(void)
 492{
 493        struct mpic *mpic1, *mpic2;
 494        struct device_node *np, *master = NULL, *slave = NULL;
 495
 496        /* We can have up to 2 MPICs cascaded */
 497        for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
 498                     != NULL;) {
 499                if (master == NULL &&
 500                    of_get_property(np, "interrupts", NULL) == NULL)
 501                        master = of_node_get(np);
 502                else if (slave == NULL)
 503                        slave = of_node_get(np);
 504                if (master && slave)
 505                        break;
 506        }
 507
 508        /* Check for bogus setups */
 509        if (master == NULL && slave != NULL) {
 510                master = slave;
 511                slave = NULL;
 512        }
 513
 514        /* Not found, default to good old pmac pic */
 515        if (master == NULL)
 516                return -ENODEV;
 517
 518        /* Set master handler */
 519        ppc_md.get_irq = mpic_get_irq;
 520
 521        /* Setup master */
 522        mpic1 = pmac_setup_one_mpic(master, 1);
 523        BUG_ON(mpic1 == NULL);
 524
 525        /* Install NMI if any */
 526        pmac_pic_setup_mpic_nmi(mpic1);
 527
 528        of_node_put(master);
 529
 530        /* Set up a cascaded controller, if present */
 531        if (slave) {
 532                mpic2 = pmac_setup_one_mpic(slave, 0);
 533                if (mpic2 == NULL)
 534                        printk(KERN_ERR "Failed to setup slave MPIC\n");
 535                of_node_put(slave);
 536        }
 537
 538        return 0;
 539}
 540
 541
 542void __init pmac_pic_init(void)
 543{
 544        /* We configure the OF parsing based on our oldworld vs. newworld
 545         * platform type and wether we were booted by BootX.
 546         */
 547#ifdef CONFIG_PPC32
 548        if (!pmac_newworld)
 549                of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
 550        if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
 551                of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
 552
 553        /* If we don't have phandles on a newworld, then try to locate a
 554         * default interrupt controller (happens when booting with BootX).
 555         * We do a first match here, hopefully, that only ever happens on
 556         * machines with one controller.
 557         */
 558        if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
 559                struct device_node *np;
 560
 561                for_each_node_with_property(np, "interrupt-controller") {
 562                        /* Skip /chosen/interrupt-controller */
 563                        if (strcmp(np->name, "chosen") == 0)
 564                                continue;
 565                        /* It seems like at least one person wants
 566                         * to use BootX on a machine with an AppleKiwi
 567                         * controller which happens to pretend to be an
 568                         * interrupt controller too. */
 569                        if (strcmp(np->name, "AppleKiwi") == 0)
 570                                continue;
 571                        /* I think we found one ! */
 572                        of_irq_dflt_pic = np;
 573                        break;
 574                }
 575        }
 576#endif /* CONFIG_PPC32 */
 577
 578        /* We first try to detect Apple's new Core99 chipset, since mac-io
 579         * is quite different on those machines and contains an IBM MPIC2.
 580         */
 581        if (pmac_pic_probe_mpic() == 0)
 582                return;
 583
 584#ifdef CONFIG_PPC32
 585        pmac_pic_probe_oldstyle();
 586#endif
 587}
 588
 589#if defined(CONFIG_PM) && defined(CONFIG_PPC32)
 590/*
 591 * These procedures are used in implementing sleep on the powerbooks.
 592 * sleep_save_intrs() saves the states of all interrupt enables
 593 * and disables all interrupts except for the nominated one.
 594 * sleep_restore_intrs() restores the states of all interrupt enables.
 595 */
 596unsigned long sleep_save_mask[2];
 597
 598/* This used to be passed by the PMU driver but that link got
 599 * broken with the new driver model. We use this tweak for now...
 600 * We really want to do things differently though...
 601 */
 602static int pmacpic_find_viaint(void)
 603{
 604        int viaint = -1;
 605
 606#ifdef CONFIG_ADB_PMU
 607        struct device_node *np;
 608
 609        if (pmu_get_model() != PMU_OHARE_BASED)
 610                goto not_found;
 611        np = of_find_node_by_name(NULL, "via-pmu");
 612        if (np == NULL)
 613                goto not_found;
 614        viaint = irq_of_parse_and_map(np, 0);
 615
 616not_found:
 617#endif /* CONFIG_ADB_PMU */
 618        return viaint;
 619}
 620
 621static int pmacpic_suspend(void)
 622{
 623        int viaint = pmacpic_find_viaint();
 624
 625        sleep_save_mask[0] = ppc_cached_irq_mask[0];
 626        sleep_save_mask[1] = ppc_cached_irq_mask[1];
 627        ppc_cached_irq_mask[0] = 0;
 628        ppc_cached_irq_mask[1] = 0;
 629        if (viaint > 0)
 630                set_bit(viaint, ppc_cached_irq_mask);
 631        out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
 632        if (max_real_irqs > 32)
 633                out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
 634        (void)in_le32(&pmac_irq_hw[0]->event);
 635        /* make sure mask gets to controller before we return to caller */
 636        mb();
 637        (void)in_le32(&pmac_irq_hw[0]->enable);
 638
 639        return 0;
 640}
 641
 642static void pmacpic_resume(void)
 643{
 644        int i;
 645
 646        out_le32(&pmac_irq_hw[0]->enable, 0);
 647        if (max_real_irqs > 32)
 648                out_le32(&pmac_irq_hw[1]->enable, 0);
 649        mb();
 650        for (i = 0; i < max_real_irqs; ++i)
 651                if (test_bit(i, sleep_save_mask))
 652                        pmac_unmask_irq(irq_get_irq_data(i));
 653}
 654
 655static struct syscore_ops pmacpic_syscore_ops = {
 656        .suspend        = pmacpic_suspend,
 657        .resume         = pmacpic_resume,
 658};
 659
 660static int __init init_pmacpic_syscore(void)
 661{
 662        if (pmac_irq_hw[0])
 663                register_syscore_ops(&pmacpic_syscore_ops);
 664        return 0;
 665}
 666
 667machine_subsys_initcall(powermac, init_pmacpic_syscore);
 668
 669#endif /* CONFIG_PM && CONFIG_PPC32 */
 670