linux/arch/powerpc/platforms/85xx/p1022_ds.c
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   1/*
   2 * P1022DS board specific routines
   3 *
   4 * Authors: Travis Wheatley <travis.wheatley@freescale.com>
   5 *          Dave Liu <daveliu@freescale.com>
   6 *          Timur Tabi <timur@freescale.com>
   7 *
   8 * Copyright 2010 Freescale Semiconductor, Inc.
   9 *
  10 * This file is taken from the Freescale P1022DS BSP, with modifications:
  11 * 2) No AMP support
  12 * 3) No PCI endpoint support
  13 *
  14 * This file is licensed under the terms of the GNU General Public License
  15 * version 2.  This program is licensed "as is" without any warranty of any
  16 * kind, whether express or implied.
  17 */
  18
  19#include <linux/pci.h>
  20#include <linux/of_platform.h>
  21#include <linux/memblock.h>
  22#include <asm/div64.h>
  23#include <asm/mpic.h>
  24#include <asm/swiotlb.h>
  25
  26#include <sysdev/fsl_soc.h>
  27#include <sysdev/fsl_pci.h>
  28#include <asm/udbg.h>
  29#include <asm/fsl_guts.h>
  30#include "smp.h"
  31
  32#include "mpc85xx.h"
  33
  34#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
  35
  36/*
  37 * Board-specific initialization of the DIU.  This code should probably be
  38 * executed when the DIU is opened, rather than in arch code, but the DIU
  39 * driver does not have a mechanism for this (yet).
  40 *
  41 * This is especially problematic on the P1022DS because the local bus (eLBC)
  42 * and the DIU video signals share the same pins, which means that enabling the
  43 * DIU will disable access to NOR flash.
  44 */
  45
  46/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
  47#define CLKDVDR_PXCKEN          0x80000000
  48#define CLKDVDR_PXCKINV         0x10000000
  49#define CLKDVDR_PXCKDLY         0x06000000
  50#define CLKDVDR_PXCLK_MASK      0x00FF0000
  51
  52/* Some ngPIXIS register definitions */
  53#define PX_BRDCFG1_DVIEN        0x80
  54#define PX_BRDCFG1_DFPEN        0x40
  55#define PX_BRDCFG1_BACKLIGHT    0x20
  56#define PX_BRDCFG1_DDCEN        0x10
  57
  58/*
  59 * DIU Area Descriptor
  60 *
  61 * Note that we need to byte-swap the value before it's written to the AD
  62 * register.  So even though the registers don't look like they're in the same
  63 * bit positions as they are on the MPC8610, the same value is written to the
  64 * AD register on the MPC8610 and on the P1022.
  65 */
  66#define AD_BYTE_F               0x10000000
  67#define AD_ALPHA_C_MASK         0x0E000000
  68#define AD_ALPHA_C_SHIFT        25
  69#define AD_BLUE_C_MASK          0x01800000
  70#define AD_BLUE_C_SHIFT         23
  71#define AD_GREEN_C_MASK         0x00600000
  72#define AD_GREEN_C_SHIFT        21
  73#define AD_RED_C_MASK           0x00180000
  74#define AD_RED_C_SHIFT          19
  75#define AD_PALETTE              0x00040000
  76#define AD_PIXEL_S_MASK         0x00030000
  77#define AD_PIXEL_S_SHIFT        16
  78#define AD_COMP_3_MASK          0x0000F000
  79#define AD_COMP_3_SHIFT         12
  80#define AD_COMP_2_MASK          0x00000F00
  81#define AD_COMP_2_SHIFT         8
  82#define AD_COMP_1_MASK          0x000000F0
  83#define AD_COMP_1_SHIFT         4
  84#define AD_COMP_0_MASK          0x0000000F
  85#define AD_COMP_0_SHIFT         0
  86
  87#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
  88        cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
  89        (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
  90        (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
  91        (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
  92        (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
  93
  94/**
  95 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
  96 *
  97 * The Area Descriptor is a 32-bit value that determine which bits in each
  98 * pixel are to be used for each color.
  99 */
 100static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
 101                                    unsigned int bits_per_pixel)
 102{
 103        switch (bits_per_pixel) {
 104        case 32:
 105                /* 0x88883316 */
 106                return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
 107        case 24:
 108                /* 0x88082219 */
 109                return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
 110        case 16:
 111                /* 0x65053118 */
 112                return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
 113        default:
 114                pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
 115                return 0;
 116        }
 117}
 118
 119/**
 120 * p1022ds_set_gamma_table: update the gamma table, if necessary
 121 *
 122 * On some boards, the gamma table for some ports may need to be modified.
 123 * This is not the case on the P1022DS, so we do nothing.
 124*/
 125static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
 126                                    char *gamma_table_base)
 127{
 128}
 129
 130/**
 131 * p1022ds_set_monitor_port: switch the output to a different monitor port
 132 *
 133 */
 134static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
 135{
 136        struct device_node *np;
 137        void __iomem *pixis;
 138        u8 __iomem *brdcfg1;
 139
 140        np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
 141        if (!np)
 142                /* older device trees used "fsl,p1022ds-pixis" */
 143                np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
 144        if (!np) {
 145                pr_err("p1022ds: missing ngPIXIS node\n");
 146                return;
 147        }
 148
 149        pixis = of_iomap(np, 0);
 150        if (!pixis) {
 151                pr_err("p1022ds: could not map ngPIXIS registers\n");
 152                return;
 153        }
 154        brdcfg1 = pixis + 9;    /* BRDCFG1 is at offset 9 in the ngPIXIS */
 155
 156        switch (port) {
 157        case FSL_DIU_PORT_DVI:
 158                printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
 159                /* Enable the DVI port, disable the DFP and the backlight */
 160                clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT,
 161                             PX_BRDCFG1_DVIEN);
 162                break;
 163        case FSL_DIU_PORT_LVDS:
 164                printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
 165                /* Enable the DFP port, disable the DVI and the backlight */
 166                clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT,
 167                             PX_BRDCFG1_DFPEN);
 168                break;
 169        default:
 170                pr_err("p1022ds: unsupported monitor port %i\n", port);
 171        }
 172
 173        iounmap(pixis);
 174}
 175
 176/**
 177 * p1022ds_set_pixel_clock: program the DIU's clock
 178 *
 179 * @pixclock: the wavelength, in picoseconds, of the clock
 180 */
 181void p1022ds_set_pixel_clock(unsigned int pixclock)
 182{
 183        struct device_node *guts_np = NULL;
 184        struct ccsr_guts_85xx __iomem *guts;
 185        unsigned long freq;
 186        u64 temp;
 187        u32 pxclk;
 188
 189        /* Map the global utilities registers. */
 190        guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
 191        if (!guts_np) {
 192                pr_err("p1022ds: missing global utilties device node\n");
 193                return;
 194        }
 195
 196        guts = of_iomap(guts_np, 0);
 197        of_node_put(guts_np);
 198        if (!guts) {
 199                pr_err("p1022ds: could not map global utilties device\n");
 200                return;
 201        }
 202
 203        /* Convert pixclock from a wavelength to a frequency */
 204        temp = 1000000000000ULL;
 205        do_div(temp, pixclock);
 206        freq = temp;
 207
 208        /*
 209         * 'pxclk' is the ratio of the platform clock to the pixel clock.
 210         * This number is programmed into the CLKDVDR register, and the valid
 211         * range of values is 2-255.
 212         */
 213        pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
 214        pxclk = clamp_t(u32, pxclk, 2, 255);
 215
 216        /* Disable the pixel clock, and set it to non-inverted and no delay */
 217        clrbits32(&guts->clkdvdr,
 218                  CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
 219
 220        /* Enable the clock and set the pxclk */
 221        setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
 222
 223        iounmap(guts);
 224}
 225
 226/**
 227 * p1022ds_valid_monitor_port: set the monitor port for sysfs
 228 */
 229enum fsl_diu_monitor_port
 230p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
 231{
 232        switch (port) {
 233        case FSL_DIU_PORT_DVI:
 234        case FSL_DIU_PORT_LVDS:
 235                return port;
 236        default:
 237                return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
 238        }
 239}
 240
 241#endif
 242
 243void __init p1022_ds_pic_init(void)
 244{
 245        struct mpic *mpic = mpic_alloc(NULL, 0,
 246                MPIC_WANTS_RESET |
 247                MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
 248                MPIC_SINGLE_DEST_CPU,
 249                0, 256, " OpenPIC  ");
 250        BUG_ON(mpic == NULL);
 251        mpic_init(mpic);
 252}
 253
 254/*
 255 * Setup the architecture
 256 */
 257static void __init p1022_ds_setup_arch(void)
 258{
 259#ifdef CONFIG_PCI
 260        struct device_node *np;
 261#endif
 262        dma_addr_t max = 0xffffffff;
 263
 264        if (ppc_md.progress)
 265                ppc_md.progress("p1022_ds_setup_arch()", 0);
 266
 267#ifdef CONFIG_PCI
 268        for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
 269                struct resource rsrc;
 270                struct pci_controller *hose;
 271
 272                of_address_to_resource(np, 0, &rsrc);
 273
 274                if ((rsrc.start & 0xfffff) == 0x8000)
 275                        fsl_add_bridge(np, 1);
 276                else
 277                        fsl_add_bridge(np, 0);
 278
 279                hose = pci_find_hose_for_OF_device(np);
 280                max = min(max, hose->dma_window_base_cur +
 281                          hose->dma_window_size);
 282        }
 283#endif
 284
 285#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 286        diu_ops.get_pixel_format        = p1022ds_get_pixel_format;
 287        diu_ops.set_gamma_table         = p1022ds_set_gamma_table;
 288        diu_ops.set_monitor_port        = p1022ds_set_monitor_port;
 289        diu_ops.set_pixel_clock         = p1022ds_set_pixel_clock;
 290        diu_ops.valid_monitor_port      = p1022ds_valid_monitor_port;
 291#endif
 292
 293        mpc85xx_smp_init();
 294
 295#ifdef CONFIG_SWIOTLB
 296        if (memblock_end_of_DRAM() > max) {
 297                ppc_swiotlb_enable = 1;
 298                set_pci_dma_ops(&swiotlb_dma_ops);
 299                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
 300        }
 301#endif
 302
 303        pr_info("Freescale P1022 DS reference board\n");
 304}
 305
 306static struct of_device_id __initdata p1022_ds_ids[] = {
 307        /* So that the DMA channel nodes can be probed individually: */
 308        { .compatible = "fsl,eloplus-dma", },
 309        {},
 310};
 311
 312static int __init p1022_ds_publish_devices(void)
 313{
 314        mpc85xx_common_publish_devices();
 315        return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
 316}
 317machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
 318
 319machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
 320
 321/*
 322 * Called very early, device-tree isn't unflattened
 323 */
 324static int __init p1022_ds_probe(void)
 325{
 326        unsigned long root = of_get_flat_dt_root();
 327
 328        return of_flat_dt_is_compatible(root, "fsl,p1022ds");
 329}
 330
 331define_machine(p1022_ds) {
 332        .name                   = "P1022 DS",
 333        .probe                  = p1022_ds_probe,
 334        .setup_arch             = p1022_ds_setup_arch,
 335        .init_IRQ               = p1022_ds_pic_init,
 336#ifdef CONFIG_PCI
 337        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 338#endif
 339        .get_irq                = mpic_get_irq,
 340        .restart                = fsl_rstcr_restart,
 341        .calibrate_decr         = generic_calibrate_decr,
 342        .progress               = udbg_progress,
 343};
 344