linux/arch/powerpc/platforms/85xx/mpc85xx_ads.c
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   1/*
   2 * MPC85xx setup and early boot code plus other random bits.
   3 *
   4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5 *
   6 * Copyright 2005 Freescale Semiconductor Inc.
   7 *
   8 * This program is free software; you can redistribute  it and/or modify it
   9 * under  the terms of  the GNU General  Public License as published by the
  10 * Free Software Foundation;  either version 2 of the  License, or (at your
  11 * option) any later version.
  12 */
  13
  14#include <linux/stddef.h>
  15#include <linux/kernel.h>
  16#include <linux/pci.h>
  17#include <linux/kdev_t.h>
  18#include <linux/delay.h>
  19#include <linux/seq_file.h>
  20#include <linux/of_platform.h>
  21
  22#include <asm/system.h>
  23#include <asm/time.h>
  24#include <asm/machdep.h>
  25#include <asm/pci-bridge.h>
  26#include <asm/mpic.h>
  27#include <mm/mmu_decl.h>
  28#include <asm/udbg.h>
  29
  30#include <sysdev/fsl_soc.h>
  31#include <sysdev/fsl_pci.h>
  32
  33#ifdef CONFIG_CPM2
  34#include <asm/cpm2.h>
  35#include <sysdev/cpm2_pic.h>
  36#endif
  37
  38#include "mpc85xx.h"
  39
  40#ifdef CONFIG_PCI
  41static int mpc85xx_exclude_device(struct pci_controller *hose,
  42                                   u_char bus, u_char devfn)
  43{
  44        if (bus == 0 && PCI_SLOT(devfn) == 0)
  45                return PCIBIOS_DEVICE_NOT_FOUND;
  46        else
  47                return PCIBIOS_SUCCESSFUL;
  48}
  49#endif /* CONFIG_PCI */
  50
  51static void __init mpc85xx_ads_pic_init(void)
  52{
  53        struct mpic *mpic = mpic_alloc(NULL, 0,
  54                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  55                        0, 256, " OpenPIC  ");
  56        BUG_ON(mpic == NULL);
  57        mpic_init(mpic);
  58
  59        mpc85xx_cpm2_pic_init();
  60}
  61
  62/*
  63 * Setup the architecture
  64 */
  65#ifdef CONFIG_CPM2
  66struct cpm_pin {
  67        int port, pin, flags;
  68};
  69
  70static const struct cpm_pin mpc8560_ads_pins[] = {
  71        /* SCC1 */
  72        {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  73        {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  74        {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  75
  76        /* SCC2 */
  77        {2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  78        {2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  79        {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  80        {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  81        {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  82
  83        /* FCC2 */
  84        {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  85        {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  86        {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  87        {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  88        {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  89        {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  90        {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  91        {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  92        {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  93        {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  94        {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  95        {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  96        {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  97        {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  98        {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
  99        {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
 100
 101        /* FCC3 */
 102        {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 103        {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 104        {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 105        {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 106        {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 107        {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 108        {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 109        {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 110        {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 111        {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 112        {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 113        {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 114        {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 115        {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */
 116        {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */
 117        {2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 118};
 119
 120static void __init init_ioports(void)
 121{
 122        int i;
 123
 124        for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
 125                const struct cpm_pin *pin = &mpc8560_ads_pins[i];
 126                cpm2_set_pin(pin->port, pin->pin, pin->flags);
 127        }
 128
 129        cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
 130        cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
 131        cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
 132        cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
 133        cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
 134        cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
 135        cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
 136        cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
 137}
 138#endif
 139
 140static void __init mpc85xx_ads_setup_arch(void)
 141{
 142#ifdef CONFIG_PCI
 143        struct device_node *np;
 144#endif
 145
 146        if (ppc_md.progress)
 147                ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
 148
 149#ifdef CONFIG_CPM2
 150        cpm2_reset();
 151        init_ioports();
 152#endif
 153
 154#ifdef CONFIG_PCI
 155        for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
 156                fsl_add_bridge(np, 1);
 157
 158        ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 159#endif
 160}
 161
 162static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
 163{
 164        uint pvid, svid, phid1;
 165
 166        pvid = mfspr(SPRN_PVR);
 167        svid = mfspr(SPRN_SVR);
 168
 169        seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 170        seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 171        seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 172
 173        /* Display cpu Pll setting */
 174        phid1 = mfspr(SPRN_HID1);
 175        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 176}
 177
 178machine_device_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
 179
 180/*
 181 * Called very early, device-tree isn't unflattened
 182 */
 183static int __init mpc85xx_ads_probe(void)
 184{
 185        unsigned long root = of_get_flat_dt_root();
 186
 187        return of_flat_dt_is_compatible(root, "MPC85xxADS");
 188}
 189
 190define_machine(mpc85xx_ads) {
 191        .name                   = "MPC85xx ADS",
 192        .probe                  = mpc85xx_ads_probe,
 193        .setup_arch             = mpc85xx_ads_setup_arch,
 194        .init_IRQ               = mpc85xx_ads_pic_init,
 195        .show_cpuinfo           = mpc85xx_ads_show_cpuinfo,
 196        .get_irq                = mpic_get_irq,
 197        .restart                = fsl_rstcr_restart,
 198        .calibrate_decr         = generic_calibrate_decr,
 199        .progress               = udbg_progress,
 200};
 201