linux/arch/powerpc/platforms/85xx/corenet_ds.c
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   1/*
   2 * Corenet based SoC DS Setup
   3 *
   4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5 *
   6 * Copyright 2009-2011 Freescale Semiconductor Inc.
   7 *
   8 * This program is free software; you can redistribute  it and/or modify it
   9 * under  the terms of  the GNU General  Public License as published by the
  10 * Free Software Foundation;  either version 2 of the  License, or (at your
  11 * option) any later version.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/pci.h>
  16#include <linux/kdev_t.h>
  17#include <linux/delay.h>
  18#include <linux/interrupt.h>
  19#include <linux/memblock.h>
  20
  21#include <asm/system.h>
  22#include <asm/time.h>
  23#include <asm/machdep.h>
  24#include <asm/pci-bridge.h>
  25#include <asm/ppc-pci.h>
  26#include <mm/mmu_decl.h>
  27#include <asm/prom.h>
  28#include <asm/udbg.h>
  29#include <asm/mpic.h>
  30
  31#include <linux/of_platform.h>
  32#include <sysdev/fsl_soc.h>
  33#include <sysdev/fsl_pci.h>
  34#include "smp.h"
  35
  36void __init corenet_ds_pic_init(void)
  37{
  38        struct mpic *mpic;
  39        unsigned int flags = MPIC_BIG_ENDIAN |
  40                                MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU;
  41
  42        if (ppc_md.get_irq == mpic_get_coreint_irq)
  43                flags |= MPIC_ENABLE_COREINT;
  44
  45        mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC  ");
  46        BUG_ON(mpic == NULL);
  47
  48        mpic_init(mpic);
  49}
  50
  51/*
  52 * Setup the architecture
  53 */
  54void __init corenet_ds_setup_arch(void)
  55{
  56#ifdef CONFIG_PCI
  57        struct device_node *np;
  58        struct pci_controller *hose;
  59#endif
  60        dma_addr_t max = 0xffffffff;
  61
  62        mpc85xx_smp_init();
  63
  64#ifdef CONFIG_PCI
  65        for_each_node_by_type(np, "pci") {
  66                if (of_device_is_compatible(np, "fsl,p4080-pcie") ||
  67                    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2")) {
  68                        fsl_add_bridge(np, 0);
  69                        hose = pci_find_hose_for_OF_device(np);
  70                        max = min(max, hose->dma_window_base_cur +
  71                                        hose->dma_window_size);
  72                }
  73        }
  74
  75#ifdef CONFIG_PPC64
  76        pci_devs_phb_init();
  77#endif
  78#endif
  79
  80#ifdef CONFIG_SWIOTLB
  81        if (memblock_end_of_DRAM() > max) {
  82                ppc_swiotlb_enable = 1;
  83                set_pci_dma_ops(&swiotlb_dma_ops);
  84                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
  85        }
  86#endif
  87        pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
  88}
  89
  90static const struct of_device_id of_device_ids[] __devinitconst = {
  91        {
  92                .compatible     = "simple-bus"
  93        },
  94        {
  95                .compatible     = "fsl,srio",
  96        },
  97        {
  98                .compatible     = "fsl,p4080-pcie",
  99        },
 100        {
 101                .compatible     = "fsl,qoriq-pcie-v2.2",
 102        },
 103        /* The following two are for the Freescale hypervisor */
 104        {
 105                .name           = "hypervisor",
 106        },
 107        {
 108                .name           = "handles",
 109        },
 110        {}
 111};
 112
 113int __init corenet_ds_publish_devices(void)
 114{
 115        return of_platform_bus_probe(NULL, of_device_ids, NULL);
 116}
 117