linux/arch/powerpc/platforms/52xx/media5200.c
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   1/*
   2 * Support for 'media5200-platform' compatible boards.
   3 *
   4 * Copyright (C) 2008 Secret Lab Technologies Ltd.
   5 *
   6 * This program is free software; you can redistribute  it and/or modify it
   7 * under  the terms of  the GNU General  Public License as published by the
   8 * Free Software Foundation;  either version 2 of the  License, or (at your
   9 * option) any later version.
  10 *
  11 * Description:
  12 * This code implements support for the Freescape Media5200 platform
  13 * (built around the MPC5200 SoC).
  14 *
  15 * Notable characteristic of the Media5200 is the presence of an FPGA
  16 * that has all external IRQ lines routed through it.  This file implements
  17 * a cascaded interrupt controller driver which attaches itself to the
  18 * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
  19 * is initialized.
  20 *
  21 */
  22
  23#undef DEBUG
  24
  25#include <linux/irq.h>
  26#include <linux/interrupt.h>
  27#include <linux/io.h>
  28#include <asm/time.h>
  29#include <asm/prom.h>
  30#include <asm/machdep.h>
  31#include <asm/mpc52xx.h>
  32
  33static struct of_device_id mpc5200_gpio_ids[] __initdata = {
  34        { .compatible = "fsl,mpc5200-gpio", },
  35        { .compatible = "mpc5200-gpio", },
  36        {}
  37};
  38
  39/* FPGA register set */
  40#define MEDIA5200_IRQ_ENABLE (0x40c)
  41#define MEDIA5200_IRQ_STATUS (0x410)
  42#define MEDIA5200_NUM_IRQS   (6)
  43#define MEDIA5200_IRQ_SHIFT  (32 - MEDIA5200_NUM_IRQS)
  44
  45struct media5200_irq {
  46        void __iomem *regs;
  47        spinlock_t lock;
  48        struct irq_host *irqhost;
  49};
  50struct media5200_irq media5200_irq;
  51
  52static void media5200_irq_unmask(struct irq_data *d)
  53{
  54        unsigned long flags;
  55        u32 val;
  56
  57        spin_lock_irqsave(&media5200_irq.lock, flags);
  58        val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  59        val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
  60        out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
  61        spin_unlock_irqrestore(&media5200_irq.lock, flags);
  62}
  63
  64static void media5200_irq_mask(struct irq_data *d)
  65{
  66        unsigned long flags;
  67        u32 val;
  68
  69        spin_lock_irqsave(&media5200_irq.lock, flags);
  70        val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  71        val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
  72        out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
  73        spin_unlock_irqrestore(&media5200_irq.lock, flags);
  74}
  75
  76static struct irq_chip media5200_irq_chip = {
  77        .name = "Media5200 FPGA",
  78        .irq_unmask = media5200_irq_unmask,
  79        .irq_mask = media5200_irq_mask,
  80        .irq_mask_ack = media5200_irq_mask,
  81};
  82
  83void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
  84{
  85        struct irq_chip *chip = irq_desc_get_chip(desc);
  86        int sub_virq, val;
  87        u32 status, enable;
  88
  89        /* Mask off the cascaded IRQ */
  90        raw_spin_lock(&desc->lock);
  91        chip->irq_mask(&desc->irq_data);
  92        raw_spin_unlock(&desc->lock);
  93
  94        /* Ask the FPGA for IRQ status.  If 'val' is 0, then no irqs
  95         * are pending.  'ffs()' is 1 based */
  96        status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  97        enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
  98        val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
  99        if (val) {
 100                sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
 101                /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
 102                 *          __func__, virq, status, enable, val - 1, sub_virq);
 103                 */
 104                generic_handle_irq(sub_virq);
 105        }
 106
 107        /* Processing done; can reenable the cascade now */
 108        raw_spin_lock(&desc->lock);
 109        chip->irq_ack(&desc->irq_data);
 110        if (!irqd_irq_disabled(&desc->irq_data))
 111                chip->irq_unmask(&desc->irq_data);
 112        raw_spin_unlock(&desc->lock);
 113}
 114
 115static int media5200_irq_map(struct irq_host *h, unsigned int virq,
 116                             irq_hw_number_t hw)
 117{
 118        pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
 119        irq_set_chip_data(virq, &media5200_irq);
 120        irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
 121        irq_set_status_flags(virq, IRQ_LEVEL);
 122        return 0;
 123}
 124
 125static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
 126                                 const u32 *intspec, unsigned int intsize,
 127                                 irq_hw_number_t *out_hwirq,
 128                                 unsigned int *out_flags)
 129{
 130        if (intsize != 2)
 131                return -1;
 132
 133        pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
 134        *out_hwirq = intspec[1];
 135        *out_flags = IRQ_TYPE_NONE;
 136        return 0;
 137}
 138
 139static struct irq_host_ops media5200_irq_ops = {
 140        .map = media5200_irq_map,
 141        .xlate = media5200_irq_xlate,
 142};
 143
 144/*
 145 * Setup Media5200 IRQ mapping
 146 */
 147static void __init media5200_init_irq(void)
 148{
 149        struct device_node *fpga_np;
 150        int cascade_virq;
 151
 152        /* First setup the regular MPC5200 interrupt controller */
 153        mpc52xx_init_irq();
 154
 155        /* Now find the FPGA IRQ */
 156        fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
 157        if (!fpga_np)
 158                goto out;
 159        pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
 160
 161        media5200_irq.regs = of_iomap(fpga_np, 0);
 162        if (!media5200_irq.regs)
 163                goto out;
 164        pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
 165
 166        cascade_virq = irq_of_parse_and_map(fpga_np, 0);
 167        if (!cascade_virq)
 168                goto out;
 169        pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
 170
 171        /* Disable all FPGA IRQs */
 172        out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
 173
 174        spin_lock_init(&media5200_irq.lock);
 175
 176        media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR,
 177                                               MEDIA5200_NUM_IRQS,
 178                                               &media5200_irq_ops, -1);
 179        if (!media5200_irq.irqhost)
 180                goto out;
 181        pr_debug("%s: allocated irqhost\n", __func__);
 182
 183        media5200_irq.irqhost->host_data = &media5200_irq;
 184
 185        irq_set_handler_data(cascade_virq, &media5200_irq);
 186        irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
 187
 188        return;
 189
 190 out:
 191        pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
 192}
 193
 194/*
 195 * Setup the architecture
 196 */
 197static void __init media5200_setup_arch(void)
 198{
 199
 200        struct device_node *np;
 201        struct mpc52xx_gpio __iomem *gpio;
 202        u32 port_config;
 203
 204        if (ppc_md.progress)
 205                ppc_md.progress("media5200_setup_arch()", 0);
 206
 207        /* Map important registers from the internal memory map */
 208        mpc52xx_map_common_devices();
 209
 210        /* Some mpc5200 & mpc5200b related configuration */
 211        mpc5200_setup_xlb_arbiter();
 212
 213        mpc52xx_setup_pci();
 214
 215        np = of_find_matching_node(NULL, mpc5200_gpio_ids);
 216        gpio = of_iomap(np, 0);
 217        of_node_put(np);
 218        if (!gpio) {
 219                printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
 220                       __func__);
 221                return;
 222        }
 223
 224        /* Set port config */
 225        port_config = in_be32(&gpio->port_config);
 226
 227        port_config &= ~0x03000000;     /* ATA CS is on csb_4/5         */
 228        port_config |=  0x01000000;
 229
 230        out_be32(&gpio->port_config, port_config);
 231
 232        /* Unmap zone */
 233        iounmap(gpio);
 234
 235}
 236
 237/* list of the supported boards */
 238static const char *board[] __initdata = {
 239        "fsl,media5200",
 240        NULL
 241};
 242
 243/*
 244 * Called very early, MMU is off, device-tree isn't unflattened
 245 */
 246static int __init media5200_probe(void)
 247{
 248        return of_flat_dt_match(of_get_flat_dt_root(), board);
 249}
 250
 251define_machine(media5200_platform) {
 252        .name           = "media5200-platform",
 253        .probe          = media5200_probe,
 254        .setup_arch     = media5200_setup_arch,
 255        .init           = mpc52xx_declare_of_platform_devices,
 256        .init_IRQ       = media5200_init_irq,
 257        .get_irq        = mpc52xx_get_irq,
 258        .restart        = mpc52xx_restart,
 259        .calibrate_decr = generic_calibrate_decr,
 260};
 261