linux/arch/powerpc/mm/pgtable.c
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   1/*
   2 * This file contains common routines for dealing with free of page tables
   3 * Along with common page table handling code
   4 *
   5 *  Derived from arch/powerpc/mm/tlb_64.c:
   6 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   7 *
   8 *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
   9 *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  10 *    Copyright (C) 1996 Paul Mackerras
  11 *
  12 *  Derived from "arch/i386/mm/init.c"
  13 *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  14 *
  15 *  Dave Engebretsen <engebret@us.ibm.com>
  16 *      Rework for PPC64 port.
  17 *
  18 *  This program is free software; you can redistribute it and/or
  19 *  modify it under the terms of the GNU General Public License
  20 *  as published by the Free Software Foundation; either version
  21 *  2 of the License, or (at your option) any later version.
  22 */
  23
  24#include <linux/kernel.h>
  25#include <linux/gfp.h>
  26#include <linux/mm.h>
  27#include <linux/init.h>
  28#include <linux/percpu.h>
  29#include <linux/hardirq.h>
  30#include <linux/hugetlb.h>
  31#include <asm/pgalloc.h>
  32#include <asm/tlbflush.h>
  33#include <asm/tlb.h>
  34
  35#include "mmu_decl.h"
  36
  37static inline int is_exec_fault(void)
  38{
  39        return current->thread.regs && TRAP(current->thread.regs) == 0x400;
  40}
  41
  42/* We only try to do i/d cache coherency on stuff that looks like
  43 * reasonably "normal" PTEs. We currently require a PTE to be present
  44 * and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE. We also only do that
  45 * on userspace PTEs
  46 */
  47static inline int pte_looks_normal(pte_t pte)
  48{
  49        return (pte_val(pte) &
  50            (_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE | _PAGE_USER)) ==
  51            (_PAGE_PRESENT | _PAGE_USER);
  52}
  53
  54struct page * maybe_pte_to_page(pte_t pte)
  55{
  56        unsigned long pfn = pte_pfn(pte);
  57        struct page *page;
  58
  59        if (unlikely(!pfn_valid(pfn)))
  60                return NULL;
  61        page = pfn_to_page(pfn);
  62        if (PageReserved(page))
  63                return NULL;
  64        return page;
  65}
  66
  67#if defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0
  68
  69/* Server-style MMU handles coherency when hashing if HW exec permission
  70 * is supposed per page (currently 64-bit only). If not, then, we always
  71 * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
  72 * support falls into the same category.
  73 */
  74
  75static pte_t set_pte_filter(pte_t pte, unsigned long addr)
  76{
  77        pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
  78        if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
  79                                       cpu_has_feature(CPU_FTR_NOEXECUTE))) {
  80                struct page *pg = maybe_pte_to_page(pte);
  81                if (!pg)
  82                        return pte;
  83                if (!test_bit(PG_arch_1, &pg->flags)) {
  84#ifdef CONFIG_8xx
  85                        /* On 8xx, cache control instructions (particularly
  86                         * "dcbst" from flush_dcache_icache) fault as write
  87                         * operation if there is an unpopulated TLB entry
  88                         * for the address in question. To workaround that,
  89                         * we invalidate the TLB here, thus avoiding dcbst
  90                         * misbehaviour.
  91                         */
  92                        /* 8xx doesn't care about PID, size or ind args */
  93                        _tlbil_va(addr, 0, 0, 0);
  94#endif /* CONFIG_8xx */
  95                        flush_dcache_icache_page(pg);
  96                        set_bit(PG_arch_1, &pg->flags);
  97                }
  98        }
  99        return pte;
 100}
 101
 102static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
 103                                     int dirty)
 104{
 105        return pte;
 106}
 107
 108#else /* defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0 */
 109
 110/* Embedded type MMU with HW exec support. This is a bit more complicated
 111 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
 112 * instead we "filter out" the exec permission for non clean pages.
 113 */
 114static pte_t set_pte_filter(pte_t pte, unsigned long addr)
 115{
 116        struct page *pg;
 117
 118        /* No exec permission in the first place, move on */
 119        if (!(pte_val(pte) & _PAGE_EXEC) || !pte_looks_normal(pte))
 120                return pte;
 121
 122        /* If you set _PAGE_EXEC on weird pages you're on your own */
 123        pg = maybe_pte_to_page(pte);
 124        if (unlikely(!pg))
 125                return pte;
 126
 127        /* If the page clean, we move on */
 128        if (test_bit(PG_arch_1, &pg->flags))
 129                return pte;
 130
 131        /* If it's an exec fault, we flush the cache and make it clean */
 132        if (is_exec_fault()) {
 133                flush_dcache_icache_page(pg);
 134                set_bit(PG_arch_1, &pg->flags);
 135                return pte;
 136        }
 137
 138        /* Else, we filter out _PAGE_EXEC */
 139        return __pte(pte_val(pte) & ~_PAGE_EXEC);
 140}
 141
 142static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
 143                                     int dirty)
 144{
 145        struct page *pg;
 146
 147        /* So here, we only care about exec faults, as we use them
 148         * to recover lost _PAGE_EXEC and perform I$/D$ coherency
 149         * if necessary. Also if _PAGE_EXEC is already set, same deal,
 150         * we just bail out
 151         */
 152        if (dirty || (pte_val(pte) & _PAGE_EXEC) || !is_exec_fault())
 153                return pte;
 154
 155#ifdef CONFIG_DEBUG_VM
 156        /* So this is an exec fault, _PAGE_EXEC is not set. If it was
 157         * an error we would have bailed out earlier in do_page_fault()
 158         * but let's make sure of it
 159         */
 160        if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
 161                return pte;
 162#endif /* CONFIG_DEBUG_VM */
 163
 164        /* If you set _PAGE_EXEC on weird pages you're on your own */
 165        pg = maybe_pte_to_page(pte);
 166        if (unlikely(!pg))
 167                goto bail;
 168
 169        /* If the page is already clean, we move on */
 170        if (test_bit(PG_arch_1, &pg->flags))
 171                goto bail;
 172
 173        /* Clean the page and set PG_arch_1 */
 174        flush_dcache_icache_page(pg);
 175        set_bit(PG_arch_1, &pg->flags);
 176
 177 bail:
 178        return __pte(pte_val(pte) | _PAGE_EXEC);
 179}
 180
 181#endif /* !(defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0) */
 182
 183/*
 184 * set_pte stores a linux PTE into the linux page table.
 185 */
 186void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
 187                pte_t pte)
 188{
 189#ifdef CONFIG_DEBUG_VM
 190        WARN_ON(pte_present(*ptep));
 191#endif
 192        /* Note: mm->context.id might not yet have been assigned as
 193         * this context might not have been activated yet when this
 194         * is called.
 195         */
 196        pte = set_pte_filter(pte, addr);
 197
 198        /* Perform the setting of the PTE */
 199        __set_pte_at(mm, addr, ptep, pte, 0);
 200}
 201
 202/*
 203 * This is called when relaxing access to a PTE. It's also called in the page
 204 * fault path when we don't hit any of the major fault cases, ie, a minor
 205 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
 206 * handled those two for us, we additionally deal with missing execute
 207 * permission here on some processors
 208 */
 209int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
 210                          pte_t *ptep, pte_t entry, int dirty)
 211{
 212        int changed;
 213        entry = set_access_flags_filter(entry, vma, dirty);
 214        changed = !pte_same(*(ptep), entry);
 215        if (changed) {
 216                if (!is_vm_hugetlb_page(vma))
 217                        assert_pte_locked(vma->vm_mm, address);
 218                __ptep_set_access_flags(ptep, entry);
 219                flush_tlb_page_nohash(vma, address);
 220        }
 221        return changed;
 222}
 223
 224#ifdef CONFIG_DEBUG_VM
 225void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
 226{
 227        pgd_t *pgd;
 228        pud_t *pud;
 229        pmd_t *pmd;
 230
 231        if (mm == &init_mm)
 232                return;
 233        pgd = mm->pgd + pgd_index(addr);
 234        BUG_ON(pgd_none(*pgd));
 235        pud = pud_offset(pgd, addr);
 236        BUG_ON(pud_none(*pud));
 237        pmd = pmd_offset(pud, addr);
 238        BUG_ON(!pmd_present(*pmd));
 239        assert_spin_locked(pte_lockptr(mm, pmd));
 240}
 241#endif /* CONFIG_DEBUG_VM */
 242
 243