linux/arch/powerpc/mm/44x_mmu.c
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   1/*
   2 * Modifications by Matt Porter (mporter@mvista.com) to support
   3 * PPC44x Book E processors.
   4 *
   5 * This file contains the routines for initializing the MMU
   6 * on the 4xx series of chips.
   7 *  -- paulus
   8 *
   9 *  Derived from arch/ppc/mm/init.c:
  10 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  11 *
  12 *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  13 *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  14 *    Copyright (C) 1996 Paul Mackerras
  15 *
  16 *  Derived from "arch/i386/mm/init.c"
  17 *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  18 *
  19 *  This program is free software; you can redistribute it and/or
  20 *  modify it under the terms of the GNU General Public License
  21 *  as published by the Free Software Foundation; either version
  22 *  2 of the License, or (at your option) any later version.
  23 *
  24 */
  25
  26#include <linux/init.h>
  27#include <linux/memblock.h>
  28
  29#include <asm/mmu.h>
  30#include <asm/system.h>
  31#include <asm/page.h>
  32#include <asm/cacheflush.h>
  33
  34#include "mmu_decl.h"
  35
  36/* Used by the 44x TLB replacement exception handler.
  37 * Just needed it declared someplace.
  38 */
  39unsigned int tlb_44x_index; /* = 0 */
  40unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
  41int icache_44x_need_flush;
  42
  43unsigned long tlb_47x_boltmap[1024/8];
  44
  45static void __cpuinit ppc44x_update_tlb_hwater(void)
  46{
  47        extern unsigned int tlb_44x_patch_hwater_D[];
  48        extern unsigned int tlb_44x_patch_hwater_I[];
  49
  50        /* The TLB miss handlers hard codes the watermark in a cmpli
  51         * instruction to improve performances rather than loading it
  52         * from the global variable. Thus, we patch the instructions
  53         * in the 2 TLB miss handlers when updating the value
  54         */
  55        tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |
  56                tlb_44x_hwater;
  57        flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],
  58                           (unsigned long)&tlb_44x_patch_hwater_D[1]);
  59        tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |
  60                tlb_44x_hwater;
  61        flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],
  62                           (unsigned long)&tlb_44x_patch_hwater_I[1]);
  63}
  64
  65/*
  66 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
  67 */
  68static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
  69{
  70        unsigned int entry = tlb_44x_hwater--;
  71
  72        ppc44x_update_tlb_hwater();
  73
  74        mtspr(SPRN_MMUCR, 0);
  75
  76        __asm__ __volatile__(
  77                "tlbwe  %2,%3,%4\n"
  78                "tlbwe  %1,%3,%5\n"
  79                "tlbwe  %0,%3,%6\n"
  80        :
  81        : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
  82          "r" (phys),
  83          "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
  84          "r" (entry),
  85          "i" (PPC44x_TLB_PAGEID),
  86          "i" (PPC44x_TLB_XLAT),
  87          "i" (PPC44x_TLB_ATTRIB));
  88}
  89
  90static int __init ppc47x_find_free_bolted(void)
  91{
  92        unsigned int mmube0 = mfspr(SPRN_MMUBE0);
  93        unsigned int mmube1 = mfspr(SPRN_MMUBE1);
  94
  95        if (!(mmube0 & MMUBE0_VBE0))
  96                return 0;
  97        if (!(mmube0 & MMUBE0_VBE1))
  98                return 1;
  99        if (!(mmube0 & MMUBE0_VBE2))
 100                return 2;
 101        if (!(mmube1 & MMUBE1_VBE3))
 102                return 3;
 103        if (!(mmube1 & MMUBE1_VBE4))
 104                return 4;
 105        if (!(mmube1 & MMUBE1_VBE5))
 106                return 5;
 107        return -1;
 108}
 109
 110static void __init ppc47x_update_boltmap(void)
 111{
 112        unsigned int mmube0 = mfspr(SPRN_MMUBE0);
 113        unsigned int mmube1 = mfspr(SPRN_MMUBE1);
 114
 115        if (mmube0 & MMUBE0_VBE0)
 116                __set_bit((mmube0 >> MMUBE0_IBE0_SHIFT) & 0xff,
 117                          tlb_47x_boltmap);
 118        if (mmube0 & MMUBE0_VBE1)
 119                __set_bit((mmube0 >> MMUBE0_IBE1_SHIFT) & 0xff,
 120                          tlb_47x_boltmap);
 121        if (mmube0 & MMUBE0_VBE2)
 122                __set_bit((mmube0 >> MMUBE0_IBE2_SHIFT) & 0xff,
 123                          tlb_47x_boltmap);
 124        if (mmube1 & MMUBE1_VBE3)
 125                __set_bit((mmube1 >> MMUBE1_IBE3_SHIFT) & 0xff,
 126                          tlb_47x_boltmap);
 127        if (mmube1 & MMUBE1_VBE4)
 128                __set_bit((mmube1 >> MMUBE1_IBE4_SHIFT) & 0xff,
 129                          tlb_47x_boltmap);
 130        if (mmube1 & MMUBE1_VBE5)
 131                __set_bit((mmube1 >> MMUBE1_IBE5_SHIFT) & 0xff,
 132                          tlb_47x_boltmap);
 133}
 134
 135/*
 136 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
 137 */
 138static void __cpuinit ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
 139{
 140        unsigned int rA;
 141        int bolted;
 142
 143        /* Base rA is HW way select, way 0, bolted bit set */
 144        rA = 0x88000000;
 145
 146        /* Look for a bolted entry slot */
 147        bolted = ppc47x_find_free_bolted();
 148        BUG_ON(bolted < 0);
 149
 150        /* Insert bolted slot number */
 151        rA |= bolted << 24;
 152
 153        pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",
 154                 virt, phys, bolted);
 155
 156        mtspr(SPRN_MMUCR, 0);
 157
 158        __asm__ __volatile__(
 159                "tlbwe  %2,%3,0\n"
 160                "tlbwe  %1,%3,1\n"
 161                "tlbwe  %0,%3,2\n"
 162                :
 163                : "r" (PPC47x_TLB2_SW | PPC47x_TLB2_SR |
 164                       PPC47x_TLB2_SX
 165#ifdef CONFIG_SMP
 166                       | PPC47x_TLB2_M
 167#endif
 168                       ),
 169                  "r" (phys),
 170                  "r" (virt | PPC47x_TLB0_VALID | PPC47x_TLB0_256M),
 171                  "r" (rA));
 172}
 173
 174void __init MMU_init_hw(void)
 175{
 176        /* This is not useful on 47x but won't hurt either */
 177        ppc44x_update_tlb_hwater();
 178
 179        flush_instruction_cache();
 180}
 181
 182unsigned long __init mmu_mapin_ram(unsigned long top)
 183{
 184        unsigned long addr;
 185        unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
 186
 187        /* Pin in enough TLBs to cover any lowmem not covered by the
 188         * initial 256M mapping established in head_44x.S */
 189        for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
 190             addr += PPC_PIN_SIZE) {
 191                if (mmu_has_feature(MMU_FTR_TYPE_47x))
 192                        ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
 193                else
 194                        ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
 195        }
 196        if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
 197                ppc47x_update_boltmap();
 198
 199#ifdef DEBUG
 200                {
 201                        int i;
 202
 203                        printk(KERN_DEBUG "bolted entries: ");
 204                        for (i = 0; i < 255; i++) {
 205                                if (test_bit(i, tlb_47x_boltmap))
 206                                        printk("%d ", i);
 207                        }
 208                        printk("\n");
 209                }
 210#endif /* DEBUG */
 211        }
 212        return total_lowmem;
 213}
 214
 215void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 216                                phys_addr_t first_memblock_size)
 217{
 218        u64 size;
 219
 220#ifndef CONFIG_NONSTATIC_KERNEL
 221        /* We don't currently support the first MEMBLOCK not mapping 0
 222         * physical on those processors
 223         */
 224        BUG_ON(first_memblock_base != 0);
 225#endif
 226
 227        /* 44x has a 256M TLB entry pinned at boot */
 228        size = (min_t(u64, first_memblock_size, PPC_PIN_SIZE));
 229        memblock_set_current_limit(first_memblock_base + size);
 230}
 231
 232#ifdef CONFIG_SMP
 233void __cpuinit mmu_init_secondary(int cpu)
 234{
 235        unsigned long addr;
 236        unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
 237
 238        /* Pin in enough TLBs to cover any lowmem not covered by the
 239         * initial 256M mapping established in head_44x.S
 240         *
 241         * WARNING: This is called with only the first 256M of the
 242         * linear mapping in the TLB and we can't take faults yet
 243         * so beware of what this code uses. It runs off a temporary
 244         * stack. current (r2) isn't initialized, smp_processor_id()
 245         * will not work, current thread info isn't accessible, ...
 246         */
 247        for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
 248             addr += PPC_PIN_SIZE) {
 249                if (mmu_has_feature(MMU_FTR_TYPE_47x))
 250                        ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
 251                else
 252                        ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
 253        }
 254}
 255#endif /* CONFIG_SMP */
 256