linux/drivers/usb/gadget/fsl_udc_core.c
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   1/*
   2 * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
   3 * All rights reserved.
   4 *
   5 * Author: Li Yang <leoli@freescale.com>
   6 *         Jiang Bo <tanya.jiang@freescale.com>
   7 *
   8 * Description:
   9 * Freescale high-speed USB SOC DR module device controller driver.
  10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  11 * The driver is previously named as mpc_udc.  Based on bare board
  12 * code from Dave Liu and Shlomi Gridish.
  13 *
  14 * This program is free software; you can redistribute  it and/or modify it
  15 * under  the terms of  the GNU General  Public License as published by the
  16 * Free Software Foundation;  either version 2 of the  License, or (at your
  17 * option) any later version.
  18 */
  19
  20#undef VERBOSE
  21
  22#include <linux/module.h>
  23#include <linux/kernel.h>
  24#include <linux/ioport.h>
  25#include <linux/types.h>
  26#include <linux/errno.h>
  27#include <linux/slab.h>
  28#include <linux/init.h>
  29#include <linux/list.h>
  30#include <linux/interrupt.h>
  31#include <linux/proc_fs.h>
  32#include <linux/mm.h>
  33#include <linux/moduleparam.h>
  34#include <linux/device.h>
  35#include <linux/usb/ch9.h>
  36#include <linux/usb/gadget.h>
  37#include <linux/usb/otg.h>
  38#include <linux/dma-mapping.h>
  39#include <linux/platform_device.h>
  40#include <linux/fsl_devices.h>
  41#include <linux/dmapool.h>
  42#include <linux/delay.h>
  43
  44#include <asm/byteorder.h>
  45#include <asm/io.h>
  46#include <asm/system.h>
  47#include <asm/unaligned.h>
  48#include <asm/dma.h>
  49
  50#include "fsl_usb2_udc.h"
  51
  52#define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  53#define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  54#define DRIVER_VERSION  "Apr 20, 2007"
  55
  56#define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  57
  58static const char driver_name[] = "fsl-usb2-udc";
  59static const char driver_desc[] = DRIVER_DESC;
  60
  61static struct usb_dr_device *dr_regs;
  62#ifndef CONFIG_ARCH_MXC
  63static struct usb_sys_interface *usb_sys_regs;
  64#endif
  65
  66/* it is initialized in probe()  */
  67static struct fsl_udc *udc_controller = NULL;
  68
  69static const struct usb_endpoint_descriptor
  70fsl_ep0_desc = {
  71        .bLength =              USB_DT_ENDPOINT_SIZE,
  72        .bDescriptorType =      USB_DT_ENDPOINT,
  73        .bEndpointAddress =     0,
  74        .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  75        .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  76};
  77
  78static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  79
  80#ifdef CONFIG_PPC32
  81/*
  82 * On some SoCs, the USB controller registers can be big or little endian,
  83 * depending on the version of the chip. In order to be able to run the
  84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  87 * call through those pointers. Platform code for SoCs that have BE USB
  88 * registers should set pdata->big_endian_mmio flag.
  89 *
  90 * This also applies to controller-to-cpu accessors for the USB descriptors,
  91 * since their endianness is also SoC dependant. Platform code for SoCs that
  92 * have BE USB descriptors should set pdata->big_endian_desc flag.
  93 */
  94static u32 _fsl_readl_be(const unsigned __iomem *p)
  95{
  96        return in_be32(p);
  97}
  98
  99static u32 _fsl_readl_le(const unsigned __iomem *p)
 100{
 101        return in_le32(p);
 102}
 103
 104static void _fsl_writel_be(u32 v, unsigned __iomem *p)
 105{
 106        out_be32(p, v);
 107}
 108
 109static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 110{
 111        out_le32(p, v);
 112}
 113
 114static u32 (*_fsl_readl)(const unsigned __iomem *p);
 115static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 116
 117#define fsl_readl(p)            (*_fsl_readl)((p))
 118#define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 119
 120static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 121{
 122        if (pdata->big_endian_mmio) {
 123                _fsl_readl = _fsl_readl_be;
 124                _fsl_writel = _fsl_writel_be;
 125        } else {
 126                _fsl_readl = _fsl_readl_le;
 127                _fsl_writel = _fsl_writel_le;
 128        }
 129}
 130
 131static inline u32 cpu_to_hc32(const u32 x)
 132{
 133        return udc_controller->pdata->big_endian_desc
 134                ? (__force u32)cpu_to_be32(x)
 135                : (__force u32)cpu_to_le32(x);
 136}
 137
 138static inline u32 hc32_to_cpu(const u32 x)
 139{
 140        return udc_controller->pdata->big_endian_desc
 141                ? be32_to_cpu((__force __be32)x)
 142                : le32_to_cpu((__force __le32)x);
 143}
 144#else /* !CONFIG_PPC32 */
 145static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 146
 147#define fsl_readl(addr)         readl(addr)
 148#define fsl_writel(val32, addr) writel(val32, addr)
 149#define cpu_to_hc32(x)          cpu_to_le32(x)
 150#define hc32_to_cpu(x)          le32_to_cpu(x)
 151#endif /* CONFIG_PPC32 */
 152
 153/********************************************************************
 154 *      Internal Used Function
 155********************************************************************/
 156/*-----------------------------------------------------------------
 157 * done() - retire a request; caller blocked irqs
 158 * @status : request status to be set, only works when
 159 *      request is still in progress.
 160 *--------------------------------------------------------------*/
 161static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 162{
 163        struct fsl_udc *udc = NULL;
 164        unsigned char stopped = ep->stopped;
 165        struct ep_td_struct *curr_td, *next_td;
 166        int j;
 167
 168        udc = (struct fsl_udc *)ep->udc;
 169        /* Removed the req from fsl_ep->queue */
 170        list_del_init(&req->queue);
 171
 172        /* req.status should be set as -EINPROGRESS in ep_queue() */
 173        if (req->req.status == -EINPROGRESS)
 174                req->req.status = status;
 175        else
 176                status = req->req.status;
 177
 178        /* Free dtd for the request */
 179        next_td = req->head;
 180        for (j = 0; j < req->dtd_count; j++) {
 181                curr_td = next_td;
 182                if (j != req->dtd_count - 1) {
 183                        next_td = curr_td->next_td_virt;
 184                }
 185                dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 186        }
 187
 188        if (req->mapped) {
 189                dma_unmap_single(ep->udc->gadget.dev.parent,
 190                        req->req.dma, req->req.length,
 191                        ep_is_in(ep)
 192                                ? DMA_TO_DEVICE
 193                                : DMA_FROM_DEVICE);
 194                req->req.dma = DMA_ADDR_INVALID;
 195                req->mapped = 0;
 196        } else
 197                dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 198                        req->req.dma, req->req.length,
 199                        ep_is_in(ep)
 200                                ? DMA_TO_DEVICE
 201                                : DMA_FROM_DEVICE);
 202
 203        if (status && (status != -ESHUTDOWN))
 204                VDBG("complete %s req %p stat %d len %u/%u",
 205                        ep->ep.name, &req->req, status,
 206                        req->req.actual, req->req.length);
 207
 208        ep->stopped = 1;
 209
 210        spin_unlock(&ep->udc->lock);
 211        /* complete() is from gadget layer,
 212         * eg fsg->bulk_in_complete() */
 213        if (req->req.complete)
 214                req->req.complete(&ep->ep, &req->req);
 215
 216        spin_lock(&ep->udc->lock);
 217        ep->stopped = stopped;
 218}
 219
 220/*-----------------------------------------------------------------
 221 * nuke(): delete all requests related to this ep
 222 * called with spinlock held
 223 *--------------------------------------------------------------*/
 224static void nuke(struct fsl_ep *ep, int status)
 225{
 226        ep->stopped = 1;
 227
 228        /* Flush fifo */
 229        fsl_ep_fifo_flush(&ep->ep);
 230
 231        /* Whether this eq has request linked */
 232        while (!list_empty(&ep->queue)) {
 233                struct fsl_req *req = NULL;
 234
 235                req = list_entry(ep->queue.next, struct fsl_req, queue);
 236                done(ep, req, status);
 237        }
 238}
 239
 240/*------------------------------------------------------------------
 241        Internal Hardware related function
 242 ------------------------------------------------------------------*/
 243
 244static int dr_controller_setup(struct fsl_udc *udc)
 245{
 246        unsigned int tmp, portctrl, ep_num;
 247        unsigned int max_no_of_ep;
 248#ifndef CONFIG_ARCH_MXC
 249        unsigned int ctrl;
 250#endif
 251        unsigned long timeout;
 252#define FSL_UDC_RESET_TIMEOUT 1000
 253
 254        /* Config PHY interface */
 255        portctrl = fsl_readl(&dr_regs->portsc1);
 256        portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 257        switch (udc->phy_mode) {
 258        case FSL_USB2_PHY_ULPI:
 259                portctrl |= PORTSCX_PTS_ULPI;
 260                break;
 261        case FSL_USB2_PHY_UTMI_WIDE:
 262                portctrl |= PORTSCX_PTW_16BIT;
 263                /* fall through */
 264        case FSL_USB2_PHY_UTMI:
 265                portctrl |= PORTSCX_PTS_UTMI;
 266                break;
 267        case FSL_USB2_PHY_SERIAL:
 268                portctrl |= PORTSCX_PTS_FSLS;
 269                break;
 270        default:
 271                return -EINVAL;
 272        }
 273        fsl_writel(portctrl, &dr_regs->portsc1);
 274
 275        /* Stop and reset the usb controller */
 276        tmp = fsl_readl(&dr_regs->usbcmd);
 277        tmp &= ~USB_CMD_RUN_STOP;
 278        fsl_writel(tmp, &dr_regs->usbcmd);
 279
 280        tmp = fsl_readl(&dr_regs->usbcmd);
 281        tmp |= USB_CMD_CTRL_RESET;
 282        fsl_writel(tmp, &dr_regs->usbcmd);
 283
 284        /* Wait for reset to complete */
 285        timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 286        while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 287                if (time_after(jiffies, timeout)) {
 288                        ERR("udc reset timeout!\n");
 289                        return -ETIMEDOUT;
 290                }
 291                cpu_relax();
 292        }
 293
 294        /* Set the controller as device mode */
 295        tmp = fsl_readl(&dr_regs->usbmode);
 296        tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 297        tmp |= USB_MODE_CTRL_MODE_DEVICE;
 298        /* Disable Setup Lockout */
 299        tmp |= USB_MODE_SETUP_LOCK_OFF;
 300        if (udc->pdata->es)
 301                tmp |= USB_MODE_ES;
 302        fsl_writel(tmp, &dr_regs->usbmode);
 303
 304        /* Clear the setup status */
 305        fsl_writel(0, &dr_regs->usbsts);
 306
 307        tmp = udc->ep_qh_dma;
 308        tmp &= USB_EP_LIST_ADDRESS_MASK;
 309        fsl_writel(tmp, &dr_regs->endpointlistaddr);
 310
 311        VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 312                udc->ep_qh, (int)tmp,
 313                fsl_readl(&dr_regs->endpointlistaddr));
 314
 315        max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 316        for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 317                tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 318                tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 319                tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 320                | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 321                fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 322        }
 323        /* Config control enable i/o output, cpu endian register */
 324#ifndef CONFIG_ARCH_MXC
 325        if (udc->pdata->have_sysif_regs) {
 326                ctrl = __raw_readl(&usb_sys_regs->control);
 327                ctrl |= USB_CTRL_IOENB;
 328                __raw_writel(ctrl, &usb_sys_regs->control);
 329        }
 330#endif
 331
 332#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 333        /* Turn on cache snooping hardware, since some PowerPC platforms
 334         * wholly rely on hardware to deal with cache coherent. */
 335
 336        if (udc->pdata->have_sysif_regs) {
 337                /* Setup Snooping for all the 4GB space */
 338                tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 339                __raw_writel(tmp, &usb_sys_regs->snoop1);
 340                tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 341                __raw_writel(tmp, &usb_sys_regs->snoop2);
 342        }
 343#endif
 344
 345        return 0;
 346}
 347
 348/* Enable DR irq and set controller to run state */
 349static void dr_controller_run(struct fsl_udc *udc)
 350{
 351        u32 temp;
 352
 353        /* Enable DR irq reg */
 354        temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 355                | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 356                | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 357
 358        fsl_writel(temp, &dr_regs->usbintr);
 359
 360        /* Clear stopped bit */
 361        udc->stopped = 0;
 362
 363        /* Set the controller as device mode */
 364        temp = fsl_readl(&dr_regs->usbmode);
 365        temp |= USB_MODE_CTRL_MODE_DEVICE;
 366        fsl_writel(temp, &dr_regs->usbmode);
 367
 368        /* Set controller to Run */
 369        temp = fsl_readl(&dr_regs->usbcmd);
 370        temp |= USB_CMD_RUN_STOP;
 371        fsl_writel(temp, &dr_regs->usbcmd);
 372}
 373
 374static void dr_controller_stop(struct fsl_udc *udc)
 375{
 376        unsigned int tmp;
 377
 378        pr_debug("%s\n", __func__);
 379
 380        /* if we're in OTG mode, and the Host is currently using the port,
 381         * stop now and don't rip the controller out from under the
 382         * ehci driver
 383         */
 384        if (udc->gadget.is_otg) {
 385                if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 386                        pr_debug("udc: Leaving early\n");
 387                        return;
 388                }
 389        }
 390
 391        /* disable all INTR */
 392        fsl_writel(0, &dr_regs->usbintr);
 393
 394        /* Set stopped bit for isr */
 395        udc->stopped = 1;
 396
 397        /* disable IO output */
 398/*      usb_sys_regs->control = 0; */
 399
 400        /* set controller to Stop */
 401        tmp = fsl_readl(&dr_regs->usbcmd);
 402        tmp &= ~USB_CMD_RUN_STOP;
 403        fsl_writel(tmp, &dr_regs->usbcmd);
 404}
 405
 406static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 407                        unsigned char ep_type)
 408{
 409        unsigned int tmp_epctrl = 0;
 410
 411        tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 412        if (dir) {
 413                if (ep_num)
 414                        tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 415                tmp_epctrl |= EPCTRL_TX_ENABLE;
 416                tmp_epctrl &= ~EPCTRL_TX_TYPE;
 417                tmp_epctrl |= ((unsigned int)(ep_type)
 418                                << EPCTRL_TX_EP_TYPE_SHIFT);
 419        } else {
 420                if (ep_num)
 421                        tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 422                tmp_epctrl |= EPCTRL_RX_ENABLE;
 423                tmp_epctrl &= ~EPCTRL_RX_TYPE;
 424                tmp_epctrl |= ((unsigned int)(ep_type)
 425                                << EPCTRL_RX_EP_TYPE_SHIFT);
 426        }
 427
 428        fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 429}
 430
 431static void
 432dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 433{
 434        u32 tmp_epctrl = 0;
 435
 436        tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 437
 438        if (value) {
 439                /* set the stall bit */
 440                if (dir)
 441                        tmp_epctrl |= EPCTRL_TX_EP_STALL;
 442                else
 443                        tmp_epctrl |= EPCTRL_RX_EP_STALL;
 444        } else {
 445                /* clear the stall bit and reset data toggle */
 446                if (dir) {
 447                        tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 448                        tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 449                } else {
 450                        tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 451                        tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 452                }
 453        }
 454        fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 455}
 456
 457/* Get stall status of a specific ep
 458   Return: 0: not stalled; 1:stalled */
 459static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 460{
 461        u32 epctrl;
 462
 463        epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 464        if (dir)
 465                return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 466        else
 467                return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 468}
 469
 470/********************************************************************
 471        Internal Structure Build up functions
 472********************************************************************/
 473
 474/*------------------------------------------------------------------
 475* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 476 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 477 * @mult: Mult field
 478 ------------------------------------------------------------------*/
 479static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 480                unsigned char dir, unsigned char ep_type,
 481                unsigned int max_pkt_len,
 482                unsigned int zlt, unsigned char mult)
 483{
 484        struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 485        unsigned int tmp = 0;
 486
 487        /* set the Endpoint Capabilites in QH */
 488        switch (ep_type) {
 489        case USB_ENDPOINT_XFER_CONTROL:
 490                /* Interrupt On Setup (IOS). for control ep  */
 491                tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 492                        | EP_QUEUE_HEAD_IOS;
 493                break;
 494        case USB_ENDPOINT_XFER_ISOC:
 495                tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 496                        | (mult << EP_QUEUE_HEAD_MULT_POS);
 497                break;
 498        case USB_ENDPOINT_XFER_BULK:
 499        case USB_ENDPOINT_XFER_INT:
 500                tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 501                break;
 502        default:
 503                VDBG("error ep type is %d", ep_type);
 504                return;
 505        }
 506        if (zlt)
 507                tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 508
 509        p_QH->max_pkt_length = cpu_to_hc32(tmp);
 510        p_QH->next_dtd_ptr = 1;
 511        p_QH->size_ioc_int_sts = 0;
 512}
 513
 514/* Setup qh structure and ep register for ep0. */
 515static void ep0_setup(struct fsl_udc *udc)
 516{
 517        /* the intialization of an ep includes: fields in QH, Regs,
 518         * fsl_ep struct */
 519        struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 520                        USB_MAX_CTRL_PAYLOAD, 0, 0);
 521        struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 522                        USB_MAX_CTRL_PAYLOAD, 0, 0);
 523        dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 524        dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 525
 526        return;
 527
 528}
 529
 530/***********************************************************************
 531                Endpoint Management Functions
 532***********************************************************************/
 533
 534/*-------------------------------------------------------------------------
 535 * when configurations are set, or when interface settings change
 536 * for example the do_set_interface() in gadget layer,
 537 * the driver will enable or disable the relevant endpoints
 538 * ep0 doesn't use this routine. It is always enabled.
 539-------------------------------------------------------------------------*/
 540static int fsl_ep_enable(struct usb_ep *_ep,
 541                const struct usb_endpoint_descriptor *desc)
 542{
 543        struct fsl_udc *udc = NULL;
 544        struct fsl_ep *ep = NULL;
 545        unsigned short max = 0;
 546        unsigned char mult = 0, zlt;
 547        int retval = -EINVAL;
 548        unsigned long flags = 0;
 549
 550        ep = container_of(_ep, struct fsl_ep, ep);
 551
 552        /* catch various bogus parameters */
 553        if (!_ep || !desc || ep->desc
 554                        || (desc->bDescriptorType != USB_DT_ENDPOINT))
 555                return -EINVAL;
 556
 557        udc = ep->udc;
 558
 559        if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 560                return -ESHUTDOWN;
 561
 562        max = usb_endpoint_maxp(desc);
 563
 564        /* Disable automatic zlp generation.  Driver is responsible to indicate
 565         * explicitly through req->req.zero.  This is needed to enable multi-td
 566         * request. */
 567        zlt = 1;
 568
 569        /* Assume the max packet size from gadget is always correct */
 570        switch (desc->bmAttributes & 0x03) {
 571        case USB_ENDPOINT_XFER_CONTROL:
 572        case USB_ENDPOINT_XFER_BULK:
 573        case USB_ENDPOINT_XFER_INT:
 574                /* mult = 0.  Execute N Transactions as demonstrated by
 575                 * the USB variable length packet protocol where N is
 576                 * computed using the Maximum Packet Length (dQH) and
 577                 * the Total Bytes field (dTD) */
 578                mult = 0;
 579                break;
 580        case USB_ENDPOINT_XFER_ISOC:
 581                /* Calculate transactions needed for high bandwidth iso */
 582                mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 583                max = max & 0x7ff;      /* bit 0~10 */
 584                /* 3 transactions at most */
 585                if (mult > 3)
 586                        goto en_done;
 587                break;
 588        default:
 589                goto en_done;
 590        }
 591
 592        spin_lock_irqsave(&udc->lock, flags);
 593        ep->ep.maxpacket = max;
 594        ep->desc = desc;
 595        ep->stopped = 0;
 596
 597        /* Controller related setup */
 598        /* Init EPx Queue Head (Ep Capabilites field in QH
 599         * according to max, zlt, mult) */
 600        struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 601                        (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 602                                        ?  USB_SEND : USB_RECV),
 603                        (unsigned char) (desc->bmAttributes
 604                                        & USB_ENDPOINT_XFERTYPE_MASK),
 605                        max, zlt, mult);
 606
 607        /* Init endpoint ctrl register */
 608        dr_ep_setup((unsigned char) ep_index(ep),
 609                        (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 610                                        ? USB_SEND : USB_RECV),
 611                        (unsigned char) (desc->bmAttributes
 612                                        & USB_ENDPOINT_XFERTYPE_MASK));
 613
 614        spin_unlock_irqrestore(&udc->lock, flags);
 615        retval = 0;
 616
 617        VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 618                        ep->desc->bEndpointAddress & 0x0f,
 619                        (desc->bEndpointAddress & USB_DIR_IN)
 620                                ? "in" : "out", max);
 621en_done:
 622        return retval;
 623}
 624
 625/*---------------------------------------------------------------------
 626 * @ep : the ep being unconfigured. May not be ep0
 627 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 628*---------------------------------------------------------------------*/
 629static int fsl_ep_disable(struct usb_ep *_ep)
 630{
 631        struct fsl_udc *udc = NULL;
 632        struct fsl_ep *ep = NULL;
 633        unsigned long flags = 0;
 634        u32 epctrl;
 635        int ep_num;
 636
 637        ep = container_of(_ep, struct fsl_ep, ep);
 638        if (!_ep || !ep->desc) {
 639                VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 640                return -EINVAL;
 641        }
 642
 643        /* disable ep on controller */
 644        ep_num = ep_index(ep);
 645        epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 646        if (ep_is_in(ep)) {
 647                epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 648                epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 649        } else {
 650                epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 651                epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 652        }
 653        fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 654
 655        udc = (struct fsl_udc *)ep->udc;
 656        spin_lock_irqsave(&udc->lock, flags);
 657
 658        /* nuke all pending requests (does flush) */
 659        nuke(ep, -ESHUTDOWN);
 660
 661        ep->desc = NULL;
 662        ep->ep.desc = NULL;
 663        ep->stopped = 1;
 664        spin_unlock_irqrestore(&udc->lock, flags);
 665
 666        VDBG("disabled %s OK", _ep->name);
 667        return 0;
 668}
 669
 670/*---------------------------------------------------------------------
 671 * allocate a request object used by this endpoint
 672 * the main operation is to insert the req->queue to the eq->queue
 673 * Returns the request, or null if one could not be allocated
 674*---------------------------------------------------------------------*/
 675static struct usb_request *
 676fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 677{
 678        struct fsl_req *req = NULL;
 679
 680        req = kzalloc(sizeof *req, gfp_flags);
 681        if (!req)
 682                return NULL;
 683
 684        req->req.dma = DMA_ADDR_INVALID;
 685        INIT_LIST_HEAD(&req->queue);
 686
 687        return &req->req;
 688}
 689
 690static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 691{
 692        struct fsl_req *req = NULL;
 693
 694        req = container_of(_req, struct fsl_req, req);
 695
 696        if (_req)
 697                kfree(req);
 698}
 699
 700/* Actually add a dTD chain to an empty dQH and let go */
 701static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
 702{
 703        struct ep_queue_head *qh = get_qh_by_ep(ep);
 704
 705        /* Write dQH next pointer and terminate bit to 0 */
 706        qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
 707                        & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
 708
 709        /* Clear active and halt bit */
 710        qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 711                                        | EP_QUEUE_HEAD_STATUS_HALT));
 712
 713        /* Ensure that updates to the QH will occur before priming. */
 714        wmb();
 715
 716        /* Prime endpoint by writing correct bit to ENDPTPRIME */
 717        fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
 718                        : (1 << (ep_index(ep))), &dr_regs->endpointprime);
 719}
 720
 721/* Add dTD chain to the dQH of an EP */
 722static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 723{
 724        u32 temp, bitmask, tmp_stat;
 725
 726        /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 727        VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 728
 729        bitmask = ep_is_in(ep)
 730                ? (1 << (ep_index(ep) + 16))
 731                : (1 << (ep_index(ep)));
 732
 733        /* check if the pipe is empty */
 734        if (!(list_empty(&ep->queue))) {
 735                /* Add td to the end */
 736                struct fsl_req *lastreq;
 737                lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 738                lastreq->tail->next_td_ptr =
 739                        cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 740                /* Read prime bit, if 1 goto done */
 741                if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 742                        return;
 743
 744                do {
 745                        /* Set ATDTW bit in USBCMD */
 746                        temp = fsl_readl(&dr_regs->usbcmd);
 747                        fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 748
 749                        /* Read correct status bit */
 750                        tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 751
 752                } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 753
 754                /* Write ATDTW bit to 0 */
 755                temp = fsl_readl(&dr_regs->usbcmd);
 756                fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 757
 758                if (tmp_stat)
 759                        return;
 760        }
 761
 762        fsl_prime_ep(ep, req->head);
 763}
 764
 765/* Fill in the dTD structure
 766 * @req: request that the transfer belongs to
 767 * @length: return actually data length of the dTD
 768 * @dma: return dma address of the dTD
 769 * @is_last: return flag if it is the last dTD of the request
 770 * return: pointer to the built dTD */
 771static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 772                dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
 773{
 774        u32 swap_temp;
 775        struct ep_td_struct *dtd;
 776
 777        /* how big will this transfer be? */
 778        *length = min(req->req.length - req->req.actual,
 779                        (unsigned)EP_MAX_LENGTH_TRANSFER);
 780
 781        dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
 782        if (dtd == NULL)
 783                return dtd;
 784
 785        dtd->td_dma = *dma;
 786        /* Clear reserved field */
 787        swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 788        swap_temp &= ~DTD_RESERVED_FIELDS;
 789        dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 790
 791        /* Init all of buffer page pointers */
 792        swap_temp = (u32) (req->req.dma + req->req.actual);
 793        dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 794        dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 795        dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 796        dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 797        dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 798
 799        req->req.actual += *length;
 800
 801        /* zlp is needed if req->req.zero is set */
 802        if (req->req.zero) {
 803                if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 804                        *is_last = 1;
 805                else
 806                        *is_last = 0;
 807        } else if (req->req.length == req->req.actual)
 808                *is_last = 1;
 809        else
 810                *is_last = 0;
 811
 812        if ((*is_last) == 0)
 813                VDBG("multi-dtd request!");
 814        /* Fill in the transfer size; set active bit */
 815        swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 816
 817        /* Enable interrupt for the last dtd of a request */
 818        if (*is_last && !req->req.no_interrupt)
 819                swap_temp |= DTD_IOC;
 820
 821        dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 822
 823        mb();
 824
 825        VDBG("length = %d address= 0x%x", *length, (int)*dma);
 826
 827        return dtd;
 828}
 829
 830/* Generate dtd chain for a request */
 831static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
 832{
 833        unsigned        count;
 834        int             is_last;
 835        int             is_first =1;
 836        struct ep_td_struct     *last_dtd = NULL, *dtd;
 837        dma_addr_t dma;
 838
 839        do {
 840                dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
 841                if (dtd == NULL)
 842                        return -ENOMEM;
 843
 844                if (is_first) {
 845                        is_first = 0;
 846                        req->head = dtd;
 847                } else {
 848                        last_dtd->next_td_ptr = cpu_to_hc32(dma);
 849                        last_dtd->next_td_virt = dtd;
 850                }
 851                last_dtd = dtd;
 852
 853                req->dtd_count++;
 854        } while (!is_last);
 855
 856        dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 857
 858        req->tail = dtd;
 859
 860        return 0;
 861}
 862
 863/* queues (submits) an I/O request to an endpoint */
 864static int
 865fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 866{
 867        struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 868        struct fsl_req *req = container_of(_req, struct fsl_req, req);
 869        struct fsl_udc *udc;
 870        unsigned long flags;
 871
 872        /* catch various bogus parameters */
 873        if (!_req || !req->req.complete || !req->req.buf
 874                        || !list_empty(&req->queue)) {
 875                VDBG("%s, bad params", __func__);
 876                return -EINVAL;
 877        }
 878        if (unlikely(!_ep || !ep->desc)) {
 879                VDBG("%s, bad ep", __func__);
 880                return -EINVAL;
 881        }
 882        if (usb_endpoint_xfer_isoc(ep->desc)) {
 883                if (req->req.length > ep->ep.maxpacket)
 884                        return -EMSGSIZE;
 885        }
 886
 887        udc = ep->udc;
 888        if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 889                return -ESHUTDOWN;
 890
 891        req->ep = ep;
 892
 893        /* map virtual address to hardware */
 894        if (req->req.dma == DMA_ADDR_INVALID) {
 895                req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 896                                        req->req.buf,
 897                                        req->req.length, ep_is_in(ep)
 898                                                ? DMA_TO_DEVICE
 899                                                : DMA_FROM_DEVICE);
 900                req->mapped = 1;
 901        } else {
 902                dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 903                                        req->req.dma, req->req.length,
 904                                        ep_is_in(ep)
 905                                                ? DMA_TO_DEVICE
 906                                                : DMA_FROM_DEVICE);
 907                req->mapped = 0;
 908        }
 909
 910        req->req.status = -EINPROGRESS;
 911        req->req.actual = 0;
 912        req->dtd_count = 0;
 913
 914        /* build dtds and push them to device queue */
 915        if (!fsl_req_to_dtd(req, gfp_flags)) {
 916                spin_lock_irqsave(&udc->lock, flags);
 917                fsl_queue_td(ep, req);
 918        } else {
 919                return -ENOMEM;
 920        }
 921
 922        /* Update ep0 state */
 923        if ((ep_index(ep) == 0))
 924                udc->ep0_state = DATA_STATE_XMIT;
 925
 926        /* irq handler advances the queue */
 927        if (req != NULL)
 928                list_add_tail(&req->queue, &ep->queue);
 929        spin_unlock_irqrestore(&udc->lock, flags);
 930
 931        return 0;
 932}
 933
 934/* dequeues (cancels, unlinks) an I/O request from an endpoint */
 935static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 936{
 937        struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 938        struct fsl_req *req;
 939        unsigned long flags;
 940        int ep_num, stopped, ret = 0;
 941        u32 epctrl;
 942
 943        if (!_ep || !_req)
 944                return -EINVAL;
 945
 946        spin_lock_irqsave(&ep->udc->lock, flags);
 947        stopped = ep->stopped;
 948
 949        /* Stop the ep before we deal with the queue */
 950        ep->stopped = 1;
 951        ep_num = ep_index(ep);
 952        epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 953        if (ep_is_in(ep))
 954                epctrl &= ~EPCTRL_TX_ENABLE;
 955        else
 956                epctrl &= ~EPCTRL_RX_ENABLE;
 957        fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 958
 959        /* make sure it's actually queued on this endpoint */
 960        list_for_each_entry(req, &ep->queue, queue) {
 961                if (&req->req == _req)
 962                        break;
 963        }
 964        if (&req->req != _req) {
 965                ret = -EINVAL;
 966                goto out;
 967        }
 968
 969        /* The request is in progress, or completed but not dequeued */
 970        if (ep->queue.next == &req->queue) {
 971                _req->status = -ECONNRESET;
 972                fsl_ep_fifo_flush(_ep); /* flush current transfer */
 973
 974                /* The request isn't the last request in this ep queue */
 975                if (req->queue.next != &ep->queue) {
 976                        struct fsl_req *next_req;
 977
 978                        next_req = list_entry(req->queue.next, struct fsl_req,
 979                                        queue);
 980
 981                        /* prime with dTD of next request */
 982                        fsl_prime_ep(ep, next_req->head);
 983                }
 984        /* The request hasn't been processed, patch up the TD chain */
 985        } else {
 986                struct fsl_req *prev_req;
 987
 988                prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 989                prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
 990        }
 991
 992        done(ep, req, -ECONNRESET);
 993
 994        /* Enable EP */
 995out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 996        if (ep_is_in(ep))
 997                epctrl |= EPCTRL_TX_ENABLE;
 998        else
 999                epctrl |= EPCTRL_RX_ENABLE;
1000        fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1001        ep->stopped = stopped;
1002
1003        spin_unlock_irqrestore(&ep->udc->lock, flags);
1004        return ret;
1005}
1006
1007/*-------------------------------------------------------------------------*/
1008
1009/*-----------------------------------------------------------------
1010 * modify the endpoint halt feature
1011 * @ep: the non-isochronous endpoint being stalled
1012 * @value: 1--set halt  0--clear halt
1013 * Returns zero, or a negative error code.
1014*----------------------------------------------------------------*/
1015static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1016{
1017        struct fsl_ep *ep = NULL;
1018        unsigned long flags = 0;
1019        int status = -EOPNOTSUPP;       /* operation not supported */
1020        unsigned char ep_dir = 0, ep_num = 0;
1021        struct fsl_udc *udc = NULL;
1022
1023        ep = container_of(_ep, struct fsl_ep, ep);
1024        udc = ep->udc;
1025        if (!_ep || !ep->desc) {
1026                status = -EINVAL;
1027                goto out;
1028        }
1029
1030        if (usb_endpoint_xfer_isoc(ep->desc)) {
1031                status = -EOPNOTSUPP;
1032                goto out;
1033        }
1034
1035        /* Attempt to halt IN ep will fail if any transfer requests
1036         * are still queue */
1037        if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1038                status = -EAGAIN;
1039                goto out;
1040        }
1041
1042        status = 0;
1043        ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1044        ep_num = (unsigned char)(ep_index(ep));
1045        spin_lock_irqsave(&ep->udc->lock, flags);
1046        dr_ep_change_stall(ep_num, ep_dir, value);
1047        spin_unlock_irqrestore(&ep->udc->lock, flags);
1048
1049        if (ep_index(ep) == 0) {
1050                udc->ep0_state = WAIT_FOR_SETUP;
1051                udc->ep0_dir = 0;
1052        }
1053out:
1054        VDBG(" %s %s halt stat %d", ep->ep.name,
1055                        value ?  "set" : "clear", status);
1056
1057        return status;
1058}
1059
1060static int fsl_ep_fifo_status(struct usb_ep *_ep)
1061{
1062        struct fsl_ep *ep;
1063        struct fsl_udc *udc;
1064        int size = 0;
1065        u32 bitmask;
1066        struct ep_queue_head *qh;
1067
1068        ep = container_of(_ep, struct fsl_ep, ep);
1069        if (!_ep || (!ep->desc && ep_index(ep) != 0))
1070                return -ENODEV;
1071
1072        udc = (struct fsl_udc *)ep->udc;
1073
1074        if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1075                return -ESHUTDOWN;
1076
1077        qh = get_qh_by_ep(ep);
1078
1079        bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1080            (1 << (ep_index(ep)));
1081
1082        if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1083                size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1084                    >> DTD_LENGTH_BIT_POS;
1085
1086        pr_debug("%s %u\n", __func__, size);
1087        return size;
1088}
1089
1090static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1091{
1092        struct fsl_ep *ep;
1093        int ep_num, ep_dir;
1094        u32 bits;
1095        unsigned long timeout;
1096#define FSL_UDC_FLUSH_TIMEOUT 1000
1097
1098        if (!_ep) {
1099                return;
1100        } else {
1101                ep = container_of(_ep, struct fsl_ep, ep);
1102                if (!ep->desc)
1103                        return;
1104        }
1105        ep_num = ep_index(ep);
1106        ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1107
1108        if (ep_num == 0)
1109                bits = (1 << 16) | 1;
1110        else if (ep_dir == USB_SEND)
1111                bits = 1 << (16 + ep_num);
1112        else
1113                bits = 1 << ep_num;
1114
1115        timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1116        do {
1117                fsl_writel(bits, &dr_regs->endptflush);
1118
1119                /* Wait until flush complete */
1120                while (fsl_readl(&dr_regs->endptflush)) {
1121                        if (time_after(jiffies, timeout)) {
1122                                ERR("ep flush timeout\n");
1123                                return;
1124                        }
1125                        cpu_relax();
1126                }
1127                /* See if we need to flush again */
1128        } while (fsl_readl(&dr_regs->endptstatus) & bits);
1129}
1130
1131static struct usb_ep_ops fsl_ep_ops = {
1132        .enable = fsl_ep_enable,
1133        .disable = fsl_ep_disable,
1134
1135        .alloc_request = fsl_alloc_request,
1136        .free_request = fsl_free_request,
1137
1138        .queue = fsl_ep_queue,
1139        .dequeue = fsl_ep_dequeue,
1140
1141        .set_halt = fsl_ep_set_halt,
1142        .fifo_status = fsl_ep_fifo_status,
1143        .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1144};
1145
1146/*-------------------------------------------------------------------------
1147                Gadget Driver Layer Operations
1148-------------------------------------------------------------------------*/
1149
1150/*----------------------------------------------------------------------
1151 * Get the current frame number (from DR frame_index Reg )
1152 *----------------------------------------------------------------------*/
1153static int fsl_get_frame(struct usb_gadget *gadget)
1154{
1155        return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1156}
1157
1158/*-----------------------------------------------------------------------
1159 * Tries to wake up the host connected to this gadget
1160 -----------------------------------------------------------------------*/
1161static int fsl_wakeup(struct usb_gadget *gadget)
1162{
1163        struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1164        u32 portsc;
1165
1166        /* Remote wakeup feature not enabled by host */
1167        if (!udc->remote_wakeup)
1168                return -ENOTSUPP;
1169
1170        portsc = fsl_readl(&dr_regs->portsc1);
1171        /* not suspended? */
1172        if (!(portsc & PORTSCX_PORT_SUSPEND))
1173                return 0;
1174        /* trigger force resume */
1175        portsc |= PORTSCX_PORT_FORCE_RESUME;
1176        fsl_writel(portsc, &dr_regs->portsc1);
1177        return 0;
1178}
1179
1180static int can_pullup(struct fsl_udc *udc)
1181{
1182        return udc->driver && udc->softconnect && udc->vbus_active;
1183}
1184
1185/* Notify controller that VBUS is powered, Called by whatever
1186   detects VBUS sessions */
1187static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1188{
1189        struct fsl_udc  *udc;
1190        unsigned long   flags;
1191
1192        udc = container_of(gadget, struct fsl_udc, gadget);
1193        spin_lock_irqsave(&udc->lock, flags);
1194        VDBG("VBUS %s", is_active ? "on" : "off");
1195        udc->vbus_active = (is_active != 0);
1196        if (can_pullup(udc))
1197                fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1198                                &dr_regs->usbcmd);
1199        else
1200                fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1201                                &dr_regs->usbcmd);
1202        spin_unlock_irqrestore(&udc->lock, flags);
1203        return 0;
1204}
1205
1206/* constrain controller's VBUS power usage
1207 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1208 * reporting how much power the device may consume.  For example, this
1209 * could affect how quickly batteries are recharged.
1210 *
1211 * Returns zero on success, else negative errno.
1212 */
1213static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1214{
1215        struct fsl_udc *udc;
1216
1217        udc = container_of(gadget, struct fsl_udc, gadget);
1218        if (udc->transceiver)
1219                return otg_set_power(udc->transceiver, mA);
1220        return -ENOTSUPP;
1221}
1222
1223/* Change Data+ pullup status
1224 * this func is used by usb_gadget_connect/disconnet
1225 */
1226static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1227{
1228        struct fsl_udc *udc;
1229
1230        udc = container_of(gadget, struct fsl_udc, gadget);
1231        udc->softconnect = (is_on != 0);
1232        if (can_pullup(udc))
1233                fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1234                                &dr_regs->usbcmd);
1235        else
1236                fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1237                                &dr_regs->usbcmd);
1238
1239        return 0;
1240}
1241
1242static int fsl_start(struct usb_gadget_driver *driver,
1243                int (*bind)(struct usb_gadget *));
1244static int fsl_stop(struct usb_gadget_driver *driver);
1245/* defined in gadget.h */
1246static struct usb_gadget_ops fsl_gadget_ops = {
1247        .get_frame = fsl_get_frame,
1248        .wakeup = fsl_wakeup,
1249/*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1250        .vbus_session = fsl_vbus_session,
1251        .vbus_draw = fsl_vbus_draw,
1252        .pullup = fsl_pullup,
1253        .start = fsl_start,
1254        .stop = fsl_stop,
1255};
1256
1257/* Set protocol stall on ep0, protocol stall will automatically be cleared
1258   on new transaction */
1259static void ep0stall(struct fsl_udc *udc)
1260{
1261        u32 tmp;
1262
1263        /* must set tx and rx to stall at the same time */
1264        tmp = fsl_readl(&dr_regs->endptctrl[0]);
1265        tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1266        fsl_writel(tmp, &dr_regs->endptctrl[0]);
1267        udc->ep0_state = WAIT_FOR_SETUP;
1268        udc->ep0_dir = 0;
1269}
1270
1271/* Prime a status phase for ep0 */
1272static int ep0_prime_status(struct fsl_udc *udc, int direction)
1273{
1274        struct fsl_req *req = udc->status_req;
1275        struct fsl_ep *ep;
1276
1277        if (direction == EP_DIR_IN)
1278                udc->ep0_dir = USB_DIR_IN;
1279        else
1280                udc->ep0_dir = USB_DIR_OUT;
1281
1282        ep = &udc->eps[0];
1283        udc->ep0_state = WAIT_FOR_OUT_STATUS;
1284
1285        req->ep = ep;
1286        req->req.length = 0;
1287        req->req.status = -EINPROGRESS;
1288        req->req.actual = 0;
1289        req->req.complete = NULL;
1290        req->dtd_count = 0;
1291
1292        req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1293                        req->req.buf, req->req.length,
1294                        ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1295        req->mapped = 1;
1296
1297        if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1298                fsl_queue_td(ep, req);
1299        else
1300                return -ENOMEM;
1301
1302        list_add_tail(&req->queue, &ep->queue);
1303
1304        return 0;
1305}
1306
1307static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1308{
1309        struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1310
1311        if (ep->name)
1312                nuke(ep, -ESHUTDOWN);
1313}
1314
1315/*
1316 * ch9 Set address
1317 */
1318static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1319{
1320        /* Save the new address to device struct */
1321        udc->device_address = (u8) value;
1322        /* Update usb state */
1323        udc->usb_state = USB_STATE_ADDRESS;
1324        /* Status phase */
1325        if (ep0_prime_status(udc, EP_DIR_IN))
1326                ep0stall(udc);
1327}
1328
1329/*
1330 * ch9 Get status
1331 */
1332static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1333                u16 index, u16 length)
1334{
1335        u16 tmp = 0;            /* Status, cpu endian */
1336        struct fsl_req *req;
1337        struct fsl_ep *ep;
1338
1339        ep = &udc->eps[0];
1340
1341        if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1342                /* Get device status */
1343                tmp = 1 << USB_DEVICE_SELF_POWERED;
1344                tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1345        } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1346                /* Get interface status */
1347                /* We don't have interface information in udc driver */
1348                tmp = 0;
1349        } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1350                /* Get endpoint status */
1351                struct fsl_ep *target_ep;
1352
1353                target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1354
1355                /* stall if endpoint doesn't exist */
1356                if (!target_ep->desc)
1357                        goto stall;
1358                tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1359                                << USB_ENDPOINT_HALT;
1360        }
1361
1362        udc->ep0_dir = USB_DIR_IN;
1363        /* Borrow the per device status_req */
1364        req = udc->status_req;
1365        /* Fill in the reqest structure */
1366        *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1367
1368        req->ep = ep;
1369        req->req.length = 2;
1370        req->req.status = -EINPROGRESS;
1371        req->req.actual = 0;
1372        req->req.complete = NULL;
1373        req->dtd_count = 0;
1374
1375        req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1376                                req->req.buf, req->req.length,
1377                                ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1378        req->mapped = 1;
1379
1380        /* prime the data phase */
1381        if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1382                fsl_queue_td(ep, req);
1383        else                    /* no mem */
1384                goto stall;
1385
1386        list_add_tail(&req->queue, &ep->queue);
1387        udc->ep0_state = DATA_STATE_XMIT;
1388        return;
1389stall:
1390        ep0stall(udc);
1391}
1392
1393static void setup_received_irq(struct fsl_udc *udc,
1394                struct usb_ctrlrequest *setup)
1395{
1396        u16 wValue = le16_to_cpu(setup->wValue);
1397        u16 wIndex = le16_to_cpu(setup->wIndex);
1398        u16 wLength = le16_to_cpu(setup->wLength);
1399
1400        udc_reset_ep_queue(udc, 0);
1401
1402        /* We process some stardard setup requests here */
1403        switch (setup->bRequest) {
1404        case USB_REQ_GET_STATUS:
1405                /* Data+Status phase from udc */
1406                if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1407                                        != (USB_DIR_IN | USB_TYPE_STANDARD))
1408                        break;
1409                ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1410                return;
1411
1412        case USB_REQ_SET_ADDRESS:
1413                /* Status phase from udc */
1414                if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1415                                                | USB_RECIP_DEVICE))
1416                        break;
1417                ch9setaddress(udc, wValue, wIndex, wLength);
1418                return;
1419
1420        case USB_REQ_CLEAR_FEATURE:
1421        case USB_REQ_SET_FEATURE:
1422                /* Status phase from udc */
1423        {
1424                int rc = -EOPNOTSUPP;
1425                u16 ptc = 0;
1426
1427                if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1428                                == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1429                        int pipe = get_pipe_by_windex(wIndex);
1430                        struct fsl_ep *ep;
1431
1432                        if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1433                                break;
1434                        ep = get_ep_by_pipe(udc, pipe);
1435
1436                        spin_unlock(&udc->lock);
1437                        rc = fsl_ep_set_halt(&ep->ep,
1438                                        (setup->bRequest == USB_REQ_SET_FEATURE)
1439                                                ? 1 : 0);
1440                        spin_lock(&udc->lock);
1441
1442                } else if ((setup->bRequestType & (USB_RECIP_MASK
1443                                | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1444                                | USB_TYPE_STANDARD)) {
1445                        /* Note: The driver has not include OTG support yet.
1446                         * This will be set when OTG support is added */
1447                        if (wValue == USB_DEVICE_TEST_MODE)
1448                                ptc = wIndex >> 8;
1449                        else if (gadget_is_otg(&udc->gadget)) {
1450                                if (setup->bRequest ==
1451                                    USB_DEVICE_B_HNP_ENABLE)
1452                                        udc->gadget.b_hnp_enable = 1;
1453                                else if (setup->bRequest ==
1454                                         USB_DEVICE_A_HNP_SUPPORT)
1455                                        udc->gadget.a_hnp_support = 1;
1456                                else if (setup->bRequest ==
1457                                         USB_DEVICE_A_ALT_HNP_SUPPORT)
1458                                        udc->gadget.a_alt_hnp_support = 1;
1459                        }
1460                        rc = 0;
1461                } else
1462                        break;
1463
1464                if (rc == 0) {
1465                        if (ep0_prime_status(udc, EP_DIR_IN))
1466                                ep0stall(udc);
1467                }
1468                if (ptc) {
1469                        u32 tmp;
1470
1471                        mdelay(10);
1472                        tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1473                        fsl_writel(tmp, &dr_regs->portsc1);
1474                        printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1475                }
1476
1477                return;
1478        }
1479
1480        default:
1481                break;
1482        }
1483
1484        /* Requests handled by gadget */
1485        if (wLength) {
1486                /* Data phase from gadget, status phase from udc */
1487                udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1488                                ?  USB_DIR_IN : USB_DIR_OUT;
1489                spin_unlock(&udc->lock);
1490                if (udc->driver->setup(&udc->gadget,
1491                                &udc->local_setup_buff) < 0)
1492                        ep0stall(udc);
1493                spin_lock(&udc->lock);
1494                udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1495                                ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1496        } else {
1497                /* No data phase, IN status from gadget */
1498                udc->ep0_dir = USB_DIR_IN;
1499                spin_unlock(&udc->lock);
1500                if (udc->driver->setup(&udc->gadget,
1501                                &udc->local_setup_buff) < 0)
1502                        ep0stall(udc);
1503                spin_lock(&udc->lock);
1504                udc->ep0_state = WAIT_FOR_OUT_STATUS;
1505        }
1506}
1507
1508/* Process request for Data or Status phase of ep0
1509 * prime status phase if needed */
1510static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1511                struct fsl_req *req)
1512{
1513        if (udc->usb_state == USB_STATE_ADDRESS) {
1514                /* Set the new address */
1515                u32 new_address = (u32) udc->device_address;
1516                fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1517                                &dr_regs->deviceaddr);
1518        }
1519
1520        done(ep0, req, 0);
1521
1522        switch (udc->ep0_state) {
1523        case DATA_STATE_XMIT:
1524                /* receive status phase */
1525                if (ep0_prime_status(udc, EP_DIR_OUT))
1526                        ep0stall(udc);
1527                break;
1528        case DATA_STATE_RECV:
1529                /* send status phase */
1530                if (ep0_prime_status(udc, EP_DIR_IN))
1531                        ep0stall(udc);
1532                break;
1533        case WAIT_FOR_OUT_STATUS:
1534                udc->ep0_state = WAIT_FOR_SETUP;
1535                break;
1536        case WAIT_FOR_SETUP:
1537                ERR("Unexpect ep0 packets\n");
1538                break;
1539        default:
1540                ep0stall(udc);
1541                break;
1542        }
1543}
1544
1545/* Tripwire mechanism to ensure a setup packet payload is extracted without
1546 * being corrupted by another incoming setup packet */
1547static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1548{
1549        u32 temp;
1550        struct ep_queue_head *qh;
1551        struct fsl_usb2_platform_data *pdata = udc->pdata;
1552
1553        qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1554
1555        /* Clear bit in ENDPTSETUPSTAT */
1556        temp = fsl_readl(&dr_regs->endptsetupstat);
1557        fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1558
1559        /* while a hazard exists when setup package arrives */
1560        do {
1561                /* Set Setup Tripwire */
1562                temp = fsl_readl(&dr_regs->usbcmd);
1563                fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1564
1565                /* Copy the setup packet to local buffer */
1566                if (pdata->le_setup_buf) {
1567                        u32 *p = (u32 *)buffer_ptr;
1568                        u32 *s = (u32 *)qh->setup_buffer;
1569
1570                        /* Convert little endian setup buffer to CPU endian */
1571                        *p++ = le32_to_cpu(*s++);
1572                        *p = le32_to_cpu(*s);
1573                } else {
1574                        memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1575                }
1576        } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1577
1578        /* Clear Setup Tripwire */
1579        temp = fsl_readl(&dr_regs->usbcmd);
1580        fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1581}
1582
1583/* process-ep_req(): free the completed Tds for this req */
1584static int process_ep_req(struct fsl_udc *udc, int pipe,
1585                struct fsl_req *curr_req)
1586{
1587        struct ep_td_struct *curr_td;
1588        int     td_complete, actual, remaining_length, j, tmp;
1589        int     status = 0;
1590        int     errors = 0;
1591        struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1592        int direction = pipe % 2;
1593
1594        curr_td = curr_req->head;
1595        td_complete = 0;
1596        actual = curr_req->req.length;
1597
1598        for (j = 0; j < curr_req->dtd_count; j++) {
1599                remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1600                                        & DTD_PACKET_SIZE)
1601                                >> DTD_LENGTH_BIT_POS;
1602                actual -= remaining_length;
1603
1604                errors = hc32_to_cpu(curr_td->size_ioc_sts);
1605                if (errors & DTD_ERROR_MASK) {
1606                        if (errors & DTD_STATUS_HALTED) {
1607                                ERR("dTD error %08x QH=%d\n", errors, pipe);
1608                                /* Clear the errors and Halt condition */
1609                                tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1610                                tmp &= ~errors;
1611                                curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1612                                status = -EPIPE;
1613                                /* FIXME: continue with next queued TD? */
1614
1615                                break;
1616                        }
1617                        if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1618                                VDBG("Transfer overflow");
1619                                status = -EPROTO;
1620                                break;
1621                        } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1622                                VDBG("ISO error");
1623                                status = -EILSEQ;
1624                                break;
1625                        } else
1626                                ERR("Unknown error has occurred (0x%x)!\n",
1627                                        errors);
1628
1629                } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1630                                & DTD_STATUS_ACTIVE) {
1631                        VDBG("Request not complete");
1632                        status = REQ_UNCOMPLETE;
1633                        return status;
1634                } else if (remaining_length) {
1635                        if (direction) {
1636                                VDBG("Transmit dTD remaining length not zero");
1637                                status = -EPROTO;
1638                                break;
1639                        } else {
1640                                td_complete++;
1641                                break;
1642                        }
1643                } else {
1644                        td_complete++;
1645                        VDBG("dTD transmitted successful");
1646                }
1647
1648                if (j != curr_req->dtd_count - 1)
1649                        curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1650        }
1651
1652        if (status)
1653                return status;
1654
1655        curr_req->req.actual = actual;
1656
1657        return 0;
1658}
1659
1660/* Process a DTD completion interrupt */
1661static void dtd_complete_irq(struct fsl_udc *udc)
1662{
1663        u32 bit_pos;
1664        int i, ep_num, direction, bit_mask, status;
1665        struct fsl_ep *curr_ep;
1666        struct fsl_req *curr_req, *temp_req;
1667
1668        /* Clear the bits in the register */
1669        bit_pos = fsl_readl(&dr_regs->endptcomplete);
1670        fsl_writel(bit_pos, &dr_regs->endptcomplete);
1671
1672        if (!bit_pos)
1673                return;
1674
1675        for (i = 0; i < udc->max_ep; i++) {
1676                ep_num = i >> 1;
1677                direction = i % 2;
1678
1679                bit_mask = 1 << (ep_num + 16 * direction);
1680
1681                if (!(bit_pos & bit_mask))
1682                        continue;
1683
1684                curr_ep = get_ep_by_pipe(udc, i);
1685
1686                /* If the ep is configured */
1687                if (curr_ep->name == NULL) {
1688                        WARNING("Invalid EP?");
1689                        continue;
1690                }
1691
1692                /* process the req queue until an uncomplete request */
1693                list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1694                                queue) {
1695                        status = process_ep_req(udc, i, curr_req);
1696
1697                        VDBG("status of process_ep_req= %d, ep = %d",
1698                                        status, ep_num);
1699                        if (status == REQ_UNCOMPLETE)
1700                                break;
1701                        /* write back status to req */
1702                        curr_req->req.status = status;
1703
1704                        if (ep_num == 0) {
1705                                ep0_req_complete(udc, curr_ep, curr_req);
1706                                break;
1707                        } else
1708                                done(curr_ep, curr_req, status);
1709                }
1710        }
1711}
1712
1713static inline enum usb_device_speed portscx_device_speed(u32 reg)
1714{
1715        switch (reg & PORTSCX_PORT_SPEED_MASK) {
1716        case PORTSCX_PORT_SPEED_HIGH:
1717                return USB_SPEED_HIGH;
1718        case PORTSCX_PORT_SPEED_FULL:
1719                return USB_SPEED_FULL;
1720        case PORTSCX_PORT_SPEED_LOW:
1721                return USB_SPEED_LOW;
1722        default:
1723                return USB_SPEED_UNKNOWN;
1724        }
1725}
1726
1727/* Process a port change interrupt */
1728static void port_change_irq(struct fsl_udc *udc)
1729{
1730        if (udc->bus_reset)
1731                udc->bus_reset = 0;
1732
1733        /* Bus resetting is finished */
1734        if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1735                /* Get the speed */
1736                udc->gadget.speed =
1737                        portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1738
1739        /* Update USB state */
1740        if (!udc->resume_state)
1741                udc->usb_state = USB_STATE_DEFAULT;
1742}
1743
1744/* Process suspend interrupt */
1745static void suspend_irq(struct fsl_udc *udc)
1746{
1747        udc->resume_state = udc->usb_state;
1748        udc->usb_state = USB_STATE_SUSPENDED;
1749
1750        /* report suspend to the driver, serial.c does not support this */
1751        if (udc->driver->suspend)
1752                udc->driver->suspend(&udc->gadget);
1753}
1754
1755static void bus_resume(struct fsl_udc *udc)
1756{
1757        udc->usb_state = udc->resume_state;
1758        udc->resume_state = 0;
1759
1760        /* report resume to the driver, serial.c does not support this */
1761        if (udc->driver->resume)
1762                udc->driver->resume(&udc->gadget);
1763}
1764
1765/* Clear up all ep queues */
1766static int reset_queues(struct fsl_udc *udc)
1767{
1768        u8 pipe;
1769
1770        for (pipe = 0; pipe < udc->max_pipes; pipe++)
1771                udc_reset_ep_queue(udc, pipe);
1772
1773        /* report disconnect; the driver is already quiesced */
1774        spin_unlock(&udc->lock);
1775        udc->driver->disconnect(&udc->gadget);
1776        spin_lock(&udc->lock);
1777
1778        return 0;
1779}
1780
1781/* Process reset interrupt */
1782static void reset_irq(struct fsl_udc *udc)
1783{
1784        u32 temp;
1785        unsigned long timeout;
1786
1787        /* Clear the device address */
1788        temp = fsl_readl(&dr_regs->deviceaddr);
1789        fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1790
1791        udc->device_address = 0;
1792
1793        /* Clear usb state */
1794        udc->resume_state = 0;
1795        udc->ep0_dir = 0;
1796        udc->ep0_state = WAIT_FOR_SETUP;
1797        udc->remote_wakeup = 0; /* default to 0 on reset */
1798        udc->gadget.b_hnp_enable = 0;
1799        udc->gadget.a_hnp_support = 0;
1800        udc->gadget.a_alt_hnp_support = 0;
1801
1802        /* Clear all the setup token semaphores */
1803        temp = fsl_readl(&dr_regs->endptsetupstat);
1804        fsl_writel(temp, &dr_regs->endptsetupstat);
1805
1806        /* Clear all the endpoint complete status bits */
1807        temp = fsl_readl(&dr_regs->endptcomplete);
1808        fsl_writel(temp, &dr_regs->endptcomplete);
1809
1810        timeout = jiffies + 100;
1811        while (fsl_readl(&dr_regs->endpointprime)) {
1812                /* Wait until all endptprime bits cleared */
1813                if (time_after(jiffies, timeout)) {
1814                        ERR("Timeout for reset\n");
1815                        break;
1816                }
1817                cpu_relax();
1818        }
1819
1820        /* Write 1s to the flush register */
1821        fsl_writel(0xffffffff, &dr_regs->endptflush);
1822
1823        if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1824                VDBG("Bus reset");
1825                /* Bus is reseting */
1826                udc->bus_reset = 1;
1827                /* Reset all the queues, include XD, dTD, EP queue
1828                 * head and TR Queue */
1829                reset_queues(udc);
1830                udc->usb_state = USB_STATE_DEFAULT;
1831        } else {
1832                VDBG("Controller reset");
1833                /* initialize usb hw reg except for regs for EP, not
1834                 * touch usbintr reg */
1835                dr_controller_setup(udc);
1836
1837                /* Reset all internal used Queues */
1838                reset_queues(udc);
1839
1840                ep0_setup(udc);
1841
1842                /* Enable DR IRQ reg, Set Run bit, change udc state */
1843                dr_controller_run(udc);
1844                udc->usb_state = USB_STATE_ATTACHED;
1845        }
1846}
1847
1848/*
1849 * USB device controller interrupt handler
1850 */
1851static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1852{
1853        struct fsl_udc *udc = _udc;
1854        u32 irq_src;
1855        irqreturn_t status = IRQ_NONE;
1856        unsigned long flags;
1857
1858        /* Disable ISR for OTG host mode */
1859        if (udc->stopped)
1860                return IRQ_NONE;
1861        spin_lock_irqsave(&udc->lock, flags);
1862        irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1863        /* Clear notification bits */
1864        fsl_writel(irq_src, &dr_regs->usbsts);
1865
1866        /* VDBG("irq_src [0x%8x]", irq_src); */
1867
1868        /* Need to resume? */
1869        if (udc->usb_state == USB_STATE_SUSPENDED)
1870                if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1871                        bus_resume(udc);
1872
1873        /* USB Interrupt */
1874        if (irq_src & USB_STS_INT) {
1875                VDBG("Packet int");
1876                /* Setup package, we only support ep0 as control ep */
1877                if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1878                        tripwire_handler(udc, 0,
1879                                        (u8 *) (&udc->local_setup_buff));
1880                        setup_received_irq(udc, &udc->local_setup_buff);
1881                        status = IRQ_HANDLED;
1882                }
1883
1884                /* completion of dtd */
1885                if (fsl_readl(&dr_regs->endptcomplete)) {
1886                        dtd_complete_irq(udc);
1887                        status = IRQ_HANDLED;
1888                }
1889        }
1890
1891        /* SOF (for ISO transfer) */
1892        if (irq_src & USB_STS_SOF) {
1893                status = IRQ_HANDLED;
1894        }
1895
1896        /* Port Change */
1897        if (irq_src & USB_STS_PORT_CHANGE) {
1898                port_change_irq(udc);
1899                status = IRQ_HANDLED;
1900        }
1901
1902        /* Reset Received */
1903        if (irq_src & USB_STS_RESET) {
1904                VDBG("reset int");
1905                reset_irq(udc);
1906                status = IRQ_HANDLED;
1907        }
1908
1909        /* Sleep Enable (Suspend) */
1910        if (irq_src & USB_STS_SUSPEND) {
1911                suspend_irq(udc);
1912                status = IRQ_HANDLED;
1913        }
1914
1915        if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1916                VDBG("Error IRQ %x", irq_src);
1917        }
1918
1919        spin_unlock_irqrestore(&udc->lock, flags);
1920        return status;
1921}
1922
1923/*----------------------------------------------------------------*
1924 * Hook to gadget drivers
1925 * Called by initialization code of gadget drivers
1926*----------------------------------------------------------------*/
1927static int fsl_start(struct usb_gadget_driver *driver,
1928                int (*bind)(struct usb_gadget *))
1929{
1930        int retval = -ENODEV;
1931        unsigned long flags = 0;
1932
1933        if (!udc_controller)
1934                return -ENODEV;
1935
1936        if (!driver || driver->max_speed < USB_SPEED_FULL
1937                        || !bind || !driver->disconnect || !driver->setup)
1938                return -EINVAL;
1939
1940        if (udc_controller->driver)
1941                return -EBUSY;
1942
1943        /* lock is needed but whether should use this lock or another */
1944        spin_lock_irqsave(&udc_controller->lock, flags);
1945
1946        driver->driver.bus = NULL;
1947        /* hook up the driver */
1948        udc_controller->driver = driver;
1949        udc_controller->gadget.dev.driver = &driver->driver;
1950        spin_unlock_irqrestore(&udc_controller->lock, flags);
1951
1952        /* bind udc driver to gadget driver */
1953        retval = bind(&udc_controller->gadget);
1954        if (retval) {
1955                VDBG("bind to %s --> %d", driver->driver.name, retval);
1956                udc_controller->gadget.dev.driver = NULL;
1957                udc_controller->driver = NULL;
1958                goto out;
1959        }
1960
1961        if (udc_controller->transceiver) {
1962                /* Suspend the controller until OTG enable it */
1963                udc_controller->stopped = 1;
1964                printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1965
1966                /* connect to bus through transceiver */
1967                if (udc_controller->transceiver) {
1968                        retval = otg_set_peripheral(udc_controller->transceiver,
1969                                                    &udc_controller->gadget);
1970                        if (retval < 0) {
1971                                ERR("can't bind to transceiver\n");
1972                                driver->unbind(&udc_controller->gadget);
1973                                udc_controller->gadget.dev.driver = 0;
1974                                udc_controller->driver = 0;
1975                                return retval;
1976                        }
1977                }
1978        } else {
1979                /* Enable DR IRQ reg and set USBCMD reg Run bit */
1980                dr_controller_run(udc_controller);
1981                udc_controller->usb_state = USB_STATE_ATTACHED;
1982                udc_controller->ep0_state = WAIT_FOR_SETUP;
1983                udc_controller->ep0_dir = 0;
1984        }
1985        printk(KERN_INFO "%s: bind to driver %s\n",
1986                        udc_controller->gadget.name, driver->driver.name);
1987
1988out:
1989        if (retval)
1990                printk(KERN_WARNING "gadget driver register failed %d\n",
1991                       retval);
1992        return retval;
1993}
1994
1995/* Disconnect from gadget driver */
1996static int fsl_stop(struct usb_gadget_driver *driver)
1997{
1998        struct fsl_ep *loop_ep;
1999        unsigned long flags;
2000
2001        if (!udc_controller)
2002                return -ENODEV;
2003
2004        if (!driver || driver != udc_controller->driver || !driver->unbind)
2005                return -EINVAL;
2006
2007        if (udc_controller->transceiver)
2008                otg_set_peripheral(udc_controller->transceiver, NULL);
2009
2010        /* stop DR, disable intr */
2011        dr_controller_stop(udc_controller);
2012
2013        /* in fact, no needed */
2014        udc_controller->usb_state = USB_STATE_ATTACHED;
2015        udc_controller->ep0_state = WAIT_FOR_SETUP;
2016        udc_controller->ep0_dir = 0;
2017
2018        /* stand operation */
2019        spin_lock_irqsave(&udc_controller->lock, flags);
2020        udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2021        nuke(&udc_controller->eps[0], -ESHUTDOWN);
2022        list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2023                        ep.ep_list)
2024                nuke(loop_ep, -ESHUTDOWN);
2025        spin_unlock_irqrestore(&udc_controller->lock, flags);
2026
2027        /* report disconnect; the controller is already quiesced */
2028        driver->disconnect(&udc_controller->gadget);
2029
2030        /* unbind gadget and unhook driver. */
2031        driver->unbind(&udc_controller->gadget);
2032        udc_controller->gadget.dev.driver = NULL;
2033        udc_controller->driver = NULL;
2034
2035        printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2036               driver->driver.name);
2037        return 0;
2038}
2039
2040/*-------------------------------------------------------------------------
2041                PROC File System Support
2042-------------------------------------------------------------------------*/
2043#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2044
2045#include <linux/seq_file.h>
2046
2047static const char proc_filename[] = "driver/fsl_usb2_udc";
2048
2049static int fsl_proc_read(char *page, char **start, off_t off, int count,
2050                int *eof, void *_dev)
2051{
2052        char *buf = page;
2053        char *next = buf;
2054        unsigned size = count;
2055        unsigned long flags;
2056        int t, i;
2057        u32 tmp_reg;
2058        struct fsl_ep *ep = NULL;
2059        struct fsl_req *req;
2060
2061        struct fsl_udc *udc = udc_controller;
2062        if (off != 0)
2063                return 0;
2064
2065        spin_lock_irqsave(&udc->lock, flags);
2066
2067        /* ------basic driver information ---- */
2068        t = scnprintf(next, size,
2069                        DRIVER_DESC "\n"
2070                        "%s version: %s\n"
2071                        "Gadget driver: %s\n\n",
2072                        driver_name, DRIVER_VERSION,
2073                        udc->driver ? udc->driver->driver.name : "(none)");
2074        size -= t;
2075        next += t;
2076
2077        /* ------ DR Registers ----- */
2078        tmp_reg = fsl_readl(&dr_regs->usbcmd);
2079        t = scnprintf(next, size,
2080                        "USBCMD reg:\n"
2081                        "SetupTW: %d\n"
2082                        "Run/Stop: %s\n\n",
2083                        (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2084                        (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2085        size -= t;
2086        next += t;
2087
2088        tmp_reg = fsl_readl(&dr_regs->usbsts);
2089        t = scnprintf(next, size,
2090                        "USB Status Reg:\n"
2091                        "Dr Suspend: %d Reset Received: %d System Error: %s "
2092                        "USB Error Interrupt: %s\n\n",
2093                        (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2094                        (tmp_reg & USB_STS_RESET) ? 1 : 0,
2095                        (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2096                        (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2097        size -= t;
2098        next += t;
2099
2100        tmp_reg = fsl_readl(&dr_regs->usbintr);
2101        t = scnprintf(next, size,
2102                        "USB Intrrupt Enable Reg:\n"
2103                        "Sleep Enable: %d SOF Received Enable: %d "
2104                        "Reset Enable: %d\n"
2105                        "System Error Enable: %d "
2106                        "Port Change Dectected Enable: %d\n"
2107                        "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2108                        (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2109                        (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2110                        (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2111                        (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2112                        (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2113                        (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2114                        (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2115        size -= t;
2116        next += t;
2117
2118        tmp_reg = fsl_readl(&dr_regs->frindex);
2119        t = scnprintf(next, size,
2120                        "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2121                        (tmp_reg & USB_FRINDEX_MASKS));
2122        size -= t;
2123        next += t;
2124
2125        tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2126        t = scnprintf(next, size,
2127                        "USB Device Address Reg: Device Addr is 0x%x\n\n",
2128                        (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2129        size -= t;
2130        next += t;
2131
2132        tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2133        t = scnprintf(next, size,
2134                        "USB Endpoint List Address Reg: "
2135                        "Device Addr is 0x%x\n\n",
2136                        (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2137        size -= t;
2138        next += t;
2139
2140        tmp_reg = fsl_readl(&dr_regs->portsc1);
2141        t = scnprintf(next, size,
2142                "USB Port Status&Control Reg:\n"
2143                "Port Transceiver Type : %s Port Speed: %s\n"
2144                "PHY Low Power Suspend: %s Port Reset: %s "
2145                "Port Suspend Mode: %s\n"
2146                "Over-current Change: %s "
2147                "Port Enable/Disable Change: %s\n"
2148                "Port Enabled/Disabled: %s "
2149                "Current Connect Status: %s\n\n", ( {
2150                        char *s;
2151                        switch (tmp_reg & PORTSCX_PTS_FSLS) {
2152                        case PORTSCX_PTS_UTMI:
2153                                s = "UTMI"; break;
2154                        case PORTSCX_PTS_ULPI:
2155                                s = "ULPI "; break;
2156                        case PORTSCX_PTS_FSLS:
2157                                s = "FS/LS Serial"; break;
2158                        default:
2159                                s = "None"; break;
2160                        }
2161                        s;} ),
2162                usb_speed_string(portscx_device_speed(tmp_reg)),
2163                (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2164                "Normal PHY mode" : "Low power mode",
2165                (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2166                "Not in Reset",
2167                (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2168                (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2169                "No",
2170                (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2171                "Not change",
2172                (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2173                "Not correct",
2174                (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2175                "Attached" : "Not-Att");
2176        size -= t;
2177        next += t;
2178
2179        tmp_reg = fsl_readl(&dr_regs->usbmode);
2180        t = scnprintf(next, size,
2181                        "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2182                                char *s;
2183                                switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2184                                case USB_MODE_CTRL_MODE_IDLE:
2185                                        s = "Idle"; break;
2186                                case USB_MODE_CTRL_MODE_DEVICE:
2187                                        s = "Device Controller"; break;
2188                                case USB_MODE_CTRL_MODE_HOST:
2189                                        s = "Host Controller"; break;
2190                                default:
2191                                        s = "None"; break;
2192                                }
2193                                s;
2194                        } ));
2195        size -= t;
2196        next += t;
2197
2198        tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2199        t = scnprintf(next, size,
2200                        "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2201                        (tmp_reg & EP_SETUP_STATUS_MASK));
2202        size -= t;
2203        next += t;
2204
2205        for (i = 0; i < udc->max_ep / 2; i++) {
2206                tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2207                t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2208                                i, tmp_reg);
2209                size -= t;
2210                next += t;
2211        }
2212        tmp_reg = fsl_readl(&dr_regs->endpointprime);
2213        t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2214        size -= t;
2215        next += t;
2216
2217#ifndef CONFIG_ARCH_MXC
2218        if (udc->pdata->have_sysif_regs) {
2219                tmp_reg = usb_sys_regs->snoop1;
2220                t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2221                size -= t;
2222                next += t;
2223
2224                tmp_reg = usb_sys_regs->control;
2225                t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2226                                tmp_reg);
2227                size -= t;
2228                next += t;
2229        }
2230#endif
2231
2232        /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2233        ep = &udc->eps[0];
2234        t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2235                        ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2236        size -= t;
2237        next += t;
2238
2239        if (list_empty(&ep->queue)) {
2240                t = scnprintf(next, size, "its req queue is empty\n\n");
2241                size -= t;
2242                next += t;
2243        } else {
2244                list_for_each_entry(req, &ep->queue, queue) {
2245                        t = scnprintf(next, size,
2246                                "req %p actual 0x%x length 0x%x buf %p\n",
2247                                &req->req, req->req.actual,
2248                                req->req.length, req->req.buf);
2249                        size -= t;
2250                        next += t;
2251                }
2252        }
2253        /* other gadget->eplist ep */
2254        list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2255                if (ep->desc) {
2256                        t = scnprintf(next, size,
2257                                        "\nFor %s Maxpkt is 0x%x "
2258                                        "index is 0x%x\n",
2259                                        ep->ep.name, ep_maxpacket(ep),
2260                                        ep_index(ep));
2261                        size -= t;
2262                        next += t;
2263
2264                        if (list_empty(&ep->queue)) {
2265                                t = scnprintf(next, size,
2266                                                "its req queue is empty\n\n");
2267                                size -= t;
2268                                next += t;
2269                        } else {
2270                                list_for_each_entry(req, &ep->queue, queue) {
2271                                        t = scnprintf(next, size,
2272                                                "req %p actual 0x%x length "
2273                                                "0x%x  buf %p\n",
2274                                                &req->req, req->req.actual,
2275                                                req->req.length, req->req.buf);
2276                                        size -= t;
2277                                        next += t;
2278                                        }       /* end for each_entry of ep req */
2279                                }       /* end for else */
2280                        }       /* end for if(ep->queue) */
2281                }               /* end (ep->desc) */
2282
2283        spin_unlock_irqrestore(&udc->lock, flags);
2284
2285        *eof = 1;
2286        return count - size;
2287}
2288
2289#define create_proc_file()      create_proc_read_entry(proc_filename, \
2290                                0, NULL, fsl_proc_read, NULL)
2291
2292#define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2293
2294#else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2295
2296#define create_proc_file()      do {} while (0)
2297#define remove_proc_file()      do {} while (0)
2298
2299#endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2300
2301/*-------------------------------------------------------------------------*/
2302
2303/* Release udc structures */
2304static void fsl_udc_release(struct device *dev)
2305{
2306        complete(udc_controller->done);
2307        dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2308                        udc_controller->ep_qh, udc_controller->ep_qh_dma);
2309        kfree(udc_controller);
2310}
2311
2312/******************************************************************
2313        Internal structure setup functions
2314*******************************************************************/
2315/*------------------------------------------------------------------
2316 * init resource for globle controller
2317 * Return the udc handle on success or NULL on failure
2318 ------------------------------------------------------------------*/
2319static int __init struct_udc_setup(struct fsl_udc *udc,
2320                struct platform_device *pdev)
2321{
2322        struct fsl_usb2_platform_data *pdata;
2323        size_t size;
2324
2325        pdata = pdev->dev.platform_data;
2326        udc->phy_mode = pdata->phy_mode;
2327
2328        udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2329        if (!udc->eps) {
2330                ERR("malloc fsl_ep failed\n");
2331                return -1;
2332        }
2333
2334        /* initialized QHs, take care of alignment */
2335        size = udc->max_ep * sizeof(struct ep_queue_head);
2336        if (size < QH_ALIGNMENT)
2337                size = QH_ALIGNMENT;
2338        else if ((size % QH_ALIGNMENT) != 0) {
2339                size += QH_ALIGNMENT + 1;
2340                size &= ~(QH_ALIGNMENT - 1);
2341        }
2342        udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2343                                        &udc->ep_qh_dma, GFP_KERNEL);
2344        if (!udc->ep_qh) {
2345                ERR("malloc QHs for udc failed\n");
2346                kfree(udc->eps);
2347                return -1;
2348        }
2349
2350        udc->ep_qh_size = size;
2351
2352        /* Initialize ep0 status request structure */
2353        /* FIXME: fsl_alloc_request() ignores ep argument */
2354        udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2355                        struct fsl_req, req);
2356        /* allocate a small amount of memory to get valid address */
2357        udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2358
2359        udc->resume_state = USB_STATE_NOTATTACHED;
2360        udc->usb_state = USB_STATE_POWERED;
2361        udc->ep0_dir = 0;
2362        udc->remote_wakeup = 0; /* default to 0 on reset */
2363
2364        return 0;
2365}
2366
2367/*----------------------------------------------------------------
2368 * Setup the fsl_ep struct for eps
2369 * Link fsl_ep->ep to gadget->ep_list
2370 * ep0out is not used so do nothing here
2371 * ep0in should be taken care
2372 *--------------------------------------------------------------*/
2373static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2374                char *name, int link)
2375{
2376        struct fsl_ep *ep = &udc->eps[index];
2377
2378        ep->udc = udc;
2379        strcpy(ep->name, name);
2380        ep->ep.name = ep->name;
2381
2382        ep->ep.ops = &fsl_ep_ops;
2383        ep->stopped = 0;
2384
2385        /* for ep0: maxP defined in desc
2386         * for other eps, maxP is set by epautoconfig() called by gadget layer
2387         */
2388        ep->ep.maxpacket = (unsigned short) ~0;
2389
2390        /* the queue lists any req for this ep */
2391        INIT_LIST_HEAD(&ep->queue);
2392
2393        /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2394        if (link)
2395                list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2396        ep->gadget = &udc->gadget;
2397        ep->qh = &udc->ep_qh[index];
2398
2399        return 0;
2400}
2401
2402/* Driver probe function
2403 * all intialization operations implemented here except enabling usb_intr reg
2404 * board setup should have been done in the platform code
2405 */
2406static int __init fsl_udc_probe(struct platform_device *pdev)
2407{
2408        struct fsl_usb2_platform_data *pdata;
2409        struct resource *res;
2410        int ret = -ENODEV;
2411        unsigned int i;
2412        u32 dccparams;
2413
2414        if (strcmp(pdev->name, driver_name)) {
2415                VDBG("Wrong device");
2416                return -ENODEV;
2417        }
2418
2419        udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2420        if (udc_controller == NULL) {
2421                ERR("malloc udc failed\n");
2422                return -ENOMEM;
2423        }
2424
2425        pdata = pdev->dev.platform_data;
2426        udc_controller->pdata = pdata;
2427        spin_lock_init(&udc_controller->lock);
2428        udc_controller->stopped = 1;
2429
2430#ifdef CONFIG_USB_OTG
2431        if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2432                udc_controller->transceiver = otg_get_transceiver();
2433                if (!udc_controller->transceiver) {
2434                        ERR("Can't find OTG driver!\n");
2435                        ret = -ENODEV;
2436                        goto err_kfree;
2437                }
2438        }
2439#endif
2440
2441        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2442        if (!res) {
2443                ret = -ENXIO;
2444                goto err_kfree;
2445        }
2446
2447        if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2448                if (!request_mem_region(res->start, resource_size(res),
2449                                        driver_name)) {
2450                        ERR("request mem region for %s failed\n", pdev->name);
2451                        ret = -EBUSY;
2452                        goto err_kfree;
2453                }
2454        }
2455
2456        dr_regs = ioremap(res->start, resource_size(res));
2457        if (!dr_regs) {
2458                ret = -ENOMEM;
2459                goto err_release_mem_region;
2460        }
2461
2462        pdata->regs = (void *)dr_regs;
2463
2464        /*
2465         * do platform specific init: check the clock, grab/config pins, etc.
2466         */
2467        if (pdata->init && pdata->init(pdev)) {
2468                ret = -ENODEV;
2469                goto err_iounmap_noclk;
2470        }
2471
2472        /* Set accessors only after pdata->init() ! */
2473        fsl_set_accessors(pdata);
2474
2475#ifndef CONFIG_ARCH_MXC
2476        if (pdata->have_sysif_regs)
2477                usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2478#endif
2479
2480        /* Initialize USB clocks */
2481        ret = fsl_udc_clk_init(pdev);
2482        if (ret < 0)
2483                goto err_iounmap_noclk;
2484
2485        /* Read Device Controller Capability Parameters register */
2486        dccparams = fsl_readl(&dr_regs->dccparams);
2487        if (!(dccparams & DCCPARAMS_DC)) {
2488                ERR("This SOC doesn't support device role\n");
2489                ret = -ENODEV;
2490                goto err_iounmap;
2491        }
2492        /* Get max device endpoints */
2493        /* DEN is bidirectional ep number, max_ep doubles the number */
2494        udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2495
2496        udc_controller->irq = platform_get_irq(pdev, 0);
2497        if (!udc_controller->irq) {
2498                ret = -ENODEV;
2499                goto err_iounmap;
2500        }
2501
2502        ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2503                        driver_name, udc_controller);
2504        if (ret != 0) {
2505                ERR("cannot request irq %d err %d\n",
2506                                udc_controller->irq, ret);
2507                goto err_iounmap;
2508        }
2509
2510        /* Initialize the udc structure including QH member and other member */
2511        if (struct_udc_setup(udc_controller, pdev)) {
2512                ERR("Can't initialize udc data structure\n");
2513                ret = -ENOMEM;
2514                goto err_free_irq;
2515        }
2516
2517        if (!udc_controller->transceiver) {
2518                /* initialize usb hw reg except for regs for EP,
2519                 * leave usbintr reg untouched */
2520                dr_controller_setup(udc_controller);
2521        }
2522
2523        fsl_udc_clk_finalize(pdev);
2524
2525        /* Setup gadget structure */
2526        udc_controller->gadget.ops = &fsl_gadget_ops;
2527        udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2528        udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2529        INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2530        udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2531        udc_controller->gadget.name = driver_name;
2532
2533        /* Setup gadget.dev and register with kernel */
2534        dev_set_name(&udc_controller->gadget.dev, "gadget");
2535        udc_controller->gadget.dev.release = fsl_udc_release;
2536        udc_controller->gadget.dev.parent = &pdev->dev;
2537        ret = device_register(&udc_controller->gadget.dev);
2538        if (ret < 0)
2539                goto err_free_irq;
2540
2541        if (udc_controller->transceiver)
2542                udc_controller->gadget.is_otg = 1;
2543
2544        /* setup QH and epctrl for ep0 */
2545        ep0_setup(udc_controller);
2546
2547        /* setup udc->eps[] for ep0 */
2548        struct_ep_setup(udc_controller, 0, "ep0", 0);
2549        /* for ep0: the desc defined here;
2550         * for other eps, gadget layer called ep_enable with defined desc
2551         */
2552        udc_controller->eps[0].desc = &fsl_ep0_desc;
2553        udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2554
2555        /* setup the udc->eps[] for non-control endpoints and link
2556         * to gadget.ep_list */
2557        for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2558                char name[14];
2559
2560                sprintf(name, "ep%dout", i);
2561                struct_ep_setup(udc_controller, i * 2, name, 1);
2562                sprintf(name, "ep%din", i);
2563                struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2564        }
2565
2566        /* use dma_pool for TD management */
2567        udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2568                        sizeof(struct ep_td_struct),
2569                        DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2570        if (udc_controller->td_pool == NULL) {
2571                ret = -ENOMEM;
2572                goto err_unregister;
2573        }
2574
2575        ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2576        if (ret)
2577                goto err_del_udc;
2578
2579        create_proc_file();
2580        return 0;
2581
2582err_del_udc:
2583        dma_pool_destroy(udc_controller->td_pool);
2584err_unregister:
2585        device_unregister(&udc_controller->gadget.dev);
2586err_free_irq:
2587        free_irq(udc_controller->irq, udc_controller);
2588err_iounmap:
2589        if (pdata->exit)
2590                pdata->exit(pdev);
2591        fsl_udc_clk_release();
2592err_iounmap_noclk:
2593        iounmap(dr_regs);
2594err_release_mem_region:
2595        if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2596                release_mem_region(res->start, resource_size(res));
2597err_kfree:
2598        kfree(udc_controller);
2599        udc_controller = NULL;
2600        return ret;
2601}
2602
2603/* Driver removal function
2604 * Free resources and finish pending transactions
2605 */
2606static int __exit fsl_udc_remove(struct platform_device *pdev)
2607{
2608        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2609        struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2610
2611        DECLARE_COMPLETION(done);
2612
2613        if (!udc_controller)
2614                return -ENODEV;
2615
2616        usb_del_gadget_udc(&udc_controller->gadget);
2617        udc_controller->done = &done;
2618
2619        fsl_udc_clk_release();
2620
2621        /* DR has been stopped in usb_gadget_unregister_driver() */
2622        remove_proc_file();
2623
2624        /* Free allocated memory */
2625        kfree(udc_controller->status_req->req.buf);
2626        kfree(udc_controller->status_req);
2627        kfree(udc_controller->eps);
2628
2629        dma_pool_destroy(udc_controller->td_pool);
2630        free_irq(udc_controller->irq, udc_controller);
2631        iounmap(dr_regs);
2632        if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2633                release_mem_region(res->start, resource_size(res));
2634
2635        device_unregister(&udc_controller->gadget.dev);
2636        /* free udc --wait for the release() finished */
2637        wait_for_completion(&done);
2638
2639        /*
2640         * do platform specific un-initialization:
2641         * release iomux pins, etc.
2642         */
2643        if (pdata->exit)
2644                pdata->exit(pdev);
2645
2646        return 0;
2647}
2648
2649/*-----------------------------------------------------------------
2650 * Modify Power management attributes
2651 * Used by OTG statemachine to disable gadget temporarily
2652 -----------------------------------------------------------------*/
2653static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2654{
2655        dr_controller_stop(udc_controller);
2656        return 0;
2657}
2658
2659/*-----------------------------------------------------------------
2660 * Invoked on USB resume. May be called in_interrupt.
2661 * Here we start the DR controller and enable the irq
2662 *-----------------------------------------------------------------*/
2663static int fsl_udc_resume(struct platform_device *pdev)
2664{
2665        /* Enable DR irq reg and set controller Run */
2666        if (udc_controller->stopped) {
2667                dr_controller_setup(udc_controller);
2668                dr_controller_run(udc_controller);
2669        }
2670        udc_controller->usb_state = USB_STATE_ATTACHED;
2671        udc_controller->ep0_state = WAIT_FOR_SETUP;
2672        udc_controller->ep0_dir = 0;
2673        return 0;
2674}
2675
2676static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2677{
2678        struct fsl_udc *udc = udc_controller;
2679        u32 mode, usbcmd;
2680
2681        mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2682
2683        pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2684
2685        /*
2686         * If the controller is already stopped, then this must be a
2687         * PM suspend.  Remember this fact, so that we will leave the
2688         * controller stopped at PM resume time.
2689         */
2690        if (udc->stopped) {
2691                pr_debug("gadget already stopped, leaving early\n");
2692                udc->already_stopped = 1;
2693                return 0;
2694        }
2695
2696        if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2697                pr_debug("gadget not in device mode, leaving early\n");
2698                return 0;
2699        }
2700
2701        /* stop the controller */
2702        usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2703        fsl_writel(usbcmd, &dr_regs->usbcmd);
2704
2705        udc->stopped = 1;
2706
2707        pr_info("USB Gadget suspended\n");
2708
2709        return 0;
2710}
2711
2712static int fsl_udc_otg_resume(struct device *dev)
2713{
2714        pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2715                 udc_controller->stopped, udc_controller->already_stopped);
2716
2717        /*
2718         * If the controller was stopped at suspend time, then
2719         * don't resume it now.
2720         */
2721        if (udc_controller->already_stopped) {
2722                udc_controller->already_stopped = 0;
2723                pr_debug("gadget was already stopped, leaving early\n");
2724                return 0;
2725        }
2726
2727        pr_info("USB Gadget resume\n");
2728
2729        return fsl_udc_resume(NULL);
2730}
2731
2732/*-------------------------------------------------------------------------
2733        Register entry point for the peripheral controller driver
2734--------------------------------------------------------------------------*/
2735
2736static struct platform_driver udc_driver = {
2737        .remove  = __exit_p(fsl_udc_remove),
2738        /* these suspend and resume are not usb suspend and resume */
2739        .suspend = fsl_udc_suspend,
2740        .resume  = fsl_udc_resume,
2741        .driver  = {
2742                .name = (char *)driver_name,
2743                .owner = THIS_MODULE,
2744                /* udc suspend/resume called from OTG driver */
2745                .suspend = fsl_udc_otg_suspend,
2746                .resume  = fsl_udc_otg_resume,
2747        },
2748};
2749
2750static int __init udc_init(void)
2751{
2752        printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2753        return platform_driver_probe(&udc_driver, fsl_udc_probe);
2754}
2755
2756module_init(udc_init);
2757
2758static void __exit udc_exit(void)
2759{
2760        platform_driver_unregister(&udc_driver);
2761        printk(KERN_WARNING "%s unregistered\n", driver_desc);
2762}
2763
2764module_exit(udc_exit);
2765
2766MODULE_DESCRIPTION(DRIVER_DESC);
2767MODULE_AUTHOR(DRIVER_AUTHOR);
2768MODULE_LICENSE("GPL");
2769MODULE_ALIAS("platform:fsl-usb2-udc");
2770