linux/drivers/pci/probe.c
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   1/*
   2 * probe.c - PCI detection and setup code
   3 */
   4
   5#include <linux/kernel.h>
   6#include <linux/delay.h>
   7#include <linux/init.h>
   8#include <linux/pci.h>
   9#include <linux/slab.h>
  10#include <linux/module.h>
  11#include <linux/cpumask.h>
  12#include <linux/pci-aspm.h>
  13#include "pci.h"
  14
  15#define CARDBUS_LATENCY_TIMER   176     /* secondary latency timer */
  16#define CARDBUS_RESERVE_BUSNR   3
  17
  18/* Ugh.  Need to stop exporting this to modules. */
  19LIST_HEAD(pci_root_buses);
  20EXPORT_SYMBOL(pci_root_buses);
  21
  22
  23static int find_anything(struct device *dev, void *data)
  24{
  25        return 1;
  26}
  27
  28/*
  29 * Some device drivers need know if pci is initiated.
  30 * Basically, we think pci is not initiated when there
  31 * is no device to be found on the pci_bus_type.
  32 */
  33int no_pci_devices(void)
  34{
  35        struct device *dev;
  36        int no_devices;
  37
  38        dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
  39        no_devices = (dev == NULL);
  40        put_device(dev);
  41        return no_devices;
  42}
  43EXPORT_SYMBOL(no_pci_devices);
  44
  45/*
  46 * PCI Bus Class
  47 */
  48static void release_pcibus_dev(struct device *dev)
  49{
  50        struct pci_bus *pci_bus = to_pci_bus(dev);
  51
  52        if (pci_bus->bridge)
  53                put_device(pci_bus->bridge);
  54        pci_bus_remove_resources(pci_bus);
  55        pci_release_bus_of_node(pci_bus);
  56        kfree(pci_bus);
  57}
  58
  59static struct class pcibus_class = {
  60        .name           = "pci_bus",
  61        .dev_release    = &release_pcibus_dev,
  62        .dev_attrs      = pcibus_dev_attrs,
  63};
  64
  65static int __init pcibus_class_init(void)
  66{
  67        return class_register(&pcibus_class);
  68}
  69postcore_initcall(pcibus_class_init);
  70
  71static u64 pci_size(u64 base, u64 maxbase, u64 mask)
  72{
  73        u64 size = mask & maxbase;      /* Find the significant bits */
  74        if (!size)
  75                return 0;
  76
  77        /* Get the lowest of them to find the decode size, and
  78           from that the extent.  */
  79        size = (size & ~(size-1)) - 1;
  80
  81        /* base == maxbase can be valid only if the BAR has
  82           already been programmed with all 1s.  */
  83        if (base == maxbase && ((base | size) & mask) != mask)
  84                return 0;
  85
  86        return size;
  87}
  88
  89static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
  90{
  91        u32 mem_type;
  92        unsigned long flags;
  93
  94        if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
  95                flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
  96                flags |= IORESOURCE_IO;
  97                return flags;
  98        }
  99
 100        flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
 101        flags |= IORESOURCE_MEM;
 102        if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
 103                flags |= IORESOURCE_PREFETCH;
 104
 105        mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 106        switch (mem_type) {
 107        case PCI_BASE_ADDRESS_MEM_TYPE_32:
 108                break;
 109        case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 110                dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
 111                break;
 112        case PCI_BASE_ADDRESS_MEM_TYPE_64:
 113                flags |= IORESOURCE_MEM_64;
 114                break;
 115        default:
 116                dev_warn(&dev->dev,
 117                         "mem unknown type %x treated as 32-bit BAR\n",
 118                         mem_type);
 119                break;
 120        }
 121        return flags;
 122}
 123
 124/**
 125 * pci_read_base - read a PCI BAR
 126 * @dev: the PCI device
 127 * @type: type of the BAR
 128 * @res: resource buffer to be filled in
 129 * @pos: BAR position in the config space
 130 *
 131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
 132 */
 133int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 134                        struct resource *res, unsigned int pos)
 135{
 136        u32 l, sz, mask;
 137        u16 orig_cmd;
 138
 139        mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
 140
 141        if (!dev->mmio_always_on) {
 142                pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
 143                pci_write_config_word(dev, PCI_COMMAND,
 144                        orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 145        }
 146
 147        res->name = pci_name(dev);
 148
 149        pci_read_config_dword(dev, pos, &l);
 150        pci_write_config_dword(dev, pos, l | mask);
 151        pci_read_config_dword(dev, pos, &sz);
 152        pci_write_config_dword(dev, pos, l);
 153
 154        if (!dev->mmio_always_on)
 155                pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
 156
 157        /*
 158         * All bits set in sz means the device isn't working properly.
 159         * If the BAR isn't implemented, all bits must be 0.  If it's a
 160         * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
 161         * 1 must be clear.
 162         */
 163        if (!sz || sz == 0xffffffff)
 164                goto fail;
 165
 166        /*
 167         * I don't know how l can have all bits set.  Copied from old code.
 168         * Maybe it fixes a bug on some ancient platform.
 169         */
 170        if (l == 0xffffffff)
 171                l = 0;
 172
 173        if (type == pci_bar_unknown) {
 174                res->flags = decode_bar(dev, l);
 175                res->flags |= IORESOURCE_SIZEALIGN;
 176                if (res->flags & IORESOURCE_IO) {
 177                        l &= PCI_BASE_ADDRESS_IO_MASK;
 178                        mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
 179                } else {
 180                        l &= PCI_BASE_ADDRESS_MEM_MASK;
 181                        mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
 182                }
 183        } else {
 184                res->flags |= (l & IORESOURCE_ROM_ENABLE);
 185                l &= PCI_ROM_ADDRESS_MASK;
 186                mask = (u32)PCI_ROM_ADDRESS_MASK;
 187        }
 188
 189        if (res->flags & IORESOURCE_MEM_64) {
 190                u64 l64 = l;
 191                u64 sz64 = sz;
 192                u64 mask64 = mask | (u64)~0 << 32;
 193
 194                pci_read_config_dword(dev, pos + 4, &l);
 195                pci_write_config_dword(dev, pos + 4, ~0);
 196                pci_read_config_dword(dev, pos + 4, &sz);
 197                pci_write_config_dword(dev, pos + 4, l);
 198
 199                l64 |= ((u64)l << 32);
 200                sz64 |= ((u64)sz << 32);
 201
 202                sz64 = pci_size(l64, sz64, mask64);
 203
 204                if (!sz64)
 205                        goto fail;
 206
 207                if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
 208                        dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
 209                                pos);
 210                        goto fail;
 211                }
 212
 213                if ((sizeof(resource_size_t) < 8) && l) {
 214                        /* Address above 32-bit boundary; disable the BAR */
 215                        pci_write_config_dword(dev, pos, 0);
 216                        pci_write_config_dword(dev, pos + 4, 0);
 217                        res->start = 0;
 218                        res->end = sz64;
 219                } else {
 220                        res->start = l64;
 221                        res->end = l64 + sz64;
 222                        dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
 223                                   pos, res);
 224                }
 225        } else {
 226                sz = pci_size(l, sz, mask);
 227
 228                if (!sz)
 229                        goto fail;
 230
 231                res->start = l;
 232                res->end = l + sz;
 233
 234                dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
 235        }
 236
 237 out:
 238        return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
 239 fail:
 240        res->flags = 0;
 241        goto out;
 242}
 243
 244static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 245{
 246        unsigned int pos, reg;
 247
 248        for (pos = 0; pos < howmany; pos++) {
 249                struct resource *res = &dev->resource[pos];
 250                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
 251                pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
 252        }
 253
 254        if (rom) {
 255                struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
 256                dev->rom_base_reg = rom;
 257                res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
 258                                IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
 259                                IORESOURCE_SIZEALIGN;
 260                __pci_read_base(dev, pci_bar_mem32, res, rom);
 261        }
 262}
 263
 264static void __devinit pci_read_bridge_io(struct pci_bus *child)
 265{
 266        struct pci_dev *dev = child->self;
 267        u8 io_base_lo, io_limit_lo;
 268        unsigned long base, limit;
 269        struct resource *res;
 270
 271        res = child->resource[0];
 272        pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 273        pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 274        base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
 275        limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
 276
 277        if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
 278                u16 io_base_hi, io_limit_hi;
 279                pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 280                pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 281                base |= (io_base_hi << 16);
 282                limit |= (io_limit_hi << 16);
 283        }
 284
 285        if (base && base <= limit) {
 286                res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 287                if (!res->start)
 288                        res->start = base;
 289                if (!res->end)
 290                        res->end = limit + 0xfff;
 291                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 292        }
 293}
 294
 295static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
 296{
 297        struct pci_dev *dev = child->self;
 298        u16 mem_base_lo, mem_limit_lo;
 299        unsigned long base, limit;
 300        struct resource *res;
 301
 302        res = child->resource[1];
 303        pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 304        pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 305        base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 306        limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 307        if (base && base <= limit) {
 308                res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
 309                res->start = base;
 310                res->end = limit + 0xfffff;
 311                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 312        }
 313}
 314
 315static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
 316{
 317        struct pci_dev *dev = child->self;
 318        u16 mem_base_lo, mem_limit_lo;
 319        unsigned long base, limit;
 320        struct resource *res;
 321
 322        res = child->resource[2];
 323        pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 324        pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 325        base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
 326        limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
 327
 328        if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
 329                u32 mem_base_hi, mem_limit_hi;
 330                pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 331                pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 332
 333                /*
 334                 * Some bridges set the base > limit by default, and some
 335                 * (broken) BIOSes do not initialize them.  If we find
 336                 * this, just assume they are not being used.
 337                 */
 338                if (mem_base_hi <= mem_limit_hi) {
 339#if BITS_PER_LONG == 64
 340                        base |= ((long) mem_base_hi) << 32;
 341                        limit |= ((long) mem_limit_hi) << 32;
 342#else
 343                        if (mem_base_hi || mem_limit_hi) {
 344                                dev_err(&dev->dev, "can't handle 64-bit "
 345                                        "address space for bridge\n");
 346                                return;
 347                        }
 348#endif
 349                }
 350        }
 351        if (base && base <= limit) {
 352                res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
 353                                         IORESOURCE_MEM | IORESOURCE_PREFETCH;
 354                if (res->flags & PCI_PREF_RANGE_TYPE_64)
 355                        res->flags |= IORESOURCE_MEM_64;
 356                res->start = base;
 357                res->end = limit + 0xfffff;
 358                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 359        }
 360}
 361
 362void __devinit pci_read_bridge_bases(struct pci_bus *child)
 363{
 364        struct pci_dev *dev = child->self;
 365        struct resource *res;
 366        int i;
 367
 368        if (pci_is_root_bus(child))     /* It's a host bus, nothing to read */
 369                return;
 370
 371        dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
 372                 child->secondary, child->subordinate,
 373                 dev->transparent ? " (subtractive decode)" : "");
 374
 375        pci_bus_remove_resources(child);
 376        for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
 377                child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
 378
 379        pci_read_bridge_io(child);
 380        pci_read_bridge_mmio(child);
 381        pci_read_bridge_mmio_pref(child);
 382
 383        if (dev->transparent) {
 384                pci_bus_for_each_resource(child->parent, res, i) {
 385                        if (res) {
 386                                pci_bus_add_resource(child, res,
 387                                                     PCI_SUBTRACTIVE_DECODE);
 388                                dev_printk(KERN_DEBUG, &dev->dev,
 389                                           "  bridge window %pR (subtractive decode)\n",
 390                                           res);
 391                        }
 392                }
 393        }
 394}
 395
 396static struct pci_bus * pci_alloc_bus(void)
 397{
 398        struct pci_bus *b;
 399
 400        b = kzalloc(sizeof(*b), GFP_KERNEL);
 401        if (b) {
 402                INIT_LIST_HEAD(&b->node);
 403                INIT_LIST_HEAD(&b->children);
 404                INIT_LIST_HEAD(&b->devices);
 405                INIT_LIST_HEAD(&b->slots);
 406                INIT_LIST_HEAD(&b->resources);
 407                b->max_bus_speed = PCI_SPEED_UNKNOWN;
 408                b->cur_bus_speed = PCI_SPEED_UNKNOWN;
 409        }
 410        return b;
 411}
 412
 413static unsigned char pcix_bus_speed[] = {
 414        PCI_SPEED_UNKNOWN,              /* 0 */
 415        PCI_SPEED_66MHz_PCIX,           /* 1 */
 416        PCI_SPEED_100MHz_PCIX,          /* 2 */
 417        PCI_SPEED_133MHz_PCIX,          /* 3 */
 418        PCI_SPEED_UNKNOWN,              /* 4 */
 419        PCI_SPEED_66MHz_PCIX_ECC,       /* 5 */
 420        PCI_SPEED_100MHz_PCIX_ECC,      /* 6 */
 421        PCI_SPEED_133MHz_PCIX_ECC,      /* 7 */
 422        PCI_SPEED_UNKNOWN,              /* 8 */
 423        PCI_SPEED_66MHz_PCIX_266,       /* 9 */
 424        PCI_SPEED_100MHz_PCIX_266,      /* A */
 425        PCI_SPEED_133MHz_PCIX_266,      /* B */
 426        PCI_SPEED_UNKNOWN,              /* C */
 427        PCI_SPEED_66MHz_PCIX_533,       /* D */
 428        PCI_SPEED_100MHz_PCIX_533,      /* E */
 429        PCI_SPEED_133MHz_PCIX_533       /* F */
 430};
 431
 432static unsigned char pcie_link_speed[] = {
 433        PCI_SPEED_UNKNOWN,              /* 0 */
 434        PCIE_SPEED_2_5GT,               /* 1 */
 435        PCIE_SPEED_5_0GT,               /* 2 */
 436        PCIE_SPEED_8_0GT,               /* 3 */
 437        PCI_SPEED_UNKNOWN,              /* 4 */
 438        PCI_SPEED_UNKNOWN,              /* 5 */
 439        PCI_SPEED_UNKNOWN,              /* 6 */
 440        PCI_SPEED_UNKNOWN,              /* 7 */
 441        PCI_SPEED_UNKNOWN,              /* 8 */
 442        PCI_SPEED_UNKNOWN,              /* 9 */
 443        PCI_SPEED_UNKNOWN,              /* A */
 444        PCI_SPEED_UNKNOWN,              /* B */
 445        PCI_SPEED_UNKNOWN,              /* C */
 446        PCI_SPEED_UNKNOWN,              /* D */
 447        PCI_SPEED_UNKNOWN,              /* E */
 448        PCI_SPEED_UNKNOWN               /* F */
 449};
 450
 451void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
 452{
 453        bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
 454}
 455EXPORT_SYMBOL_GPL(pcie_update_link_speed);
 456
 457static unsigned char agp_speeds[] = {
 458        AGP_UNKNOWN,
 459        AGP_1X,
 460        AGP_2X,
 461        AGP_4X,
 462        AGP_8X
 463};
 464
 465static enum pci_bus_speed agp_speed(int agp3, int agpstat)
 466{
 467        int index = 0;
 468
 469        if (agpstat & 4)
 470                index = 3;
 471        else if (agpstat & 2)
 472                index = 2;
 473        else if (agpstat & 1)
 474                index = 1;
 475        else
 476                goto out;
 477        
 478        if (agp3) {
 479                index += 2;
 480                if (index == 5)
 481                        index = 0;
 482        }
 483
 484 out:
 485        return agp_speeds[index];
 486}
 487
 488
 489static void pci_set_bus_speed(struct pci_bus *bus)
 490{
 491        struct pci_dev *bridge = bus->self;
 492        int pos;
 493
 494        pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
 495        if (!pos)
 496                pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
 497        if (pos) {
 498                u32 agpstat, agpcmd;
 499
 500                pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
 501                bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
 502
 503                pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
 504                bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
 505        }
 506
 507        pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
 508        if (pos) {
 509                u16 status;
 510                enum pci_bus_speed max;
 511                pci_read_config_word(bridge, pos + 2, &status);
 512
 513                if (status & 0x8000) {
 514                        max = PCI_SPEED_133MHz_PCIX_533;
 515                } else if (status & 0x4000) {
 516                        max = PCI_SPEED_133MHz_PCIX_266;
 517                } else if (status & 0x0002) {
 518                        if (((status >> 12) & 0x3) == 2) {
 519                                max = PCI_SPEED_133MHz_PCIX_ECC;
 520                        } else {
 521                                max = PCI_SPEED_133MHz_PCIX;
 522                        }
 523                } else {
 524                        max = PCI_SPEED_66MHz_PCIX;
 525                }
 526
 527                bus->max_bus_speed = max;
 528                bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
 529
 530                return;
 531        }
 532
 533        pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
 534        if (pos) {
 535                u32 linkcap;
 536                u16 linksta;
 537
 538                pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
 539                bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
 540
 541                pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
 542                pcie_update_link_speed(bus, linksta);
 543        }
 544}
 545
 546
 547static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 548                                           struct pci_dev *bridge, int busnr)
 549{
 550        struct pci_bus *child;
 551        int i;
 552
 553        /*
 554         * Allocate a new bus, and inherit stuff from the parent..
 555         */
 556        child = pci_alloc_bus();
 557        if (!child)
 558                return NULL;
 559
 560        child->parent = parent;
 561        child->ops = parent->ops;
 562        child->sysdata = parent->sysdata;
 563        child->bus_flags = parent->bus_flags;
 564
 565        /* initialize some portions of the bus device, but don't register it
 566         * now as the parent is not properly set up yet.  This device will get
 567         * registered later in pci_bus_add_devices()
 568         */
 569        child->dev.class = &pcibus_class;
 570        dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
 571
 572        /*
 573         * Set up the primary, secondary and subordinate
 574         * bus numbers.
 575         */
 576        child->number = child->secondary = busnr;
 577        child->primary = parent->secondary;
 578        child->subordinate = 0xff;
 579
 580        if (!bridge)
 581                return child;
 582
 583        child->self = bridge;
 584        child->bridge = get_device(&bridge->dev);
 585        pci_set_bus_of_node(child);
 586        pci_set_bus_speed(child);
 587
 588        /* Set up default resource pointers and names.. */
 589        for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
 590                child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
 591                child->resource[i]->name = child->name;
 592        }
 593        bridge->subordinate = child;
 594
 595        return child;
 596}
 597
 598struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
 599{
 600        struct pci_bus *child;
 601
 602        child = pci_alloc_child_bus(parent, dev, busnr);
 603        if (child) {
 604                down_write(&pci_bus_sem);
 605                list_add_tail(&child->node, &parent->children);
 606                up_write(&pci_bus_sem);
 607        }
 608        return child;
 609}
 610
 611static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
 612{
 613        struct pci_bus *parent = child->parent;
 614
 615        /* Attempts to fix that up are really dangerous unless
 616           we're going to re-assign all bus numbers. */
 617        if (!pcibios_assign_all_busses())
 618                return;
 619
 620        while (parent->parent && parent->subordinate < max) {
 621                parent->subordinate = max;
 622                pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
 623                parent = parent->parent;
 624        }
 625}
 626
 627/*
 628 * If it's a bridge, configure it and scan the bus behind it.
 629 * For CardBus bridges, we don't scan behind as the devices will
 630 * be handled by the bridge driver itself.
 631 *
 632 * We need to process bridges in two passes -- first we scan those
 633 * already configured by the BIOS and after we are done with all of
 634 * them, we proceed to assigning numbers to the remaining buses in
 635 * order to avoid overlaps between old and new bus numbers.
 636 */
 637int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
 638{
 639        struct pci_bus *child;
 640        int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
 641        u32 buses, i, j = 0;
 642        u16 bctl;
 643        u8 primary, secondary, subordinate;
 644        int broken = 0;
 645
 646        pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
 647        primary = buses & 0xFF;
 648        secondary = (buses >> 8) & 0xFF;
 649        subordinate = (buses >> 16) & 0xFF;
 650
 651        dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
 652                secondary, subordinate, pass);
 653
 654        if (!primary && (primary != bus->number) && secondary && subordinate) {
 655                dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
 656                primary = bus->number;
 657        }
 658
 659        /* Check if setup is sensible at all */
 660        if (!pass &&
 661            (primary != bus->number || secondary <= bus->number)) {
 662                dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
 663                broken = 1;
 664        }
 665
 666        /* Disable MasterAbortMode during probing to avoid reporting
 667           of bus errors (in some architectures) */ 
 668        pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
 669        pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
 670                              bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 671
 672        if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
 673            !is_cardbus && !broken) {
 674                unsigned int cmax;
 675                /*
 676                 * Bus already configured by firmware, process it in the first
 677                 * pass and just note the configuration.
 678                 */
 679                if (pass)
 680                        goto out;
 681
 682                /*
 683                 * If we already got to this bus through a different bridge,
 684                 * don't re-add it. This can happen with the i450NX chipset.
 685                 *
 686                 * However, we continue to descend down the hierarchy and
 687                 * scan remaining child buses.
 688                 */
 689                child = pci_find_bus(pci_domain_nr(bus), secondary);
 690                if (!child) {
 691                        child = pci_add_new_bus(bus, dev, secondary);
 692                        if (!child)
 693                                goto out;
 694                        child->primary = primary;
 695                        child->subordinate = subordinate;
 696                        child->bridge_ctl = bctl;
 697                }
 698
 699                cmax = pci_scan_child_bus(child);
 700                if (cmax > max)
 701                        max = cmax;
 702                if (child->subordinate > max)
 703                        max = child->subordinate;
 704        } else {
 705                /*
 706                 * We need to assign a number to this bus which we always
 707                 * do in the second pass.
 708                 */
 709                if (!pass) {
 710                        if (pcibios_assign_all_busses() || broken)
 711                                /* Temporarily disable forwarding of the
 712                                   configuration cycles on all bridges in
 713                                   this bus segment to avoid possible
 714                                   conflicts in the second pass between two
 715                                   bridges programmed with overlapping
 716                                   bus ranges. */
 717                                pci_write_config_dword(dev, PCI_PRIMARY_BUS,
 718                                                       buses & ~0xffffff);
 719                        goto out;
 720                }
 721
 722                /* Clear errors */
 723                pci_write_config_word(dev, PCI_STATUS, 0xffff);
 724
 725                /* Prevent assigning a bus number that already exists.
 726                 * This can happen when a bridge is hot-plugged, so in
 727                 * this case we only re-scan this bus. */
 728                child = pci_find_bus(pci_domain_nr(bus), max+1);
 729                if (!child) {
 730                        child = pci_add_new_bus(bus, dev, ++max);
 731                        if (!child)
 732                                goto out;
 733                }
 734                buses = (buses & 0xff000000)
 735                      | ((unsigned int)(child->primary)     <<  0)
 736                      | ((unsigned int)(child->secondary)   <<  8)
 737                      | ((unsigned int)(child->subordinate) << 16);
 738
 739                /*
 740                 * yenta.c forces a secondary latency timer of 176.
 741                 * Copy that behaviour here.
 742                 */
 743                if (is_cardbus) {
 744                        buses &= ~0xff000000;
 745                        buses |= CARDBUS_LATENCY_TIMER << 24;
 746                }
 747
 748                /*
 749                 * We need to blast all three values with a single write.
 750                 */
 751                pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 752
 753                if (!is_cardbus) {
 754                        child->bridge_ctl = bctl;
 755                        /*
 756                         * Adjust subordinate busnr in parent buses.
 757                         * We do this before scanning for children because
 758                         * some devices may not be detected if the bios
 759                         * was lazy.
 760                         */
 761                        pci_fixup_parent_subordinate_busnr(child, max);
 762                        /* Now we can scan all subordinate buses... */
 763                        max = pci_scan_child_bus(child);
 764                        /*
 765                         * now fix it up again since we have found
 766                         * the real value of max.
 767                         */
 768                        pci_fixup_parent_subordinate_busnr(child, max);
 769                } else {
 770                        /*
 771                         * For CardBus bridges, we leave 4 bus numbers
 772                         * as cards with a PCI-to-PCI bridge can be
 773                         * inserted later.
 774                         */
 775                        for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
 776                                struct pci_bus *parent = bus;
 777                                if (pci_find_bus(pci_domain_nr(bus),
 778                                                        max+i+1))
 779                                        break;
 780                                while (parent->parent) {
 781                                        if ((!pcibios_assign_all_busses()) &&
 782                                            (parent->subordinate > max) &&
 783                                            (parent->subordinate <= max+i)) {
 784                                                j = 1;
 785                                        }
 786                                        parent = parent->parent;
 787                                }
 788                                if (j) {
 789                                        /*
 790                                         * Often, there are two cardbus bridges
 791                                         * -- try to leave one valid bus number
 792                                         * for each one.
 793                                         */
 794                                        i /= 2;
 795                                        break;
 796                                }
 797                        }
 798                        max += i;
 799                        pci_fixup_parent_subordinate_busnr(child, max);
 800                }
 801                /*
 802                 * Set the subordinate bus number to its real value.
 803                 */
 804                child->subordinate = max;
 805                pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
 806        }
 807
 808        sprintf(child->name,
 809                (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
 810                pci_domain_nr(bus), child->number);
 811
 812        /* Has only triggered on CardBus, fixup is in yenta_socket */
 813        while (bus->parent) {
 814                if ((child->subordinate > bus->subordinate) ||
 815                    (child->number > bus->subordinate) ||
 816                    (child->number < bus->number) ||
 817                    (child->subordinate < bus->number)) {
 818                        dev_info(&child->dev, "[bus %02x-%02x] %s "
 819                                "hidden behind%s bridge %s [bus %02x-%02x]\n",
 820                                child->number, child->subordinate,
 821                                (bus->number > child->subordinate &&
 822                                 bus->subordinate < child->number) ?
 823                                        "wholly" : "partially",
 824                                bus->self->transparent ? " transparent" : "",
 825                                dev_name(&bus->dev),
 826                                bus->number, bus->subordinate);
 827                }
 828                bus = bus->parent;
 829        }
 830
 831out:
 832        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
 833
 834        return max;
 835}
 836
 837/*
 838 * Read interrupt line and base address registers.
 839 * The architecture-dependent code can tweak these, of course.
 840 */
 841static void pci_read_irq(struct pci_dev *dev)
 842{
 843        unsigned char irq;
 844
 845        pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
 846        dev->pin = irq;
 847        if (irq)
 848                pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 849        dev->irq = irq;
 850}
 851
 852void set_pcie_port_type(struct pci_dev *pdev)
 853{
 854        int pos;
 855        u16 reg16;
 856
 857        pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 858        if (!pos)
 859                return;
 860        pdev->is_pcie = 1;
 861        pdev->pcie_cap = pos;
 862        pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
 863        pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
 864        pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
 865        pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
 866}
 867
 868void set_pcie_hotplug_bridge(struct pci_dev *pdev)
 869{
 870        int pos;
 871        u16 reg16;
 872        u32 reg32;
 873
 874        pos = pci_pcie_cap(pdev);
 875        if (!pos)
 876                return;
 877        pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
 878        if (!(reg16 & PCI_EXP_FLAGS_SLOT))
 879                return;
 880        pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
 881        if (reg32 & PCI_EXP_SLTCAP_HPC)
 882                pdev->is_hotplug_bridge = 1;
 883}
 884
 885#define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 886
 887/**
 888 * pci_setup_device - fill in class and map information of a device
 889 * @dev: the device structure to fill
 890 *
 891 * Initialize the device structure with information about the device's 
 892 * vendor,class,memory and IO-space addresses,IRQ lines etc.
 893 * Called at initialisation of the PCI subsystem and by CardBus services.
 894 * Returns 0 on success and negative if unknown type of device (not normal,
 895 * bridge or CardBus).
 896 */
 897int pci_setup_device(struct pci_dev *dev)
 898{
 899        u32 class;
 900        u8 hdr_type;
 901        struct pci_slot *slot;
 902        int pos = 0;
 903
 904        if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
 905                return -EIO;
 906
 907        dev->sysdata = dev->bus->sysdata;
 908        dev->dev.parent = dev->bus->bridge;
 909        dev->dev.bus = &pci_bus_type;
 910        dev->hdr_type = hdr_type & 0x7f;
 911        dev->multifunction = !!(hdr_type & 0x80);
 912        dev->error_state = pci_channel_io_normal;
 913        set_pcie_port_type(dev);
 914
 915        list_for_each_entry(slot, &dev->bus->slots, list)
 916                if (PCI_SLOT(dev->devfn) == slot->number)
 917                        dev->slot = slot;
 918
 919        /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
 920           set this higher, assuming the system even supports it.  */
 921        dev->dma_mask = 0xffffffff;
 922
 923        dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
 924                     dev->bus->number, PCI_SLOT(dev->devfn),
 925                     PCI_FUNC(dev->devfn));
 926
 927        pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 928        dev->revision = class & 0xff;
 929        class >>= 8;                                /* upper 3 bytes */
 930        dev->class = class;
 931        class >>= 8;
 932
 933        dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
 934                   dev->vendor, dev->device, dev->hdr_type, class);
 935
 936        /* need to have dev->class ready */
 937        dev->cfg_size = pci_cfg_space_size(dev);
 938
 939        /* "Unknown power state" */
 940        dev->current_state = PCI_UNKNOWN;
 941
 942        /* Early fixups, before probing the BARs */
 943        pci_fixup_device(pci_fixup_early, dev);
 944        /* device class may be changed after fixup */
 945        class = dev->class >> 8;
 946
 947        switch (dev->hdr_type) {                    /* header type */
 948        case PCI_HEADER_TYPE_NORMAL:                /* standard header */
 949                if (class == PCI_CLASS_BRIDGE_PCI)
 950                        goto bad;
 951                pci_read_irq(dev);
 952                pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
 953                pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 954                pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
 955
 956                /*
 957                 *      Do the ugly legacy mode stuff here rather than broken chip
 958                 *      quirk code. Legacy mode ATA controllers have fixed
 959                 *      addresses. These are not always echoed in BAR0-3, and
 960                 *      BAR0-3 in a few cases contain junk!
 961                 */
 962                if (class == PCI_CLASS_STORAGE_IDE) {
 963                        u8 progif;
 964                        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
 965                        if ((progif & 1) == 0) {
 966                                dev->resource[0].start = 0x1F0;
 967                                dev->resource[0].end = 0x1F7;
 968                                dev->resource[0].flags = LEGACY_IO_RESOURCE;
 969                                dev->resource[1].start = 0x3F6;
 970                                dev->resource[1].end = 0x3F6;
 971                                dev->resource[1].flags = LEGACY_IO_RESOURCE;
 972                        }
 973                        if ((progif & 4) == 0) {
 974                                dev->resource[2].start = 0x170;
 975                                dev->resource[2].end = 0x177;
 976                                dev->resource[2].flags = LEGACY_IO_RESOURCE;
 977                                dev->resource[3].start = 0x376;
 978                                dev->resource[3].end = 0x376;
 979                                dev->resource[3].flags = LEGACY_IO_RESOURCE;
 980                        }
 981                }
 982                break;
 983
 984        case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
 985                if (class != PCI_CLASS_BRIDGE_PCI)
 986                        goto bad;
 987                /* The PCI-to-PCI bridge spec requires that subtractive
 988                   decoding (i.e. transparent) bridge must have programming
 989                   interface code of 0x01. */ 
 990                pci_read_irq(dev);
 991                dev->transparent = ((dev->class & 0xff) == 1);
 992                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
 993                set_pcie_hotplug_bridge(dev);
 994                pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
 995                if (pos) {
 996                        pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
 997                        pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
 998                }
 999                break;
1000
1001        case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
1002                if (class != PCI_CLASS_BRIDGE_CARDBUS)
1003                        goto bad;
1004                pci_read_irq(dev);
1005                pci_read_bases(dev, 1, 0);
1006                pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1007                pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1008                break;
1009
1010        default:                                    /* unknown header */
1011                dev_err(&dev->dev, "unknown header type %02x, "
1012                        "ignoring device\n", dev->hdr_type);
1013                return -EIO;
1014
1015        bad:
1016                dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1017                        "type %02x)\n", class, dev->hdr_type);
1018                dev->class = PCI_CLASS_NOT_DEFINED;
1019        }
1020
1021        /* We found a fine healthy device, go go go... */
1022        return 0;
1023}
1024
1025static void pci_release_capabilities(struct pci_dev *dev)
1026{
1027        pci_vpd_release(dev);
1028        pci_iov_release(dev);
1029}
1030
1031/**
1032 * pci_release_dev - free a pci device structure when all users of it are finished.
1033 * @dev: device that's been disconnected
1034 *
1035 * Will be called only by the device core when all users of this pci device are
1036 * done.
1037 */
1038static void pci_release_dev(struct device *dev)
1039{
1040        struct pci_dev *pci_dev;
1041
1042        pci_dev = to_pci_dev(dev);
1043        pci_release_capabilities(pci_dev);
1044        pci_release_of_node(pci_dev);
1045        kfree(pci_dev);
1046}
1047
1048/**
1049 * pci_cfg_space_size - get the configuration space size of the PCI device.
1050 * @dev: PCI device
1051 *
1052 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1053 * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
1054 * access it.  Maybe we don't have a way to generate extended config space
1055 * accesses, or the device is behind a reverse Express bridge.  So we try
1056 * reading the dword at 0x100 which must either be 0 or a valid extended
1057 * capability header.
1058 */
1059int pci_cfg_space_size_ext(struct pci_dev *dev)
1060{
1061        u32 status;
1062        int pos = PCI_CFG_SPACE_SIZE;
1063
1064        if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1065                goto fail;
1066        if (status == 0xffffffff)
1067                goto fail;
1068
1069        return PCI_CFG_SPACE_EXP_SIZE;
1070
1071 fail:
1072        return PCI_CFG_SPACE_SIZE;
1073}
1074
1075int pci_cfg_space_size(struct pci_dev *dev)
1076{
1077        int pos;
1078        u32 status;
1079        u16 class;
1080
1081        class = dev->class >> 8;
1082        if (class == PCI_CLASS_BRIDGE_HOST)
1083                return pci_cfg_space_size_ext(dev);
1084
1085        pos = pci_pcie_cap(dev);
1086        if (!pos) {
1087                pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1088                if (!pos)
1089                        goto fail;
1090
1091                pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1092                if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1093                        goto fail;
1094        }
1095
1096        return pci_cfg_space_size_ext(dev);
1097
1098 fail:
1099        return PCI_CFG_SPACE_SIZE;
1100}
1101
1102static void pci_release_bus_bridge_dev(struct device *dev)
1103{
1104        kfree(dev);
1105}
1106
1107struct pci_dev *alloc_pci_dev(void)
1108{
1109        struct pci_dev *dev;
1110
1111        dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1112        if (!dev)
1113                return NULL;
1114
1115        INIT_LIST_HEAD(&dev->bus_list);
1116
1117        return dev;
1118}
1119EXPORT_SYMBOL(alloc_pci_dev);
1120
1121/*
1122 * Read the config data for a PCI device, sanity-check it
1123 * and fill in the dev structure...
1124 */
1125static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1126{
1127        struct pci_dev *dev;
1128        u32 l;
1129        int delay = 1;
1130
1131        if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1132                return NULL;
1133
1134        /* some broken boards return 0 or ~0 if a slot is empty: */
1135        if (l == 0xffffffff || l == 0x00000000 ||
1136            l == 0x0000ffff || l == 0xffff0000)
1137                return NULL;
1138
1139        /* Configuration request Retry Status */
1140        while (l == 0xffff0001) {
1141                msleep(delay);
1142                delay *= 2;
1143                if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1144                        return NULL;
1145                /* Card hasn't responded in 60 seconds?  Must be stuck. */
1146                if (delay > 60 * 1000) {
1147                        printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1148                                        "responding\n", pci_domain_nr(bus),
1149                                        bus->number, PCI_SLOT(devfn),
1150                                        PCI_FUNC(devfn));
1151                        return NULL;
1152                }
1153        }
1154
1155        dev = alloc_pci_dev();
1156        if (!dev)
1157                return NULL;
1158
1159        dev->bus = bus;
1160        dev->devfn = devfn;
1161        dev->vendor = l & 0xffff;
1162        dev->device = (l >> 16) & 0xffff;
1163
1164        pci_set_of_node(dev);
1165
1166        if (pci_setup_device(dev)) {
1167                kfree(dev);
1168                return NULL;
1169        }
1170
1171        return dev;
1172}
1173
1174static void pci_init_capabilities(struct pci_dev *dev)
1175{
1176        /* MSI/MSI-X list */
1177        pci_msi_init_pci_dev(dev);
1178
1179        /* Buffers for saving PCIe and PCI-X capabilities */
1180        pci_allocate_cap_save_buffers(dev);
1181
1182        /* Power Management */
1183        pci_pm_init(dev);
1184        platform_pci_wakeup_init(dev);
1185
1186        /* Vital Product Data */
1187        pci_vpd_pci22_init(dev);
1188
1189        /* Alternative Routing-ID Forwarding */
1190        pci_enable_ari(dev);
1191
1192        /* Single Root I/O Virtualization */
1193        pci_iov_init(dev);
1194
1195        /* Enable ACS P2P upstream forwarding */
1196        pci_enable_acs(dev);
1197}
1198
1199void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1200{
1201        device_initialize(&dev->dev);
1202        dev->dev.release = pci_release_dev;
1203        pci_dev_get(dev);
1204
1205        dev->dev.dma_mask = &dev->dma_mask;
1206        dev->dev.dma_parms = &dev->dma_parms;
1207        dev->dev.coherent_dma_mask = 0xffffffffull;
1208
1209        pci_set_dma_max_seg_size(dev, 65536);
1210        pci_set_dma_seg_boundary(dev, 0xffffffff);
1211
1212        /* Fix up broken headers */
1213        pci_fixup_device(pci_fixup_header, dev);
1214
1215        /* Clear the state_saved flag. */
1216        dev->state_saved = false;
1217
1218        /* Initialize various capabilities */
1219        pci_init_capabilities(dev);
1220
1221        /*
1222         * Add the device to our list of discovered devices
1223         * and the bus list for fixup functions, etc.
1224         */
1225        down_write(&pci_bus_sem);
1226        list_add_tail(&dev->bus_list, &bus->devices);
1227        up_write(&pci_bus_sem);
1228}
1229
1230struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1231{
1232        struct pci_dev *dev;
1233
1234        dev = pci_get_slot(bus, devfn);
1235        if (dev) {
1236                pci_dev_put(dev);
1237                return dev;
1238        }
1239
1240        dev = pci_scan_device(bus, devfn);
1241        if (!dev)
1242                return NULL;
1243
1244        pci_device_add(dev, bus);
1245
1246        return dev;
1247}
1248EXPORT_SYMBOL(pci_scan_single_device);
1249
1250static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1251{
1252        u16 cap;
1253        unsigned pos, next_fn;
1254
1255        if (!dev)
1256                return 0;
1257
1258        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1259        if (!pos)
1260                return 0;
1261        pci_read_config_word(dev, pos + 4, &cap);
1262        next_fn = cap >> 8;
1263        if (next_fn <= fn)
1264                return 0;
1265        return next_fn;
1266}
1267
1268static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1269{
1270        return (fn + 1) % 8;
1271}
1272
1273static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1274{
1275        return 0;
1276}
1277
1278static int only_one_child(struct pci_bus *bus)
1279{
1280        struct pci_dev *parent = bus->self;
1281        if (!parent || !pci_is_pcie(parent))
1282                return 0;
1283        if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1284            parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1285                return 1;
1286        return 0;
1287}
1288
1289/**
1290 * pci_scan_slot - scan a PCI slot on a bus for devices.
1291 * @bus: PCI bus to scan
1292 * @devfn: slot number to scan (must have zero function.)
1293 *
1294 * Scan a PCI slot on the specified PCI bus for devices, adding
1295 * discovered devices to the @bus->devices list.  New devices
1296 * will not have is_added set.
1297 *
1298 * Returns the number of new devices found.
1299 */
1300int pci_scan_slot(struct pci_bus *bus, int devfn)
1301{
1302        unsigned fn, nr = 0;
1303        struct pci_dev *dev;
1304        unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1305
1306        if (only_one_child(bus) && (devfn > 0))
1307                return 0; /* Already scanned the entire slot */
1308
1309        dev = pci_scan_single_device(bus, devfn);
1310        if (!dev)
1311                return 0;
1312        if (!dev->is_added)
1313                nr++;
1314
1315        if (pci_ari_enabled(bus))
1316                next_fn = next_ari_fn;
1317        else if (dev->multifunction)
1318                next_fn = next_trad_fn;
1319
1320        for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1321                dev = pci_scan_single_device(bus, devfn + fn);
1322                if (dev) {
1323                        if (!dev->is_added)
1324                                nr++;
1325                        dev->multifunction = 1;
1326                }
1327        }
1328
1329        /* only one slot has pcie device */
1330        if (bus->self && nr)
1331                pcie_aspm_init_link_state(bus->self);
1332
1333        return nr;
1334}
1335
1336static int pcie_find_smpss(struct pci_dev *dev, void *data)
1337{
1338        u8 *smpss = data;
1339
1340        if (!pci_is_pcie(dev))
1341                return 0;
1342
1343        /* For PCIE hotplug enabled slots not connected directly to a
1344         * PCI-E root port, there can be problems when hotplugging
1345         * devices.  This is due to the possibility of hotplugging a
1346         * device into the fabric with a smaller MPS that the devices
1347         * currently running have configured.  Modifying the MPS on the
1348         * running devices could cause a fatal bus error due to an
1349         * incoming frame being larger than the newly configured MPS.
1350         * To work around this, the MPS for the entire fabric must be
1351         * set to the minimum size.  Any devices hotplugged into this
1352         * fabric will have the minimum MPS set.  If the PCI hotplug
1353         * slot is directly connected to the root port and there are not
1354         * other devices on the fabric (which seems to be the most
1355         * common case), then this is not an issue and MPS discovery
1356         * will occur as normal.
1357         */
1358        if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1359             (dev->bus->self &&
1360              dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
1361                *smpss = 0;
1362
1363        if (*smpss > dev->pcie_mpss)
1364                *smpss = dev->pcie_mpss;
1365
1366        return 0;
1367}
1368
1369static void pcie_write_mps(struct pci_dev *dev, int mps)
1370{
1371        int rc;
1372
1373        if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1374                mps = 128 << dev->pcie_mpss;
1375
1376                if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
1377                        /* For "Performance", the assumption is made that
1378                         * downstream communication will never be larger than
1379                         * the MRRS.  So, the MPS only needs to be configured
1380                         * for the upstream communication.  This being the case,
1381                         * walk from the top down and set the MPS of the child
1382                         * to that of the parent bus.
1383                         *
1384                         * Configure the device MPS with the smaller of the
1385                         * device MPSS or the bridge MPS (which is assumed to be
1386                         * properly configured at this point to the largest
1387                         * allowable MPS based on its parent bus).
1388                         */
1389                        mps = min(mps, pcie_get_mps(dev->bus->self));
1390        }
1391
1392        rc = pcie_set_mps(dev, mps);
1393        if (rc)
1394                dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1395}
1396
1397static void pcie_write_mrrs(struct pci_dev *dev)
1398{
1399        int rc, mrrs;
1400
1401        /* In the "safe" case, do not configure the MRRS.  There appear to be
1402         * issues with setting MRRS to 0 on a number of devices.
1403         */
1404        if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1405                return;
1406
1407        /* For Max performance, the MRRS must be set to the largest supported
1408         * value.  However, it cannot be configured larger than the MPS the
1409         * device or the bus can support.  This should already be properly
1410         * configured by a prior call to pcie_write_mps.
1411         */
1412        mrrs = pcie_get_mps(dev);
1413
1414        /* MRRS is a R/W register.  Invalid values can be written, but a
1415         * subsequent read will verify if the value is acceptable or not.
1416         * If the MRRS value provided is not acceptable (e.g., too large),
1417         * shrink the value until it is acceptable to the HW.
1418         */
1419        while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1420                rc = pcie_set_readrq(dev, mrrs);
1421                if (!rc)
1422                        break;
1423
1424                dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1425                mrrs /= 2;
1426        }
1427
1428        if (mrrs < 128)
1429                dev_err(&dev->dev, "MRRS was unable to be configured with a "
1430                        "safe value.  If problems are experienced, try running "
1431                        "with pci=pcie_bus_safe.\n");
1432}
1433
1434static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1435{
1436        int mps, orig_mps;
1437
1438        if (!pci_is_pcie(dev))
1439                return 0;
1440
1441        mps = 128 << *(u8 *)data;
1442        orig_mps = pcie_get_mps(dev);
1443
1444        pcie_write_mps(dev, mps);
1445        pcie_write_mrrs(dev);
1446
1447        dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1448                 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1449                 orig_mps, pcie_get_readrq(dev));
1450
1451        return 0;
1452}
1453
1454/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1455 * parents then children fashion.  If this changes, then this code will not
1456 * work as designed.
1457 */
1458void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1459{
1460        u8 smpss;
1461
1462        if (!pci_is_pcie(bus->self))
1463                return;
1464
1465        if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1466                return;
1467
1468        /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1469         * to be aware to the MPS of the destination.  To work around this,
1470         * simply force the MPS of the entire system to the smallest possible.
1471         */
1472        if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1473                smpss = 0;
1474
1475        if (pcie_bus_config == PCIE_BUS_SAFE) {
1476                smpss = mpss;
1477
1478                pcie_find_smpss(bus->self, &smpss);
1479                pci_walk_bus(bus, pcie_find_smpss, &smpss);
1480        }
1481
1482        pcie_bus_configure_set(bus->self, &smpss);
1483        pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1484}
1485EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1486
1487unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1488{
1489        unsigned int devfn, pass, max = bus->secondary;
1490        struct pci_dev *dev;
1491
1492        dev_dbg(&bus->dev, "scanning bus\n");
1493
1494        /* Go find them, Rover! */
1495        for (devfn = 0; devfn < 0x100; devfn += 8)
1496                pci_scan_slot(bus, devfn);
1497
1498        /* Reserve buses for SR-IOV capability. */
1499        max += pci_iov_bus_range(bus);
1500
1501        /*
1502         * After performing arch-dependent fixup of the bus, look behind
1503         * all PCI-to-PCI bridges on this bus.
1504         */
1505        if (!bus->is_added) {
1506                dev_dbg(&bus->dev, "fixups for bus\n");
1507                pcibios_fixup_bus(bus);
1508                if (pci_is_root_bus(bus))
1509                        bus->is_added = 1;
1510        }
1511
1512        for (pass=0; pass < 2; pass++)
1513                list_for_each_entry(dev, &bus->devices, bus_list) {
1514                        if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1515                            dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1516                                max = pci_scan_bridge(bus, dev, max, pass);
1517                }
1518
1519        /*
1520         * We've scanned the bus and so we know all about what's on
1521         * the other side of any bridges that may be on this bus plus
1522         * any devices.
1523         *
1524         * Return how far we've got finding sub-buses.
1525         */
1526        dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1527        return max;
1528}
1529
1530struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1531                struct pci_ops *ops, void *sysdata, struct list_head *resources)
1532{
1533        int error, i;
1534        struct pci_bus *b, *b2;
1535        struct device *dev;
1536        struct pci_bus_resource *bus_res, *n;
1537        struct resource *res;
1538
1539        b = pci_alloc_bus();
1540        if (!b)
1541                return NULL;
1542
1543        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1544        if (!dev) {
1545                kfree(b);
1546                return NULL;
1547        }
1548
1549        b->sysdata = sysdata;
1550        b->ops = ops;
1551
1552        b2 = pci_find_bus(pci_domain_nr(b), bus);
1553        if (b2) {
1554                /* If we already got to this bus through a different bridge, ignore it */
1555                dev_dbg(&b2->dev, "bus already known\n");
1556                goto err_out;
1557        }
1558
1559        down_write(&pci_bus_sem);
1560        list_add_tail(&b->node, &pci_root_buses);
1561        up_write(&pci_bus_sem);
1562
1563        dev->parent = parent;
1564        dev->release = pci_release_bus_bridge_dev;
1565        dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1566        error = device_register(dev);
1567        if (error)
1568                goto dev_reg_err;
1569        b->bridge = get_device(dev);
1570        device_enable_async_suspend(b->bridge);
1571        pci_set_bus_of_node(b);
1572
1573        if (!parent)
1574                set_dev_node(b->bridge, pcibus_to_node(b));
1575
1576        b->dev.class = &pcibus_class;
1577        b->dev.parent = b->bridge;
1578        dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1579        error = device_register(&b->dev);
1580        if (error)
1581                goto class_dev_reg_err;
1582
1583        /* Create legacy_io and legacy_mem files for this bus */
1584        pci_create_legacy_files(b);
1585
1586        b->number = b->secondary = bus;
1587
1588        /* Add initial resources to the bus */
1589        list_for_each_entry_safe(bus_res, n, resources, list)
1590                list_move_tail(&bus_res->list, &b->resources);
1591
1592        if (parent)
1593                dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1594        else
1595                printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1596
1597        pci_bus_for_each_resource(b, res, i) {
1598                if (res)
1599                        dev_info(&b->dev, "root bus resource %pR\n", res);
1600        }
1601
1602        return b;
1603
1604class_dev_reg_err:
1605        device_unregister(dev);
1606dev_reg_err:
1607        down_write(&pci_bus_sem);
1608        list_del(&b->node);
1609        up_write(&pci_bus_sem);
1610err_out:
1611        kfree(dev);
1612        kfree(b);
1613        return NULL;
1614}
1615
1616struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
1617                struct pci_ops *ops, void *sysdata, struct list_head *resources)
1618{
1619        struct pci_bus *b;
1620
1621        b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1622        if (!b)
1623                return NULL;
1624
1625        b->subordinate = pci_scan_child_bus(b);
1626        pci_bus_add_devices(b);
1627        return b;
1628}
1629EXPORT_SYMBOL(pci_scan_root_bus);
1630
1631/* Deprecated; use pci_scan_root_bus() instead */
1632struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1633                int bus, struct pci_ops *ops, void *sysdata)
1634{
1635        LIST_HEAD(resources);
1636        struct pci_bus *b;
1637
1638        pci_add_resource(&resources, &ioport_resource);
1639        pci_add_resource(&resources, &iomem_resource);
1640        b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1641        if (b)
1642                b->subordinate = pci_scan_child_bus(b);
1643        else
1644                pci_free_resource_list(&resources);
1645        return b;
1646}
1647EXPORT_SYMBOL(pci_scan_bus_parented);
1648
1649struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
1650                                        void *sysdata)
1651{
1652        LIST_HEAD(resources);
1653        struct pci_bus *b;
1654
1655        pci_add_resource(&resources, &ioport_resource);
1656        pci_add_resource(&resources, &iomem_resource);
1657        b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1658        if (b) {
1659                b->subordinate = pci_scan_child_bus(b);
1660                pci_bus_add_devices(b);
1661        } else {
1662                pci_free_resource_list(&resources);
1663        }
1664        return b;
1665}
1666EXPORT_SYMBOL(pci_scan_bus);
1667
1668#ifdef CONFIG_HOTPLUG
1669/**
1670 * pci_rescan_bus - scan a PCI bus for devices.
1671 * @bus: PCI bus to scan
1672 *
1673 * Scan a PCI bus and child buses for new devices, adds them,
1674 * and enables them.
1675 *
1676 * Returns the max number of subordinate bus discovered.
1677 */
1678unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1679{
1680        unsigned int max;
1681        struct pci_dev *dev;
1682
1683        max = pci_scan_child_bus(bus);
1684
1685        down_read(&pci_bus_sem);
1686        list_for_each_entry(dev, &bus->devices, bus_list)
1687                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1688                    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1689                        if (dev->subordinate)
1690                                pci_bus_size_bridges(dev->subordinate);
1691        up_read(&pci_bus_sem);
1692
1693        pci_bus_assign_resources(bus);
1694        pci_enable_bridges(bus);
1695        pci_bus_add_devices(bus);
1696
1697        return max;
1698}
1699EXPORT_SYMBOL_GPL(pci_rescan_bus);
1700
1701EXPORT_SYMBOL(pci_add_new_bus);
1702EXPORT_SYMBOL(pci_scan_slot);
1703EXPORT_SYMBOL(pci_scan_bridge);
1704EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1705#endif
1706
1707static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1708{
1709        const struct pci_dev *a = to_pci_dev(d_a);
1710        const struct pci_dev *b = to_pci_dev(d_b);
1711
1712        if      (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1713        else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return  1;
1714
1715        if      (a->bus->number < b->bus->number) return -1;
1716        else if (a->bus->number > b->bus->number) return  1;
1717
1718        if      (a->devfn < b->devfn) return -1;
1719        else if (a->devfn > b->devfn) return  1;
1720
1721        return 0;
1722}
1723
1724void __init pci_sort_breadthfirst(void)
1725{
1726        bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1727}
1728