linux/drivers/pci/hotplug/shpchp.h
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   1/*
   2 * Standard Hot Plug Controller Driver
   3 *
   4 * Copyright (C) 1995,2001 Compaq Computer Corporation
   5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6 * Copyright (C) 2001 IBM
   7 * Copyright (C) 2003-2004 Intel Corporation
   8 *
   9 * All rights reserved.
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or (at
  14 * your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful, but
  17 * WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19 * NON INFRINGEMENT.  See the GNU General Public License for more
  20 * details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25 *
  26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27 *
  28 */
  29#ifndef _SHPCHP_H
  30#define _SHPCHP_H
  31
  32#include <linux/types.h>
  33#include <linux/pci.h>
  34#include <linux/pci_hotplug.h>
  35#include <linux/delay.h>
  36#include <linux/sched.h>        /* signal_pending(), struct timer_list */
  37#include <linux/mutex.h>
  38#include <linux/workqueue.h>
  39
  40#if !defined(MODULE)
  41        #define MY_NAME "shpchp"
  42#else
  43        #define MY_NAME THIS_MODULE->name
  44#endif
  45
  46extern bool shpchp_poll_mode;
  47extern int shpchp_poll_time;
  48extern bool shpchp_debug;
  49extern struct workqueue_struct *shpchp_wq;
  50extern struct workqueue_struct *shpchp_ordered_wq;
  51
  52#define dbg(format, arg...)                                             \
  53do {                                                                    \
  54        if (shpchp_debug)                                               \
  55                printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg);     \
  56} while (0)
  57#define err(format, arg...)                                             \
  58        printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
  59#define info(format, arg...)                                            \
  60        printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
  61#define warn(format, arg...)                                            \
  62        printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
  63
  64#define ctrl_dbg(ctrl, format, arg...)                                  \
  65        do {                                                            \
  66                if (shpchp_debug)                                       \
  67                        dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev,     \
  68                                        format, ## arg);                \
  69        } while (0)
  70#define ctrl_err(ctrl, format, arg...)                                  \
  71        dev_err(&ctrl->pci_dev->dev, format, ## arg)
  72#define ctrl_info(ctrl, format, arg...)                                 \
  73        dev_info(&ctrl->pci_dev->dev, format, ## arg)
  74#define ctrl_warn(ctrl, format, arg...)                                 \
  75        dev_warn(&ctrl->pci_dev->dev, format, ## arg)
  76
  77
  78#define SLOT_NAME_SIZE 10
  79struct slot {
  80        u8 bus;
  81        u8 device;
  82        u16 status;
  83        u32 number;
  84        u8 is_a_board;
  85        u8 state;
  86        u8 presence_save;
  87        u8 pwr_save;
  88        struct controller *ctrl;
  89        struct hpc_ops *hpc_ops;
  90        struct hotplug_slot *hotplug_slot;
  91        struct list_head        slot_list;
  92        struct delayed_work work;       /* work for button event */
  93        struct mutex lock;
  94        u8 hp_slot;
  95};
  96
  97struct event_info {
  98        u32 event_type;
  99        struct slot *p_slot;
 100        struct work_struct work;
 101};
 102
 103struct controller {
 104        struct mutex crit_sect;         /* critical section mutex */
 105        struct mutex cmd_lock;          /* command lock */
 106        int num_slots;                  /* Number of slots on ctlr */
 107        int slot_num_inc;               /* 1 or -1 */
 108        struct pci_dev *pci_dev;
 109        struct list_head slot_list;
 110        struct hpc_ops *hpc_ops;
 111        wait_queue_head_t queue;        /* sleep & wake process */
 112        u8 slot_device_offset;
 113        u32 pcix_misc2_reg;     /* for amd pogo errata */
 114        u32 first_slot;         /* First physical slot number */
 115        u32 cap_offset;
 116        unsigned long mmio_base;
 117        unsigned long mmio_size;
 118        void __iomem *creg;
 119        struct timer_list poll_timer;
 120};
 121
 122/* Define AMD SHPC ID  */
 123#define PCI_DEVICE_ID_AMD_GOLAM_7450    0x7450
 124#define PCI_DEVICE_ID_AMD_POGO_7458     0x7458
 125
 126/* AMD PCI-X bridge registers */
 127#define PCIX_MEM_BASE_LIMIT_OFFSET      0x1C
 128#define PCIX_MISCII_OFFSET              0x48
 129#define PCIX_MISC_BRIDGE_ERRORS_OFFSET  0x80
 130
 131/* AMD PCIX_MISCII masks and offsets */
 132#define PERRNONFATALENABLE_MASK         0x00040000
 133#define PERRFATALENABLE_MASK            0x00080000
 134#define PERRFLOODENABLE_MASK            0x00100000
 135#define SERRNONFATALENABLE_MASK         0x00200000
 136#define SERRFATALENABLE_MASK            0x00400000
 137
 138/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
 139#define PERR_OBSERVED_MASK              0x00000001
 140
 141/* AMD PCIX_MEM_BASE_LIMIT masks */
 142#define RSE_MASK                        0x40000000
 143
 144#define INT_BUTTON_IGNORE               0
 145#define INT_PRESENCE_ON                 1
 146#define INT_PRESENCE_OFF                2
 147#define INT_SWITCH_CLOSE                3
 148#define INT_SWITCH_OPEN                 4
 149#define INT_POWER_FAULT                 5
 150#define INT_POWER_FAULT_CLEAR           6
 151#define INT_BUTTON_PRESS                7
 152#define INT_BUTTON_RELEASE              8
 153#define INT_BUTTON_CANCEL               9
 154
 155#define STATIC_STATE                    0
 156#define BLINKINGON_STATE                1
 157#define BLINKINGOFF_STATE               2
 158#define POWERON_STATE                   3
 159#define POWEROFF_STATE                  4
 160
 161/* Error messages */
 162#define INTERLOCK_OPEN                  0x00000002
 163#define ADD_NOT_SUPPORTED               0x00000003
 164#define CARD_FUNCTIONING                0x00000005
 165#define ADAPTER_NOT_SAME                0x00000006
 166#define NO_ADAPTER_PRESENT              0x00000009
 167#define NOT_ENOUGH_RESOURCES            0x0000000B
 168#define DEVICE_TYPE_NOT_SUPPORTED       0x0000000C
 169#define WRONG_BUS_FREQUENCY             0x0000000D
 170#define POWER_FAILURE                   0x0000000E
 171
 172extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
 173extern void shpchp_remove_ctrl_files(struct controller *ctrl);
 174extern int shpchp_sysfs_enable_slot(struct slot *slot);
 175extern int shpchp_sysfs_disable_slot(struct slot *slot);
 176extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
 177extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
 178extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
 179extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
 180extern int shpchp_configure_device(struct slot *p_slot);
 181extern int shpchp_unconfigure_device(struct slot *p_slot);
 182extern void cleanup_slots(struct controller *ctrl);
 183extern void shpchp_queue_pushbutton_work(struct work_struct *work);
 184extern int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
 185
 186static inline const char *slot_name(struct slot *slot)
 187{
 188        return hotplug_slot_name(slot->hotplug_slot);
 189}
 190
 191#ifdef CONFIG_ACPI
 192#include <linux/pci-acpi.h>
 193static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
 194{
 195        u32 flags = OSC_SHPC_NATIVE_HP_CONTROL;
 196        return acpi_get_hp_hw_control_from_firmware(dev, flags);
 197}
 198#else
 199#define get_hp_hw_control_from_firmware(dev) (0)
 200#endif
 201
 202struct ctrl_reg {
 203        volatile u32 base_offset;
 204        volatile u32 slot_avail1;
 205        volatile u32 slot_avail2;
 206        volatile u32 slot_config;
 207        volatile u16 sec_bus_config;
 208        volatile u8  msi_ctrl;
 209        volatile u8  prog_interface;
 210        volatile u16 cmd;
 211        volatile u16 cmd_status;
 212        volatile u32 intr_loc;
 213        volatile u32 serr_loc;
 214        volatile u32 serr_intr_enable;
 215        volatile u32 slot1;
 216} __attribute__ ((packed));
 217
 218/* offsets to the controller registers based on the above structure layout */
 219enum ctrl_offsets {
 220        BASE_OFFSET      = offsetof(struct ctrl_reg, base_offset),
 221        SLOT_AVAIL1      = offsetof(struct ctrl_reg, slot_avail1),
 222        SLOT_AVAIL2      = offsetof(struct ctrl_reg, slot_avail2),
 223        SLOT_CONFIG      = offsetof(struct ctrl_reg, slot_config),
 224        SEC_BUS_CONFIG   = offsetof(struct ctrl_reg, sec_bus_config),
 225        MSI_CTRL         = offsetof(struct ctrl_reg, msi_ctrl),
 226        PROG_INTERFACE   = offsetof(struct ctrl_reg, prog_interface),
 227        CMD              = offsetof(struct ctrl_reg, cmd),
 228        CMD_STATUS       = offsetof(struct ctrl_reg, cmd_status),
 229        INTR_LOC         = offsetof(struct ctrl_reg, intr_loc),
 230        SERR_LOC         = offsetof(struct ctrl_reg, serr_loc),
 231        SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
 232        SLOT1            = offsetof(struct ctrl_reg, slot1),
 233};
 234
 235static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
 236{
 237        return hotplug_slot->private;
 238}
 239
 240static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
 241{
 242        struct slot *slot;
 243
 244        list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
 245                if (slot->device == device)
 246                        return slot;
 247        }
 248
 249        ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
 250        return NULL;
 251}
 252
 253static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
 254{
 255        u32 pcix_misc2_temp;
 256
 257        /* save MiscII register */
 258        pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
 259
 260        p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
 261
 262        /* clear SERR/PERR enable bits */
 263        pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 264        pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 265        pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 266        pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 267        pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 268        pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 269}
 270
 271static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
 272{
 273        u32 pcix_misc2_temp;
 274        u32 pcix_bridge_errors_reg;
 275        u32 pcix_mem_base_reg;
 276        u8  perr_set;
 277        u8  rse_set;
 278
 279        /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
 280        pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
 281        perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
 282        if (perr_set) {
 283                ctrl_dbg(p_slot->ctrl,
 284                         "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
 285                         perr_set);
 286
 287                pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
 288        }
 289
 290        /* write-one-to-clear Memory_Base_Limit[ RSE ] */
 291        pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
 292        rse_set = pcix_mem_base_reg & RSE_MASK;
 293        if (rse_set) {
 294                ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
 295
 296                pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
 297        }
 298        /* restore MiscII register */
 299        pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
 300
 301        if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
 302                pcix_misc2_temp |= SERRFATALENABLE_MASK;
 303        else
 304                pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 305
 306        if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
 307                pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
 308        else
 309                pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 310
 311        if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
 312                pcix_misc2_temp |= PERRFLOODENABLE_MASK;
 313        else
 314                pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 315
 316        if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
 317                pcix_misc2_temp |= PERRFATALENABLE_MASK;
 318        else
 319                pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 320
 321        if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
 322                pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
 323        else
 324                pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 325        pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 326}
 327
 328struct hpc_ops {
 329        int (*power_on_slot)(struct slot *slot);
 330        int (*slot_enable)(struct slot *slot);
 331        int (*slot_disable)(struct slot *slot);
 332        int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
 333        int (*get_power_status)(struct slot *slot, u8 *status);
 334        int (*get_attention_status)(struct slot *slot, u8 *status);
 335        int (*set_attention_status)(struct slot *slot, u8 status);
 336        int (*get_latch_status)(struct slot *slot, u8 *status);
 337        int (*get_adapter_status)(struct slot *slot, u8 *status);
 338        int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
 339        int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
 340        int (*get_prog_int)(struct slot *slot, u8 *prog_int);
 341        int (*query_power_fault)(struct slot *slot);
 342        void (*green_led_on)(struct slot *slot);
 343        void (*green_led_off)(struct slot *slot);
 344        void (*green_led_blink)(struct slot *slot);
 345        void (*release_ctlr)(struct controller *ctrl);
 346        int (*check_cmd_status)(struct controller *ctrl);
 347};
 348
 349#endif                          /* _SHPCHP_H */
 350