linux/drivers/gpio/gpio-pch.c
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   1/*
   2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; version 2 of the License.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program; if not, write to the Free Software
  15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  16 */
  17#include <linux/module.h>
  18#include <linux/kernel.h>
  19#include <linux/pci.h>
  20#include <linux/gpio.h>
  21#include <linux/interrupt.h>
  22#include <linux/irq.h>
  23
  24#define PCH_EDGE_FALLING        0
  25#define PCH_EDGE_RISING         BIT(0)
  26#define PCH_LEVEL_L             BIT(1)
  27#define PCH_LEVEL_H             (BIT(0) | BIT(1))
  28#define PCH_EDGE_BOTH           BIT(2)
  29#define PCH_IM_MASK             (BIT(0) | BIT(1) | BIT(2))
  30
  31#define PCH_IRQ_BASE            24
  32
  33struct pch_regs {
  34        u32     ien;
  35        u32     istatus;
  36        u32     idisp;
  37        u32     iclr;
  38        u32     imask;
  39        u32     imaskclr;
  40        u32     po;
  41        u32     pi;
  42        u32     pm;
  43        u32     im0;
  44        u32     im1;
  45        u32     reserved[3];
  46        u32     gpio_use_sel;
  47        u32     reset;
  48};
  49
  50enum pch_type_t {
  51        INTEL_EG20T_PCH,
  52        OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
  53        OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
  54};
  55
  56/* Specifies number of GPIO PINS */
  57static int gpio_pins[] = {
  58        [INTEL_EG20T_PCH] = 12,
  59        [OKISEMI_ML7223m_IOH] = 8,
  60        [OKISEMI_ML7223n_IOH] = 8,
  61};
  62
  63/**
  64 * struct pch_gpio_reg_data - The register store data.
  65 * @ien_reg:    To store contents of IEN register.
  66 * @imask_reg:  To store contents of IMASK register.
  67 * @po_reg:     To store contents of PO register.
  68 * @pm_reg:     To store contents of PM register.
  69 * @im0_reg:    To store contents of IM0 register.
  70 * @im1_reg:    To store contents of IM1 register.
  71 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
  72 *                     (Only ML7223 Bus-n)
  73 */
  74struct pch_gpio_reg_data {
  75        u32 ien_reg;
  76        u32 imask_reg;
  77        u32 po_reg;
  78        u32 pm_reg;
  79        u32 im0_reg;
  80        u32 im1_reg;
  81        u32 gpio_use_sel_reg;
  82};
  83
  84/**
  85 * struct pch_gpio - GPIO private data structure.
  86 * @base:                       PCI base address of Memory mapped I/O register.
  87 * @reg:                        Memory mapped PCH GPIO register list.
  88 * @dev:                        Pointer to device structure.
  89 * @gpio:                       Data for GPIO infrastructure.
  90 * @pch_gpio_reg:               Memory mapped Register data is saved here
  91 *                              when suspend.
  92 * @lock:                       Used for register access protection
  93 * @irq_base:           Save base of IRQ number for interrupt
  94 * @ioh:                IOH ID
  95 * @spinlock:           Used for register access protection in
  96 *                              interrupt context pch_irq_mask,
  97 *                              pch_irq_unmask and pch_irq_type;
  98 */
  99struct pch_gpio {
 100        void __iomem *base;
 101        struct pch_regs __iomem *reg;
 102        struct device *dev;
 103        struct gpio_chip gpio;
 104        struct pch_gpio_reg_data pch_gpio_reg;
 105        struct mutex lock;
 106        int irq_base;
 107        enum pch_type_t ioh;
 108        spinlock_t spinlock;
 109};
 110
 111static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
 112{
 113        u32 reg_val;
 114        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 115
 116        mutex_lock(&chip->lock);
 117        reg_val = ioread32(&chip->reg->po);
 118        if (val)
 119                reg_val |= (1 << nr);
 120        else
 121                reg_val &= ~(1 << nr);
 122
 123        iowrite32(reg_val, &chip->reg->po);
 124        mutex_unlock(&chip->lock);
 125}
 126
 127static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
 128{
 129        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 130
 131        return ioread32(&chip->reg->pi) & (1 << nr);
 132}
 133
 134static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
 135                                     int val)
 136{
 137        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 138        u32 pm;
 139        u32 reg_val;
 140
 141        mutex_lock(&chip->lock);
 142        pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
 143        pm |= (1 << nr);
 144        iowrite32(pm, &chip->reg->pm);
 145
 146        reg_val = ioread32(&chip->reg->po);
 147        if (val)
 148                reg_val |= (1 << nr);
 149        else
 150                reg_val &= ~(1 << nr);
 151        iowrite32(reg_val, &chip->reg->po);
 152
 153        mutex_unlock(&chip->lock);
 154
 155        return 0;
 156}
 157
 158static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 159{
 160        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 161        u32 pm;
 162
 163        mutex_lock(&chip->lock);
 164        pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
 165        pm &= ~(1 << nr);
 166        iowrite32(pm, &chip->reg->pm);
 167        mutex_unlock(&chip->lock);
 168
 169        return 0;
 170}
 171
 172/*
 173 * Save register configuration and disable interrupts.
 174 */
 175static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
 176{
 177        chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
 178        chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
 179        chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
 180        chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
 181        chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
 182        if (chip->ioh == INTEL_EG20T_PCH)
 183                chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
 184        if (chip->ioh == OKISEMI_ML7223n_IOH)
 185                chip->pch_gpio_reg.gpio_use_sel_reg =\
 186                                            ioread32(&chip->reg->gpio_use_sel);
 187}
 188
 189/*
 190 * This function restores the register configuration of the GPIO device.
 191 */
 192static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
 193{
 194        iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
 195        iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
 196        /* to store contents of PO register */
 197        iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
 198        /* to store contents of PM register */
 199        iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
 200        iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
 201        if (chip->ioh == INTEL_EG20T_PCH)
 202                iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
 203        if (chip->ioh == OKISEMI_ML7223n_IOH)
 204                iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
 205                          &chip->reg->gpio_use_sel);
 206}
 207
 208static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
 209{
 210        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
 211        return chip->irq_base + offset;
 212}
 213
 214static void pch_gpio_setup(struct pch_gpio *chip)
 215{
 216        struct gpio_chip *gpio = &chip->gpio;
 217
 218        gpio->label = dev_name(chip->dev);
 219        gpio->owner = THIS_MODULE;
 220        gpio->direction_input = pch_gpio_direction_input;
 221        gpio->get = pch_gpio_get;
 222        gpio->direction_output = pch_gpio_direction_output;
 223        gpio->set = pch_gpio_set;
 224        gpio->dbg_show = NULL;
 225        gpio->base = -1;
 226        gpio->ngpio = gpio_pins[chip->ioh];
 227        gpio->can_sleep = 0;
 228        gpio->to_irq = pch_gpio_to_irq;
 229}
 230
 231static int pch_irq_type(struct irq_data *d, unsigned int type)
 232{
 233        u32 im;
 234        u32 __iomem *im_reg;
 235        u32 ien;
 236        u32 im_pos;
 237        int ch;
 238        unsigned long flags;
 239        u32 val;
 240        int irq = d->irq;
 241        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 242        struct pch_gpio *chip = gc->private;
 243
 244        ch = irq - chip->irq_base;
 245        if (irq <= chip->irq_base + 7) {
 246                im_reg = &chip->reg->im0;
 247                im_pos = ch;
 248        } else {
 249                im_reg = &chip->reg->im1;
 250                im_pos = ch - 8;
 251        }
 252        dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
 253                __func__, irq, type, ch, im_pos);
 254
 255        spin_lock_irqsave(&chip->spinlock, flags);
 256
 257        switch (type) {
 258        case IRQ_TYPE_EDGE_RISING:
 259                val = PCH_EDGE_RISING;
 260                break;
 261        case IRQ_TYPE_EDGE_FALLING:
 262                val = PCH_EDGE_FALLING;
 263                break;
 264        case IRQ_TYPE_EDGE_BOTH:
 265                val = PCH_EDGE_BOTH;
 266                break;
 267        case IRQ_TYPE_LEVEL_HIGH:
 268                val = PCH_LEVEL_H;
 269                break;
 270        case IRQ_TYPE_LEVEL_LOW:
 271                val = PCH_LEVEL_L;
 272                break;
 273        case IRQ_TYPE_PROBE:
 274                goto end;
 275        default:
 276                dev_warn(chip->dev, "%s: unknown type(%dd)",
 277                        __func__, type);
 278                goto end;
 279        }
 280
 281        /* Set interrupt mode */
 282        im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
 283        iowrite32(im | (val << (im_pos * 4)), im_reg);
 284
 285        /* iclr */
 286        iowrite32(BIT(ch), &chip->reg->iclr);
 287
 288        /* IMASKCLR */
 289        iowrite32(BIT(ch), &chip->reg->imaskclr);
 290
 291        /* Enable interrupt */
 292        ien = ioread32(&chip->reg->ien);
 293        iowrite32(ien | BIT(ch), &chip->reg->ien);
 294end:
 295        spin_unlock_irqrestore(&chip->spinlock, flags);
 296
 297        return 0;
 298}
 299
 300static void pch_irq_unmask(struct irq_data *d)
 301{
 302        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 303        struct pch_gpio *chip = gc->private;
 304
 305        iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
 306}
 307
 308static void pch_irq_mask(struct irq_data *d)
 309{
 310        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 311        struct pch_gpio *chip = gc->private;
 312
 313        iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
 314}
 315
 316static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
 317{
 318        struct pch_gpio *chip = dev_id;
 319        u32 reg_val = ioread32(&chip->reg->istatus);
 320        int i;
 321        int ret = IRQ_NONE;
 322
 323        for (i = 0; i < gpio_pins[chip->ioh]; i++) {
 324                if (reg_val & BIT(i)) {
 325                        dev_dbg(chip->dev, "%s:[%d]:irq=%d  status=0x%x\n",
 326                                __func__, i, irq, reg_val);
 327                        iowrite32(BIT(i), &chip->reg->iclr);
 328                        generic_handle_irq(chip->irq_base + i);
 329                        ret = IRQ_HANDLED;
 330                }
 331        }
 332        return ret;
 333}
 334
 335static __devinit void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
 336                                unsigned int irq_start, unsigned int num)
 337{
 338        struct irq_chip_generic *gc;
 339        struct irq_chip_type *ct;
 340
 341        gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
 342                                    handle_simple_irq);
 343        gc->private = chip;
 344        ct = gc->chip_types;
 345
 346        ct->chip.irq_mask = pch_irq_mask;
 347        ct->chip.irq_unmask = pch_irq_unmask;
 348        ct->chip.irq_set_type = pch_irq_type;
 349
 350        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 351                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 352}
 353
 354static int __devinit pch_gpio_probe(struct pci_dev *pdev,
 355                                    const struct pci_device_id *id)
 356{
 357        s32 ret;
 358        struct pch_gpio *chip;
 359        int irq_base;
 360
 361        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
 362        if (chip == NULL)
 363                return -ENOMEM;
 364
 365        chip->dev = &pdev->dev;
 366        ret = pci_enable_device(pdev);
 367        if (ret) {
 368                dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
 369                goto err_pci_enable;
 370        }
 371
 372        ret = pci_request_regions(pdev, KBUILD_MODNAME);
 373        if (ret) {
 374                dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
 375                goto err_request_regions;
 376        }
 377
 378        chip->base = pci_iomap(pdev, 1, 0);
 379        if (!chip->base) {
 380                dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
 381                ret = -ENOMEM;
 382                goto err_iomap;
 383        }
 384
 385        if (pdev->device == 0x8803)
 386                chip->ioh = INTEL_EG20T_PCH;
 387        else if (pdev->device == 0x8014)
 388                chip->ioh = OKISEMI_ML7223m_IOH;
 389        else if (pdev->device == 0x8043)
 390                chip->ioh = OKISEMI_ML7223n_IOH;
 391
 392        chip->reg = chip->base;
 393        pci_set_drvdata(pdev, chip);
 394        mutex_init(&chip->lock);
 395        spin_lock_init(&chip->spinlock);
 396        pch_gpio_setup(chip);
 397        ret = gpiochip_add(&chip->gpio);
 398        if (ret) {
 399                dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
 400                goto err_gpiochip_add;
 401        }
 402
 403        irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
 404        if (irq_base < 0) {
 405                dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
 406                chip->irq_base = -1;
 407                goto end;
 408        }
 409        chip->irq_base = irq_base;
 410
 411        ret = request_irq(pdev->irq, pch_gpio_handler,
 412                             IRQF_SHARED, KBUILD_MODNAME, chip);
 413        if (ret != 0) {
 414                dev_err(&pdev->dev,
 415                        "%s request_irq failed\n", __func__);
 416                goto err_request_irq;
 417        }
 418
 419        pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
 420
 421        /* Initialize interrupt ien register */
 422        iowrite32(0, &chip->reg->ien);
 423end:
 424        return 0;
 425
 426err_request_irq:
 427        irq_free_descs(irq_base, gpio_pins[chip->ioh]);
 428
 429        ret = gpiochip_remove(&chip->gpio);
 430        if (ret)
 431                dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
 432
 433err_gpiochip_add:
 434        pci_iounmap(pdev, chip->base);
 435
 436err_iomap:
 437        pci_release_regions(pdev);
 438
 439err_request_regions:
 440        pci_disable_device(pdev);
 441
 442err_pci_enable:
 443        kfree(chip);
 444        dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
 445        return ret;
 446}
 447
 448static void __devexit pch_gpio_remove(struct pci_dev *pdev)
 449{
 450        int err;
 451        struct pch_gpio *chip = pci_get_drvdata(pdev);
 452
 453        if (chip->irq_base != -1) {
 454                free_irq(pdev->irq, chip);
 455
 456                irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
 457        }
 458
 459        err = gpiochip_remove(&chip->gpio);
 460        if (err)
 461                dev_err(&pdev->dev, "Failed gpiochip_remove\n");
 462
 463        pci_iounmap(pdev, chip->base);
 464        pci_release_regions(pdev);
 465        pci_disable_device(pdev);
 466        kfree(chip);
 467}
 468
 469#ifdef CONFIG_PM
 470static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
 471{
 472        s32 ret;
 473        struct pch_gpio *chip = pci_get_drvdata(pdev);
 474        unsigned long flags;
 475
 476        spin_lock_irqsave(&chip->spinlock, flags);
 477        pch_gpio_save_reg_conf(chip);
 478        spin_unlock_irqrestore(&chip->spinlock, flags);
 479
 480        ret = pci_save_state(pdev);
 481        if (ret) {
 482                dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
 483                return ret;
 484        }
 485        pci_disable_device(pdev);
 486        pci_set_power_state(pdev, PCI_D0);
 487        ret = pci_enable_wake(pdev, PCI_D0, 1);
 488        if (ret)
 489                dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
 490
 491        return 0;
 492}
 493
 494static int pch_gpio_resume(struct pci_dev *pdev)
 495{
 496        s32 ret;
 497        struct pch_gpio *chip = pci_get_drvdata(pdev);
 498        unsigned long flags;
 499
 500        ret = pci_enable_wake(pdev, PCI_D0, 0);
 501
 502        pci_set_power_state(pdev, PCI_D0);
 503        ret = pci_enable_device(pdev);
 504        if (ret) {
 505                dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
 506                return ret;
 507        }
 508        pci_restore_state(pdev);
 509
 510        spin_lock_irqsave(&chip->spinlock, flags);
 511        iowrite32(0x01, &chip->reg->reset);
 512        iowrite32(0x00, &chip->reg->reset);
 513        pch_gpio_restore_reg_conf(chip);
 514        spin_unlock_irqrestore(&chip->spinlock, flags);
 515
 516        return 0;
 517}
 518#else
 519#define pch_gpio_suspend NULL
 520#define pch_gpio_resume NULL
 521#endif
 522
 523#define PCI_VENDOR_ID_ROHM             0x10DB
 524static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
 525        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
 526        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
 527        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
 528        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
 529        { 0, }
 530};
 531MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
 532
 533static struct pci_driver pch_gpio_driver = {
 534        .name = "pch_gpio",
 535        .id_table = pch_gpio_pcidev_id,
 536        .probe = pch_gpio_probe,
 537        .remove = __devexit_p(pch_gpio_remove),
 538        .suspend = pch_gpio_suspend,
 539        .resume = pch_gpio_resume
 540};
 541
 542static int __init pch_gpio_pci_init(void)
 543{
 544        return pci_register_driver(&pch_gpio_driver);
 545}
 546module_init(pch_gpio_pci_init);
 547
 548static void __exit pch_gpio_pci_exit(void)
 549{
 550        pci_unregister_driver(&pch_gpio_driver);
 551}
 552module_exit(pch_gpio_pci_exit);
 553
 554MODULE_DESCRIPTION("PCH GPIO PCI Driver");
 555MODULE_LICENSE("GPL");
 556