linux/drivers/gpio/gpio-mxc.c
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   1/*
   2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4 *
   5 * Based on code from Freescale,
   6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License
  10 * as published by the Free Software Foundation; either version 2
  11 * of the License, or (at your option) any later version.
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20 */
  21
  22#include <linux/init.h>
  23#include <linux/interrupt.h>
  24#include <linux/io.h>
  25#include <linux/irq.h>
  26#include <linux/gpio.h>
  27#include <linux/platform_device.h>
  28#include <linux/slab.h>
  29#include <linux/basic_mmio_gpio.h>
  30#include <linux/of.h>
  31#include <linux/of_device.h>
  32#include <linux/module.h>
  33#include <asm-generic/bug.h>
  34#include <asm/mach/irq.h>
  35
  36#define irq_to_gpio(irq)        ((irq) - MXC_GPIO_IRQ_START)
  37
  38enum mxc_gpio_hwtype {
  39        IMX1_GPIO,      /* runs on i.mx1 */
  40        IMX21_GPIO,     /* runs on i.mx21 and i.mx27 */
  41        IMX31_GPIO,     /* runs on all other i.mx */
  42};
  43
  44/* device type dependent stuff */
  45struct mxc_gpio_hwdata {
  46        unsigned dr_reg;
  47        unsigned gdir_reg;
  48        unsigned psr_reg;
  49        unsigned icr1_reg;
  50        unsigned icr2_reg;
  51        unsigned imr_reg;
  52        unsigned isr_reg;
  53        unsigned low_level;
  54        unsigned high_level;
  55        unsigned rise_edge;
  56        unsigned fall_edge;
  57};
  58
  59struct mxc_gpio_port {
  60        struct list_head node;
  61        void __iomem *base;
  62        int irq;
  63        int irq_high;
  64        int virtual_irq_start;
  65        struct bgpio_chip bgc;
  66        u32 both_edges;
  67};
  68
  69static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
  70        .dr_reg         = 0x1c,
  71        .gdir_reg       = 0x00,
  72        .psr_reg        = 0x24,
  73        .icr1_reg       = 0x28,
  74        .icr2_reg       = 0x2c,
  75        .imr_reg        = 0x30,
  76        .isr_reg        = 0x34,
  77        .low_level      = 0x03,
  78        .high_level     = 0x02,
  79        .rise_edge      = 0x00,
  80        .fall_edge      = 0x01,
  81};
  82
  83static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
  84        .dr_reg         = 0x00,
  85        .gdir_reg       = 0x04,
  86        .psr_reg        = 0x08,
  87        .icr1_reg       = 0x0c,
  88        .icr2_reg       = 0x10,
  89        .imr_reg        = 0x14,
  90        .isr_reg        = 0x18,
  91        .low_level      = 0x00,
  92        .high_level     = 0x01,
  93        .rise_edge      = 0x02,
  94        .fall_edge      = 0x03,
  95};
  96
  97static enum mxc_gpio_hwtype mxc_gpio_hwtype;
  98static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
  99
 100#define GPIO_DR                 (mxc_gpio_hwdata->dr_reg)
 101#define GPIO_GDIR               (mxc_gpio_hwdata->gdir_reg)
 102#define GPIO_PSR                (mxc_gpio_hwdata->psr_reg)
 103#define GPIO_ICR1               (mxc_gpio_hwdata->icr1_reg)
 104#define GPIO_ICR2               (mxc_gpio_hwdata->icr2_reg)
 105#define GPIO_IMR                (mxc_gpio_hwdata->imr_reg)
 106#define GPIO_ISR                (mxc_gpio_hwdata->isr_reg)
 107
 108#define GPIO_INT_LOW_LEV        (mxc_gpio_hwdata->low_level)
 109#define GPIO_INT_HIGH_LEV       (mxc_gpio_hwdata->high_level)
 110#define GPIO_INT_RISE_EDGE      (mxc_gpio_hwdata->rise_edge)
 111#define GPIO_INT_FALL_EDGE      (mxc_gpio_hwdata->fall_edge)
 112#define GPIO_INT_NONE           0x4
 113
 114static struct platform_device_id mxc_gpio_devtype[] = {
 115        {
 116                .name = "imx1-gpio",
 117                .driver_data = IMX1_GPIO,
 118        }, {
 119                .name = "imx21-gpio",
 120                .driver_data = IMX21_GPIO,
 121        }, {
 122                .name = "imx31-gpio",
 123                .driver_data = IMX31_GPIO,
 124        }, {
 125                /* sentinel */
 126        }
 127};
 128
 129static const struct of_device_id mxc_gpio_dt_ids[] = {
 130        { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
 131        { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
 132        { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
 133        { /* sentinel */ }
 134};
 135
 136/*
 137 * MX2 has one interrupt *for all* gpio ports. The list is used
 138 * to save the references to all ports, so that mx2_gpio_irq_handler
 139 * can walk through all interrupt status registers.
 140 */
 141static LIST_HEAD(mxc_gpio_ports);
 142
 143/* Note: This driver assumes 32 GPIOs are handled in one register */
 144
 145static int gpio_set_irq_type(struct irq_data *d, u32 type)
 146{
 147        u32 gpio = irq_to_gpio(d->irq);
 148        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 149        struct mxc_gpio_port *port = gc->private;
 150        u32 bit, val;
 151        int edge;
 152        void __iomem *reg = port->base;
 153
 154        port->both_edges &= ~(1 << (gpio & 31));
 155        switch (type) {
 156        case IRQ_TYPE_EDGE_RISING:
 157                edge = GPIO_INT_RISE_EDGE;
 158                break;
 159        case IRQ_TYPE_EDGE_FALLING:
 160                edge = GPIO_INT_FALL_EDGE;
 161                break;
 162        case IRQ_TYPE_EDGE_BOTH:
 163                val = gpio_get_value(gpio);
 164                if (val) {
 165                        edge = GPIO_INT_LOW_LEV;
 166                        pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
 167                } else {
 168                        edge = GPIO_INT_HIGH_LEV;
 169                        pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
 170                }
 171                port->both_edges |= 1 << (gpio & 31);
 172                break;
 173        case IRQ_TYPE_LEVEL_LOW:
 174                edge = GPIO_INT_LOW_LEV;
 175                break;
 176        case IRQ_TYPE_LEVEL_HIGH:
 177                edge = GPIO_INT_HIGH_LEV;
 178                break;
 179        default:
 180                return -EINVAL;
 181        }
 182
 183        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 184        bit = gpio & 0xf;
 185        val = readl(reg) & ~(0x3 << (bit << 1));
 186        writel(val | (edge << (bit << 1)), reg);
 187        writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
 188
 189        return 0;
 190}
 191
 192static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 193{
 194        void __iomem *reg = port->base;
 195        u32 bit, val;
 196        int edge;
 197
 198        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 199        bit = gpio & 0xf;
 200        val = readl(reg);
 201        edge = (val >> (bit << 1)) & 3;
 202        val &= ~(0x3 << (bit << 1));
 203        if (edge == GPIO_INT_HIGH_LEV) {
 204                edge = GPIO_INT_LOW_LEV;
 205                pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 206        } else if (edge == GPIO_INT_LOW_LEV) {
 207                edge = GPIO_INT_HIGH_LEV;
 208                pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 209        } else {
 210                pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 211                       gpio, edge);
 212                return;
 213        }
 214        writel(val | (edge << (bit << 1)), reg);
 215}
 216
 217/* handle 32 interrupts in one status register */
 218static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 219{
 220        u32 gpio_irq_no_base = port->virtual_irq_start;
 221
 222        while (irq_stat != 0) {
 223                int irqoffset = fls(irq_stat) - 1;
 224
 225                if (port->both_edges & (1 << irqoffset))
 226                        mxc_flip_edge(port, irqoffset);
 227
 228                generic_handle_irq(gpio_irq_no_base + irqoffset);
 229
 230                irq_stat &= ~(1 << irqoffset);
 231        }
 232}
 233
 234/* MX1 and MX3 has one interrupt *per* gpio port */
 235static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 236{
 237        u32 irq_stat;
 238        struct mxc_gpio_port *port = irq_get_handler_data(irq);
 239        struct irq_chip *chip = irq_get_chip(irq);
 240
 241        chained_irq_enter(chip, desc);
 242
 243        irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
 244
 245        mxc_gpio_irq_handler(port, irq_stat);
 246
 247        chained_irq_exit(chip, desc);
 248}
 249
 250/* MX2 has one interrupt *for all* gpio ports */
 251static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 252{
 253        u32 irq_msk, irq_stat;
 254        struct mxc_gpio_port *port;
 255
 256        /* walk through all interrupt status registers */
 257        list_for_each_entry(port, &mxc_gpio_ports, node) {
 258                irq_msk = readl(port->base + GPIO_IMR);
 259                if (!irq_msk)
 260                        continue;
 261
 262                irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
 263                if (irq_stat)
 264                        mxc_gpio_irq_handler(port, irq_stat);
 265        }
 266}
 267
 268/*
 269 * Set interrupt number "irq" in the GPIO as a wake-up source.
 270 * While system is running, all registered GPIO interrupts need to have
 271 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 272 * need to have wake-up enabled.
 273 * @param  irq          interrupt source number
 274 * @param  enable       enable as wake-up if equal to non-zero
 275 * @return       This function returns 0 on success.
 276 */
 277static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 278{
 279        u32 gpio = irq_to_gpio(d->irq);
 280        u32 gpio_idx = gpio & 0x1F;
 281        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 282        struct mxc_gpio_port *port = gc->private;
 283
 284        if (enable) {
 285                if (port->irq_high && (gpio_idx >= 16))
 286                        enable_irq_wake(port->irq_high);
 287                else
 288                        enable_irq_wake(port->irq);
 289        } else {
 290                if (port->irq_high && (gpio_idx >= 16))
 291                        disable_irq_wake(port->irq_high);
 292                else
 293                        disable_irq_wake(port->irq);
 294        }
 295
 296        return 0;
 297}
 298
 299static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
 300{
 301        struct irq_chip_generic *gc;
 302        struct irq_chip_type *ct;
 303
 304        gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
 305                                    port->base, handle_level_irq);
 306        gc->private = port;
 307
 308        ct = gc->chip_types;
 309        ct->chip.irq_ack = irq_gc_ack_set_bit;
 310        ct->chip.irq_mask = irq_gc_mask_clr_bit;
 311        ct->chip.irq_unmask = irq_gc_mask_set_bit;
 312        ct->chip.irq_set_type = gpio_set_irq_type;
 313        ct->chip.irq_set_wake = gpio_set_wake_irq;
 314        ct->regs.ack = GPIO_ISR;
 315        ct->regs.mask = GPIO_IMR;
 316
 317        irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 318                               IRQ_NOREQUEST, 0);
 319}
 320
 321static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
 322{
 323        const struct of_device_id *of_id =
 324                        of_match_device(mxc_gpio_dt_ids, &pdev->dev);
 325        enum mxc_gpio_hwtype hwtype;
 326
 327        if (of_id)
 328                pdev->id_entry = of_id->data;
 329        hwtype = pdev->id_entry->driver_data;
 330
 331        if (mxc_gpio_hwtype) {
 332                /*
 333                 * The driver works with a reasonable presupposition,
 334                 * that is all gpio ports must be the same type when
 335                 * running on one soc.
 336                 */
 337                BUG_ON(mxc_gpio_hwtype != hwtype);
 338                return;
 339        }
 340
 341        if (hwtype == IMX31_GPIO)
 342                mxc_gpio_hwdata = &imx31_gpio_hwdata;
 343        else
 344                mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
 345
 346        mxc_gpio_hwtype = hwtype;
 347}
 348
 349static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 350{
 351        struct bgpio_chip *bgc = to_bgpio_chip(gc);
 352        struct mxc_gpio_port *port =
 353                container_of(bgc, struct mxc_gpio_port, bgc);
 354
 355        return port->virtual_irq_start + offset;
 356}
 357
 358static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 359{
 360        struct device_node *np = pdev->dev.of_node;
 361        struct mxc_gpio_port *port;
 362        struct resource *iores;
 363        int err;
 364
 365        mxc_gpio_get_hw(pdev);
 366
 367        port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
 368        if (!port)
 369                return -ENOMEM;
 370
 371        iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 372        if (!iores) {
 373                err = -ENODEV;
 374                goto out_kfree;
 375        }
 376
 377        if (!request_mem_region(iores->start, resource_size(iores),
 378                                pdev->name)) {
 379                err = -EBUSY;
 380                goto out_kfree;
 381        }
 382
 383        port->base = ioremap(iores->start, resource_size(iores));
 384        if (!port->base) {
 385                err = -ENOMEM;
 386                goto out_release_mem;
 387        }
 388
 389        port->irq_high = platform_get_irq(pdev, 1);
 390        port->irq = platform_get_irq(pdev, 0);
 391        if (port->irq < 0) {
 392                err = -EINVAL;
 393                goto out_iounmap;
 394        }
 395
 396        /* disable the interrupt and clear the status */
 397        writel(0, port->base + GPIO_IMR);
 398        writel(~0, port->base + GPIO_ISR);
 399
 400        if (mxc_gpio_hwtype == IMX21_GPIO) {
 401                /* setup one handler for all GPIO interrupts */
 402                if (pdev->id == 0)
 403                        irq_set_chained_handler(port->irq,
 404                                                mx2_gpio_irq_handler);
 405        } else {
 406                /* setup one handler for each entry */
 407                irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
 408                irq_set_handler_data(port->irq, port);
 409                if (port->irq_high > 0) {
 410                        /* setup handler for GPIO 16 to 31 */
 411                        irq_set_chained_handler(port->irq_high,
 412                                                mx3_gpio_irq_handler);
 413                        irq_set_handler_data(port->irq_high, port);
 414                }
 415        }
 416
 417        err = bgpio_init(&port->bgc, &pdev->dev, 4,
 418                         port->base + GPIO_PSR,
 419                         port->base + GPIO_DR, NULL,
 420                         port->base + GPIO_GDIR, NULL, false);
 421        if (err)
 422                goto out_iounmap;
 423
 424        port->bgc.gc.to_irq = mxc_gpio_to_irq;
 425        port->bgc.gc.base = pdev->id * 32;
 426        port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
 427        port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
 428
 429        err = gpiochip_add(&port->bgc.gc);
 430        if (err)
 431                goto out_bgpio_remove;
 432
 433        /*
 434         * In dt case, we use gpio number range dynamically
 435         * allocated by gpio core.
 436         */
 437        port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
 438                                                             pdev->id * 32);
 439
 440        /* gpio-mxc can be a generic irq chip */
 441        mxc_gpio_init_gc(port);
 442
 443        list_add_tail(&port->node, &mxc_gpio_ports);
 444
 445        return 0;
 446
 447out_bgpio_remove:
 448        bgpio_remove(&port->bgc);
 449out_iounmap:
 450        iounmap(port->base);
 451out_release_mem:
 452        release_mem_region(iores->start, resource_size(iores));
 453out_kfree:
 454        kfree(port);
 455        dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 456        return err;
 457}
 458
 459static struct platform_driver mxc_gpio_driver = {
 460        .driver         = {
 461                .name   = "gpio-mxc",
 462                .owner  = THIS_MODULE,
 463                .of_match_table = mxc_gpio_dt_ids,
 464        },
 465        .probe          = mxc_gpio_probe,
 466        .id_table       = mxc_gpio_devtype,
 467};
 468
 469static int __init gpio_mxc_init(void)
 470{
 471        return platform_driver_register(&mxc_gpio_driver);
 472}
 473postcore_initcall(gpio_mxc_init);
 474
 475MODULE_AUTHOR("Freescale Semiconductor, "
 476              "Daniel Mack <danielncaiaq.de>, "
 477              "Juergen Beisert <kernel@pengutronix.de>");
 478MODULE_DESCRIPTION("Freescale MXC GPIO");
 479MODULE_LICENSE("GPL");
 480