linux/drivers/ata/ahci.c
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   1/*
   2 *  ahci.c - AHCI SATA support
   3 *
   4 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *  Copyright 2004-2005 Red Hat, Inc.
   9 *
  10 *
  11 *  This program is free software; you can redistribute it and/or modify
  12 *  it under the terms of the GNU General Public License as published by
  13 *  the Free Software Foundation; either version 2, or (at your option)
  14 *  any later version.
  15 *
  16 *  This program is distributed in the hope that it will be useful,
  17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *  GNU General Public License for more details.
  20 *
  21 *  You should have received a copy of the GNU General Public License
  22 *  along with this program; see the file COPYING.  If not, write to
  23 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24 *
  25 *
  26 * libata documentation is available via 'make {ps|pdf}docs',
  27 * as Documentation/DocBook/libata.*
  28 *
  29 * AHCI hardware documentation:
  30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32 *
  33 */
  34
  35#include <linux/kernel.h>
  36#include <linux/module.h>
  37#include <linux/pci.h>
  38#include <linux/init.h>
  39#include <linux/blkdev.h>
  40#include <linux/delay.h>
  41#include <linux/interrupt.h>
  42#include <linux/dma-mapping.h>
  43#include <linux/device.h>
  44#include <linux/dmi.h>
  45#include <linux/gfp.h>
  46#include <scsi/scsi_host.h>
  47#include <scsi/scsi_cmnd.h>
  48#include <linux/libata.h>
  49#include "ahci.h"
  50
  51#define DRV_NAME        "ahci"
  52#define DRV_VERSION     "3.0"
  53
  54enum {
  55        AHCI_PCI_BAR_STA2X11    = 0,
  56        AHCI_PCI_BAR_STANDARD   = 5,
  57};
  58
  59enum board_ids {
  60        /* board IDs by feature in alphabetical order */
  61        board_ahci,
  62        board_ahci_ign_iferr,
  63        board_ahci_nosntf,
  64        board_ahci_yes_fbs,
  65
  66        /* board IDs for specific chipsets in alphabetical order */
  67        board_ahci_mcp65,
  68        board_ahci_mcp77,
  69        board_ahci_mcp89,
  70        board_ahci_mv,
  71        board_ahci_sb600,
  72        board_ahci_sb700,       /* for SB700 and SB800 */
  73        board_ahci_vt8251,
  74
  75        /* aliases */
  76        board_ahci_mcp_linux    = board_ahci_mcp65,
  77        board_ahci_mcp67        = board_ahci_mcp65,
  78        board_ahci_mcp73        = board_ahci_mcp65,
  79        board_ahci_mcp79        = board_ahci_mcp77,
  80};
  81
  82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  84                                 unsigned long deadline);
  85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  86                                unsigned long deadline);
  87#ifdef CONFIG_PM
  88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  89static int ahci_pci_device_resume(struct pci_dev *pdev);
  90#endif
  91
  92static struct scsi_host_template ahci_sht = {
  93        AHCI_SHT("ahci"),
  94};
  95
  96static struct ata_port_operations ahci_vt8251_ops = {
  97        .inherits               = &ahci_ops,
  98        .hardreset              = ahci_vt8251_hardreset,
  99};
 100
 101static struct ata_port_operations ahci_p5wdh_ops = {
 102        .inherits               = &ahci_ops,
 103        .hardreset              = ahci_p5wdh_hardreset,
 104};
 105
 106static const struct ata_port_info ahci_port_info[] = {
 107        /* by features */
 108        [board_ahci] =
 109        {
 110                .flags          = AHCI_FLAG_COMMON,
 111                .pio_mask       = ATA_PIO4,
 112                .udma_mask      = ATA_UDMA6,
 113                .port_ops       = &ahci_ops,
 114        },
 115        [board_ahci_ign_iferr] =
 116        {
 117                AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
 118                .flags          = AHCI_FLAG_COMMON,
 119                .pio_mask       = ATA_PIO4,
 120                .udma_mask      = ATA_UDMA6,
 121                .port_ops       = &ahci_ops,
 122        },
 123        [board_ahci_nosntf] =
 124        {
 125                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
 126                .flags          = AHCI_FLAG_COMMON,
 127                .pio_mask       = ATA_PIO4,
 128                .udma_mask      = ATA_UDMA6,
 129                .port_ops       = &ahci_ops,
 130        },
 131        [board_ahci_yes_fbs] =
 132        {
 133                AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
 134                .flags          = AHCI_FLAG_COMMON,
 135                .pio_mask       = ATA_PIO4,
 136                .udma_mask      = ATA_UDMA6,
 137                .port_ops       = &ahci_ops,
 138        },
 139        /* by chipsets */
 140        [board_ahci_mcp65] =
 141        {
 142                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 143                                 AHCI_HFLAG_YES_NCQ),
 144                .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 145                .pio_mask       = ATA_PIO4,
 146                .udma_mask      = ATA_UDMA6,
 147                .port_ops       = &ahci_ops,
 148        },
 149        [board_ahci_mcp77] =
 150        {
 151                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 152                .flags          = AHCI_FLAG_COMMON,
 153                .pio_mask       = ATA_PIO4,
 154                .udma_mask      = ATA_UDMA6,
 155                .port_ops       = &ahci_ops,
 156        },
 157        [board_ahci_mcp89] =
 158        {
 159                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
 160                .flags          = AHCI_FLAG_COMMON,
 161                .pio_mask       = ATA_PIO4,
 162                .udma_mask      = ATA_UDMA6,
 163                .port_ops       = &ahci_ops,
 164        },
 165        [board_ahci_mv] =
 166        {
 167                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 168                                 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 169                .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
 170                .pio_mask       = ATA_PIO4,
 171                .udma_mask      = ATA_UDMA6,
 172                .port_ops       = &ahci_ops,
 173        },
 174        [board_ahci_sb600] =
 175        {
 176                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
 177                                 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 178                                 AHCI_HFLAG_32BIT_ONLY),
 179                .flags          = AHCI_FLAG_COMMON,
 180                .pio_mask       = ATA_PIO4,
 181                .udma_mask      = ATA_UDMA6,
 182                .port_ops       = &ahci_pmp_retry_srst_ops,
 183        },
 184        [board_ahci_sb700] =    /* for SB700 and SB800 */
 185        {
 186                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
 187                .flags          = AHCI_FLAG_COMMON,
 188                .pio_mask       = ATA_PIO4,
 189                .udma_mask      = ATA_UDMA6,
 190                .port_ops       = &ahci_pmp_retry_srst_ops,
 191        },
 192        [board_ahci_vt8251] =
 193        {
 194                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 195                .flags          = AHCI_FLAG_COMMON,
 196                .pio_mask       = ATA_PIO4,
 197                .udma_mask      = ATA_UDMA6,
 198                .port_ops       = &ahci_vt8251_ops,
 199        },
 200};
 201
 202static const struct pci_device_id ahci_pci_tbl[] = {
 203        /* Intel */
 204        { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 205        { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 206        { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 207        { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 208        { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 209        { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 210        { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 211        { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 212        { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 213        { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 214        { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 215        { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 216        { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 217        { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 218        { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 219        { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 220        { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 221        { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 222        { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 223        { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 224        { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
 225        { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
 226        { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
 227        { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
 228        { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
 229        { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 230        { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
 231        { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 232        { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 233        { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 234        { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 235        { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 236        { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 237        { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 238        { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 239        { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 240        { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
 241        { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 242        { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
 243        { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 244        { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 245        { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
 246        { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 247        { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
 248        { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 249        { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 250        { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
 251        { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
 252        { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 253        { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
 254        { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
 255        { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
 256        { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
 257        { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
 258        { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
 259        { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
 260        { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
 261        { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
 262
 263        /* JMicron 360/1/3/5/6, match class to avoid IDE function */
 264        { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 265          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 266
 267        /* ATI */
 268        { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 269        { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 270        { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 271        { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 272        { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 273        { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 274        { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 275
 276        /* AMD */
 277        { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 278        /* AMD is using RAID class only for ahci controllers */
 279        { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 280          PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 281
 282        /* VIA */
 283        { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 284        { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 285
 286        /* NVIDIA */
 287        { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
 288        { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
 289        { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
 290        { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
 291        { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
 292        { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
 293        { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
 294        { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
 295        { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
 296        { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
 297        { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
 298        { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
 299        { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
 300        { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
 301        { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
 302        { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
 303        { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
 304        { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
 305        { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
 306        { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
 307        { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
 308        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
 309        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
 310        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
 311        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
 312        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
 313        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
 314        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
 315        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
 316        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
 317        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
 318        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
 319        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
 320        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
 321        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
 322        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
 323        { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
 324        { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
 325        { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
 326        { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
 327        { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
 328        { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
 329        { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
 330        { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
 331        { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
 332        { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
 333        { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
 334        { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
 335        { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
 336        { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
 337        { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
 338        { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
 339        { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
 340        { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
 341        { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
 342        { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
 343        { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
 344        { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
 345        { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
 346        { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
 347        { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
 348        { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
 349        { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
 350        { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
 351        { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
 352        { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
 353        { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
 354        { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
 355        { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
 356        { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
 357        { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
 358        { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
 359        { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
 360        { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
 361        { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
 362        { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
 363        { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
 364        { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
 365        { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
 366        { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
 367        { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
 368        { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
 369        { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
 370        { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
 371
 372        /* SiS */
 373        { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
 374        { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
 375        { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
 376
 377        /* ST Microelectronics */
 378        { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
 379
 380        /* Marvell */
 381        { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
 382        { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
 383        { PCI_DEVICE(0x1b4b, 0x9123),
 384          .class = PCI_CLASS_STORAGE_SATA_AHCI,
 385          .class_mask = 0xffffff,
 386          .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
 387        { PCI_DEVICE(0x1b4b, 0x9125),
 388          .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
 389        { PCI_DEVICE(0x1b4b, 0x91a3),
 390          .driver_data = board_ahci_yes_fbs },
 391
 392        /* Promise */
 393        { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
 394
 395        /* Asmedia */
 396        { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1061 */
 397
 398        /* Generic, PCI class code for AHCI */
 399        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 400          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 401
 402        { }     /* terminate list */
 403};
 404
 405
 406static struct pci_driver ahci_pci_driver = {
 407        .name                   = DRV_NAME,
 408        .id_table               = ahci_pci_tbl,
 409        .probe                  = ahci_init_one,
 410        .remove                 = ata_pci_remove_one,
 411#ifdef CONFIG_PM
 412        .suspend                = ahci_pci_device_suspend,
 413        .resume                 = ahci_pci_device_resume,
 414#endif
 415};
 416
 417#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 418static int marvell_enable;
 419#else
 420static int marvell_enable = 1;
 421#endif
 422module_param(marvell_enable, int, 0644);
 423MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 424
 425
 426static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 427                                         struct ahci_host_priv *hpriv)
 428{
 429        unsigned int force_port_map = 0;
 430        unsigned int mask_port_map = 0;
 431
 432        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 433                dev_info(&pdev->dev, "JMB361 has only one port\n");
 434                force_port_map = 1;
 435        }
 436
 437        /*
 438         * Temporary Marvell 6145 hack: PATA port presence
 439         * is asserted through the standard AHCI port
 440         * presence register, as bit 4 (counting from 0)
 441         */
 442        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 443                if (pdev->device == 0x6121)
 444                        mask_port_map = 0x3;
 445                else
 446                        mask_port_map = 0xf;
 447                dev_info(&pdev->dev,
 448                          "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 449        }
 450
 451        ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
 452                                 mask_port_map);
 453}
 454
 455static int ahci_pci_reset_controller(struct ata_host *host)
 456{
 457        struct pci_dev *pdev = to_pci_dev(host->dev);
 458
 459        ahci_reset_controller(host);
 460
 461        if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 462                struct ahci_host_priv *hpriv = host->private_data;
 463                u16 tmp16;
 464
 465                /* configure PCS */
 466                pci_read_config_word(pdev, 0x92, &tmp16);
 467                if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
 468                        tmp16 |= hpriv->port_map;
 469                        pci_write_config_word(pdev, 0x92, tmp16);
 470                }
 471        }
 472
 473        return 0;
 474}
 475
 476static void ahci_pci_init_controller(struct ata_host *host)
 477{
 478        struct ahci_host_priv *hpriv = host->private_data;
 479        struct pci_dev *pdev = to_pci_dev(host->dev);
 480        void __iomem *port_mmio;
 481        u32 tmp;
 482        int mv;
 483
 484        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 485                if (pdev->device == 0x6121)
 486                        mv = 2;
 487                else
 488                        mv = 4;
 489                port_mmio = __ahci_port_base(host, mv);
 490
 491                writel(0, port_mmio + PORT_IRQ_MASK);
 492
 493                /* clear port IRQ */
 494                tmp = readl(port_mmio + PORT_IRQ_STAT);
 495                VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
 496                if (tmp)
 497                        writel(tmp, port_mmio + PORT_IRQ_STAT);
 498        }
 499
 500        ahci_init_controller(host);
 501}
 502
 503static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 504                                 unsigned long deadline)
 505{
 506        struct ata_port *ap = link->ap;
 507        bool online;
 508        int rc;
 509
 510        DPRINTK("ENTER\n");
 511
 512        ahci_stop_engine(ap);
 513
 514        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 515                                 deadline, &online, NULL);
 516
 517        ahci_start_engine(ap);
 518
 519        DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 520
 521        /* vt8251 doesn't clear BSY on signature FIS reception,
 522         * request follow-up softreset.
 523         */
 524        return online ? -EAGAIN : rc;
 525}
 526
 527static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 528                                unsigned long deadline)
 529{
 530        struct ata_port *ap = link->ap;
 531        struct ahci_port_priv *pp = ap->private_data;
 532        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 533        struct ata_taskfile tf;
 534        bool online;
 535        int rc;
 536
 537        ahci_stop_engine(ap);
 538
 539        /* clear D2H reception area to properly wait for D2H FIS */
 540        ata_tf_init(link->device, &tf);
 541        tf.command = 0x80;
 542        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 543
 544        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 545                                 deadline, &online, NULL);
 546
 547        ahci_start_engine(ap);
 548
 549        /* The pseudo configuration device on SIMG4726 attached to
 550         * ASUS P5W-DH Deluxe doesn't send signature FIS after
 551         * hardreset if no device is attached to the first downstream
 552         * port && the pseudo device locks up on SRST w/ PMP==0.  To
 553         * work around this, wait for !BSY only briefly.  If BSY isn't
 554         * cleared, perform CLO and proceed to IDENTIFY (achieved by
 555         * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 556         *
 557         * Wait for two seconds.  Devices attached to downstream port
 558         * which can't process the following IDENTIFY after this will
 559         * have to be reset again.  For most cases, this should
 560         * suffice while making probing snappish enough.
 561         */
 562        if (online) {
 563                rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 564                                          ahci_check_ready);
 565                if (rc)
 566                        ahci_kick_engine(ap);
 567        }
 568        return rc;
 569}
 570
 571#ifdef CONFIG_PM
 572static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 573{
 574        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 575        struct ahci_host_priv *hpriv = host->private_data;
 576        void __iomem *mmio = hpriv->mmio;
 577        u32 ctl;
 578
 579        if (mesg.event & PM_EVENT_SUSPEND &&
 580            hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 581                dev_err(&pdev->dev,
 582                        "BIOS update required for suspend/resume\n");
 583                return -EIO;
 584        }
 585
 586        if (mesg.event & PM_EVENT_SLEEP) {
 587                /* AHCI spec rev1.1 section 8.3.3:
 588                 * Software must disable interrupts prior to requesting a
 589                 * transition of the HBA to D3 state.
 590                 */
 591                ctl = readl(mmio + HOST_CTL);
 592                ctl &= ~HOST_IRQ_EN;
 593                writel(ctl, mmio + HOST_CTL);
 594                readl(mmio + HOST_CTL); /* flush */
 595        }
 596
 597        return ata_pci_device_suspend(pdev, mesg);
 598}
 599
 600static int ahci_pci_device_resume(struct pci_dev *pdev)
 601{
 602        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 603        int rc;
 604
 605        rc = ata_pci_device_do_resume(pdev);
 606        if (rc)
 607                return rc;
 608
 609        if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 610                rc = ahci_pci_reset_controller(host);
 611                if (rc)
 612                        return rc;
 613
 614                ahci_pci_init_controller(host);
 615        }
 616
 617        ata_host_resume(host);
 618
 619        return 0;
 620}
 621#endif
 622
 623static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 624{
 625        int rc;
 626
 627        /*
 628         * If the device fixup already set the dma_mask to some non-standard
 629         * value, don't extend it here. This happens on STA2X11, for example.
 630         */
 631        if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 632                return 0;
 633
 634        if (using_dac &&
 635            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 636                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 637                if (rc) {
 638                        rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 639                        if (rc) {
 640                                dev_err(&pdev->dev,
 641                                        "64-bit DMA enable failed\n");
 642                                return rc;
 643                        }
 644                }
 645        } else {
 646                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 647                if (rc) {
 648                        dev_err(&pdev->dev, "32-bit DMA enable failed\n");
 649                        return rc;
 650                }
 651                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 652                if (rc) {
 653                        dev_err(&pdev->dev,
 654                                "32-bit consistent DMA enable failed\n");
 655                        return rc;
 656                }
 657        }
 658        return 0;
 659}
 660
 661static void ahci_pci_print_info(struct ata_host *host)
 662{
 663        struct pci_dev *pdev = to_pci_dev(host->dev);
 664        u16 cc;
 665        const char *scc_s;
 666
 667        pci_read_config_word(pdev, 0x0a, &cc);
 668        if (cc == PCI_CLASS_STORAGE_IDE)
 669                scc_s = "IDE";
 670        else if (cc == PCI_CLASS_STORAGE_SATA)
 671                scc_s = "SATA";
 672        else if (cc == PCI_CLASS_STORAGE_RAID)
 673                scc_s = "RAID";
 674        else
 675                scc_s = "unknown";
 676
 677        ahci_print_info(host, scc_s);
 678}
 679
 680/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 681 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 682 * support PMP and the 4726 either directly exports the device
 683 * attached to the first downstream port or acts as a hardware storage
 684 * controller and emulate a single ATA device (can be RAID 0/1 or some
 685 * other configuration).
 686 *
 687 * When there's no device attached to the first downstream port of the
 688 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 689 * configure the 4726.  However, ATA emulation of the device is very
 690 * lame.  It doesn't send signature D2H Reg FIS after the initial
 691 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 692 *
 693 * The following function works around the problem by always using
 694 * hardreset on the port and not depending on receiving signature FIS
 695 * afterward.  If signature FIS isn't received soon, ATA class is
 696 * assumed without follow-up softreset.
 697 */
 698static void ahci_p5wdh_workaround(struct ata_host *host)
 699{
 700        static struct dmi_system_id sysids[] = {
 701                {
 702                        .ident = "P5W DH Deluxe",
 703                        .matches = {
 704                                DMI_MATCH(DMI_SYS_VENDOR,
 705                                          "ASUSTEK COMPUTER INC"),
 706                                DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
 707                        },
 708                },
 709                { }
 710        };
 711        struct pci_dev *pdev = to_pci_dev(host->dev);
 712
 713        if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
 714            dmi_check_system(sysids)) {
 715                struct ata_port *ap = host->ports[1];
 716
 717                dev_info(&pdev->dev,
 718                         "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
 719
 720                ap->ops = &ahci_p5wdh_ops;
 721                ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
 722        }
 723}
 724
 725/* only some SB600 ahci controllers can do 64bit DMA */
 726static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
 727{
 728        static const struct dmi_system_id sysids[] = {
 729                /*
 730                 * The oldest version known to be broken is 0901 and
 731                 * working is 1501 which was released on 2007-10-26.
 732                 * Enable 64bit DMA on 1501 and anything newer.
 733                 *
 734                 * Please read bko#9412 for more info.
 735                 */
 736                {
 737                        .ident = "ASUS M2A-VM",
 738                        .matches = {
 739                                DMI_MATCH(DMI_BOARD_VENDOR,
 740                                          "ASUSTeK Computer INC."),
 741                                DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
 742                        },
 743                        .driver_data = "20071026",      /* yyyymmdd */
 744                },
 745                /*
 746                 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
 747                 * support 64bit DMA.
 748                 *
 749                 * BIOS versions earlier than 1.5 had the Manufacturer DMI
 750                 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
 751                 * This spelling mistake was fixed in BIOS version 1.5, so
 752                 * 1.5 and later have the Manufacturer as
 753                 * "MICRO-STAR INTERNATIONAL CO.,LTD".
 754                 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
 755                 *
 756                 * BIOS versions earlier than 1.9 had a Board Product Name
 757                 * DMI field of "MS-7376". This was changed to be
 758                 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
 759                 * match on DMI_BOARD_NAME of "MS-7376".
 760                 */
 761                {
 762                        .ident = "MSI K9A2 Platinum",
 763                        .matches = {
 764                                DMI_MATCH(DMI_BOARD_VENDOR,
 765                                          "MICRO-STAR INTER"),
 766                                DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
 767                        },
 768                },
 769                /*
 770                 * All BIOS versions for the Asus M3A support 64bit DMA.
 771                 * (all release versions from 0301 to 1206 were tested)
 772                 */
 773                {
 774                        .ident = "ASUS M3A",
 775                        .matches = {
 776                                DMI_MATCH(DMI_BOARD_VENDOR,
 777                                          "ASUSTeK Computer INC."),
 778                                DMI_MATCH(DMI_BOARD_NAME, "M3A"),
 779                        },
 780                },
 781                { }
 782        };
 783        const struct dmi_system_id *match;
 784        int year, month, date;
 785        char buf[9];
 786
 787        match = dmi_first_match(sysids);
 788        if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
 789            !match)
 790                return false;
 791
 792        if (!match->driver_data)
 793                goto enable_64bit;
 794
 795        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 796        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 797
 798        if (strcmp(buf, match->driver_data) >= 0)
 799                goto enable_64bit;
 800        else {
 801                dev_warn(&pdev->dev,
 802                         "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
 803                         match->ident);
 804                return false;
 805        }
 806
 807enable_64bit:
 808        dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
 809        return true;
 810}
 811
 812static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
 813{
 814        static const struct dmi_system_id broken_systems[] = {
 815                {
 816                        .ident = "HP Compaq nx6310",
 817                        .matches = {
 818                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 819                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
 820                        },
 821                        /* PCI slot number of the controller */
 822                        .driver_data = (void *)0x1FUL,
 823                },
 824                {
 825                        .ident = "HP Compaq 6720s",
 826                        .matches = {
 827                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 828                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
 829                        },
 830                        /* PCI slot number of the controller */
 831                        .driver_data = (void *)0x1FUL,
 832                },
 833
 834                { }     /* terminate list */
 835        };
 836        const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
 837
 838        if (dmi) {
 839                unsigned long slot = (unsigned long)dmi->driver_data;
 840                /* apply the quirk only to on-board controllers */
 841                return slot == PCI_SLOT(pdev->devfn);
 842        }
 843
 844        return false;
 845}
 846
 847static bool ahci_broken_suspend(struct pci_dev *pdev)
 848{
 849        static const struct dmi_system_id sysids[] = {
 850                /*
 851                 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
 852                 * to the harddisk doesn't become online after
 853                 * resuming from STR.  Warn and fail suspend.
 854                 *
 855                 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
 856                 *
 857                 * Use dates instead of versions to match as HP is
 858                 * apparently recycling both product and version
 859                 * strings.
 860                 *
 861                 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
 862                 */
 863                {
 864                        .ident = "dv4",
 865                        .matches = {
 866                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 867                                DMI_MATCH(DMI_PRODUCT_NAME,
 868                                          "HP Pavilion dv4 Notebook PC"),
 869                        },
 870                        .driver_data = "20090105",      /* F.30 */
 871                },
 872                {
 873                        .ident = "dv5",
 874                        .matches = {
 875                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 876                                DMI_MATCH(DMI_PRODUCT_NAME,
 877                                          "HP Pavilion dv5 Notebook PC"),
 878                        },
 879                        .driver_data = "20090506",      /* F.16 */
 880                },
 881                {
 882                        .ident = "dv6",
 883                        .matches = {
 884                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 885                                DMI_MATCH(DMI_PRODUCT_NAME,
 886                                          "HP Pavilion dv6 Notebook PC"),
 887                        },
 888                        .driver_data = "20090423",      /* F.21 */
 889                },
 890                {
 891                        .ident = "HDX18",
 892                        .matches = {
 893                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 894                                DMI_MATCH(DMI_PRODUCT_NAME,
 895                                          "HP HDX18 Notebook PC"),
 896                        },
 897                        .driver_data = "20090430",      /* F.23 */
 898                },
 899                /*
 900                 * Acer eMachines G725 has the same problem.  BIOS
 901                 * V1.03 is known to be broken.  V3.04 is known to
 902                 * work.  Between, there are V1.06, V2.06 and V3.03
 903                 * that we don't have much idea about.  For now,
 904                 * blacklist anything older than V3.04.
 905                 *
 906                 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
 907                 */
 908                {
 909                        .ident = "G725",
 910                        .matches = {
 911                                DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
 912                                DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
 913                        },
 914                        .driver_data = "20091216",      /* V3.04 */
 915                },
 916                { }     /* terminate list */
 917        };
 918        const struct dmi_system_id *dmi = dmi_first_match(sysids);
 919        int year, month, date;
 920        char buf[9];
 921
 922        if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
 923                return false;
 924
 925        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 926        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 927
 928        return strcmp(buf, dmi->driver_data) < 0;
 929}
 930
 931static bool ahci_broken_online(struct pci_dev *pdev)
 932{
 933#define ENCODE_BUSDEVFN(bus, slot, func)                        \
 934        (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
 935        static const struct dmi_system_id sysids[] = {
 936                /*
 937                 * There are several gigabyte boards which use
 938                 * SIMG5723s configured as hardware RAID.  Certain
 939                 * 5723 firmware revisions shipped there keep the link
 940                 * online but fail to answer properly to SRST or
 941                 * IDENTIFY when no device is attached downstream
 942                 * causing libata to retry quite a few times leading
 943                 * to excessive detection delay.
 944                 *
 945                 * As these firmwares respond to the second reset try
 946                 * with invalid device signature, considering unknown
 947                 * sig as offline works around the problem acceptably.
 948                 */
 949                {
 950                        .ident = "EP45-DQ6",
 951                        .matches = {
 952                                DMI_MATCH(DMI_BOARD_VENDOR,
 953                                          "Gigabyte Technology Co., Ltd."),
 954                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
 955                        },
 956                        .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
 957                },
 958                {
 959                        .ident = "EP45-DS5",
 960                        .matches = {
 961                                DMI_MATCH(DMI_BOARD_VENDOR,
 962                                          "Gigabyte Technology Co., Ltd."),
 963                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
 964                        },
 965                        .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
 966                },
 967                { }     /* terminate list */
 968        };
 969#undef ENCODE_BUSDEVFN
 970        const struct dmi_system_id *dmi = dmi_first_match(sysids);
 971        unsigned int val;
 972
 973        if (!dmi)
 974                return false;
 975
 976        val = (unsigned long)dmi->driver_data;
 977
 978        return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
 979}
 980
 981#ifdef CONFIG_ATA_ACPI
 982static void ahci_gtf_filter_workaround(struct ata_host *host)
 983{
 984        static const struct dmi_system_id sysids[] = {
 985                /*
 986                 * Aspire 3810T issues a bunch of SATA enable commands
 987                 * via _GTF including an invalid one and one which is
 988                 * rejected by the device.  Among the successful ones
 989                 * is FPDMA non-zero offset enable which when enabled
 990                 * only on the drive side leads to NCQ command
 991                 * failures.  Filter it out.
 992                 */
 993                {
 994                        .ident = "Aspire 3810T",
 995                        .matches = {
 996                                DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
 997                                DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
 998                        },
 999                        .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1000                },
1001                { }
1002        };
1003        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1004        unsigned int filter;
1005        int i;
1006
1007        if (!dmi)
1008                return;
1009
1010        filter = (unsigned long)dmi->driver_data;
1011        dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1012                 filter, dmi->ident);
1013
1014        for (i = 0; i < host->n_ports; i++) {
1015                struct ata_port *ap = host->ports[i];
1016                struct ata_link *link;
1017                struct ata_device *dev;
1018
1019                ata_for_each_link(link, ap, EDGE)
1020                        ata_for_each_dev(dev, link, ALL)
1021                                dev->gtf_filter |= filter;
1022        }
1023}
1024#else
1025static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1026{}
1027#endif
1028
1029static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1030{
1031        unsigned int board_id = ent->driver_data;
1032        struct ata_port_info pi = ahci_port_info[board_id];
1033        const struct ata_port_info *ppi[] = { &pi, NULL };
1034        struct device *dev = &pdev->dev;
1035        struct ahci_host_priv *hpriv;
1036        struct ata_host *host;
1037        int n_ports, i, rc;
1038        int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1039
1040        VPRINTK("ENTER\n");
1041
1042        WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1043
1044        ata_print_version_once(&pdev->dev, DRV_VERSION);
1045
1046        /* The AHCI driver can only drive the SATA ports, the PATA driver
1047           can drive them all so if both drivers are selected make sure
1048           AHCI stays out of the way */
1049        if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1050                return -ENODEV;
1051
1052        /*
1053         * For some reason, MCP89 on MacBook 7,1 doesn't work with
1054         * ahci, use ata_generic instead.
1055         */
1056        if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1057            pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1058            pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1059            pdev->subsystem_device == 0xcb89)
1060                return -ENODEV;
1061
1062        /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1063         * At the moment, we can only use the AHCI mode. Let the users know
1064         * that for SAS drives they're out of luck.
1065         */
1066        if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1067                dev_info(&pdev->dev,
1068                         "PDC42819 can only drive SATA devices with this driver\n");
1069
1070        /* The Connext uses non-standard BAR */
1071        if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1072                ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1073
1074        /* acquire resources */
1075        rc = pcim_enable_device(pdev);
1076        if (rc)
1077                return rc;
1078
1079        /* AHCI controllers often implement SFF compatible interface.
1080         * Grab all PCI BARs just in case.
1081         */
1082        rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1083        if (rc == -EBUSY)
1084                pcim_pin_device(pdev);
1085        if (rc)
1086                return rc;
1087
1088        if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1089            (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1090                u8 map;
1091
1092                /* ICH6s share the same PCI ID for both piix and ahci
1093                 * modes.  Enabling ahci mode while MAP indicates
1094                 * combined mode is a bad idea.  Yield to ata_piix.
1095                 */
1096                pci_read_config_byte(pdev, ICH_MAP, &map);
1097                if (map & 0x3) {
1098                        dev_info(&pdev->dev,
1099                                 "controller is in combined mode, can't enable AHCI mode\n");
1100                        return -ENODEV;
1101                }
1102        }
1103
1104        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1105        if (!hpriv)
1106                return -ENOMEM;
1107        hpriv->flags |= (unsigned long)pi.private_data;
1108
1109        /* MCP65 revision A1 and A2 can't do MSI */
1110        if (board_id == board_ahci_mcp65 &&
1111            (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1112                hpriv->flags |= AHCI_HFLAG_NO_MSI;
1113
1114        /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1115        if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1116                hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1117
1118        /* only some SB600s can do 64bit DMA */
1119        if (ahci_sb600_enable_64bit(pdev))
1120                hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1121
1122        if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1123                pci_intx(pdev, 1);
1124
1125        hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1126
1127        /* save initial config */
1128        ahci_pci_save_initial_config(pdev, hpriv);
1129
1130        /* prepare host */
1131        if (hpriv->cap & HOST_CAP_NCQ) {
1132                pi.flags |= ATA_FLAG_NCQ;
1133                /*
1134                 * Auto-activate optimization is supposed to be
1135                 * supported on all AHCI controllers indicating NCQ
1136                 * capability, but it seems to be broken on some
1137                 * chipsets including NVIDIAs.
1138                 */
1139                if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1140                        pi.flags |= ATA_FLAG_FPDMA_AA;
1141        }
1142
1143        if (hpriv->cap & HOST_CAP_PMP)
1144                pi.flags |= ATA_FLAG_PMP;
1145
1146        ahci_set_em_messages(hpriv, &pi);
1147
1148        if (ahci_broken_system_poweroff(pdev)) {
1149                pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1150                dev_info(&pdev->dev,
1151                        "quirky BIOS, skipping spindown on poweroff\n");
1152        }
1153
1154        if (ahci_broken_suspend(pdev)) {
1155                hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1156                dev_warn(&pdev->dev,
1157                         "BIOS update required for suspend/resume\n");
1158        }
1159
1160        if (ahci_broken_online(pdev)) {
1161                hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1162                dev_info(&pdev->dev,
1163                         "online status unreliable, applying workaround\n");
1164        }
1165
1166        /* CAP.NP sometimes indicate the index of the last enabled
1167         * port, at other times, that of the last possible port, so
1168         * determining the maximum port number requires looking at
1169         * both CAP.NP and port_map.
1170         */
1171        n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1172
1173        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1174        if (!host)
1175                return -ENOMEM;
1176        host->private_data = hpriv;
1177
1178        if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1179                host->flags |= ATA_HOST_PARALLEL_SCAN;
1180        else
1181                printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1182
1183        if (pi.flags & ATA_FLAG_EM)
1184                ahci_reset_em(host);
1185
1186        for (i = 0; i < host->n_ports; i++) {
1187                struct ata_port *ap = host->ports[i];
1188
1189                ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1190                ata_port_pbar_desc(ap, ahci_pci_bar,
1191                                   0x100 + ap->port_no * 0x80, "port");
1192
1193                /* set enclosure management message type */
1194                if (ap->flags & ATA_FLAG_EM)
1195                        ap->em_message_type = hpriv->em_msg_type;
1196
1197
1198                /* disabled/not-implemented port */
1199                if (!(hpriv->port_map & (1 << i)))
1200                        ap->ops = &ata_dummy_port_ops;
1201        }
1202
1203        /* apply workaround for ASUS P5W DH Deluxe mainboard */
1204        ahci_p5wdh_workaround(host);
1205
1206        /* apply gtf filter quirk */
1207        ahci_gtf_filter_workaround(host);
1208
1209        /* initialize adapter */
1210        rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1211        if (rc)
1212                return rc;
1213
1214        rc = ahci_pci_reset_controller(host);
1215        if (rc)
1216                return rc;
1217
1218        ahci_pci_init_controller(host);
1219        ahci_pci_print_info(host);
1220
1221        pci_set_master(pdev);
1222        return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1223                                 &ahci_sht);
1224}
1225
1226static int __init ahci_init(void)
1227{
1228        return pci_register_driver(&ahci_pci_driver);
1229}
1230
1231static void __exit ahci_exit(void)
1232{
1233        pci_unregister_driver(&ahci_pci_driver);
1234}
1235
1236
1237MODULE_AUTHOR("Jeff Garzik");
1238MODULE_DESCRIPTION("AHCI SATA low-level driver");
1239MODULE_LICENSE("GPL");
1240MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1241MODULE_VERSION(DRV_VERSION);
1242
1243module_init(ahci_init);
1244module_exit(ahci_exit);
1245