/*
 *      PCI Bus Services, see include/linux/pci.h for further explanation.
 *
 *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
 *      David Mosberger-Tang
 *
 *      Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/log2.h>
#include <linux/pci-aspm.h>
#include <linux/pm_wakeup.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/pm_runtime.h>
#include <asm/setup.h>
#include "pci.h"

const char *pci_power_names[] = {
        "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
};
EXPORT_SYMBOL_GPL(pci_power_names);

int isa_dma_bridge_buggy;
EXPORT_SYMBOL(isa_dma_bridge_buggy);

int pci_pci_problems;
EXPORT_SYMBOL(pci_pci_problems);

unsigned int pci_pm_d3_delay;

static void pci_pme_list_scan(struct work_struct *work);

static LIST_HEAD(pci_pme_list);
static DEFINE_MUTEX(pci_pme_list_mutex);
static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);

struct pci_pme_device {
        struct list_head list;
        struct pci_dev *dev;
};

#define PME_TIMEOUT 1000 /* How long between PME checks */

static void pci_dev_d3_sleep(struct pci_dev *dev)
{
        unsigned int delay = dev->d3_delay;

        if (delay < pci_pm_d3_delay)
                delay = pci_pm_d3_delay;

        msleep(delay);
}

#ifdef CONFIG_PCI_DOMAINS
int pci_domains_supported = 1;
#endif

#define DEFAULT_CARDBUS_IO_SIZE         (256)
#define DEFAULT_CARDBUS_MEM_SIZE        (64*1024*1024)
/* pci=cbmemsize=nnM,cbiosize=nn can override this */
unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;

#define DEFAULT_HOTPLUG_IO_SIZE         (256)
#define DEFAULT_HOTPLUG_MEM_SIZE        (2*1024*1024)
/* pci=hpmemsize=nnM,hpiosize=nn can override this */
unsigned long pci_hotplug_io_size  = DEFAULT_HOTPLUG_IO_SIZE;
unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;

enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;

/*
 * The default CLS is used if arch didn't set CLS explicitly and not
 * all pci devices agree on the same value.  Arch can override either
 * the dfl or actual value as it sees fit.  Don't forget this is
 * measured in 32-bit words, not bytes.
 */
u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
u8 pci_cache_line_size;

/*
 * If we set up a device for bus mastering, we need to check the latency
 * timer as certain BIOSes forget to set it properly.
 */
unsigned int pcibios_max_latency = 255;

/**
 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
 * @bus: pointer to PCI bus structure to search
 *
 * Given a PCI bus, returns the highest PCI bus number present in the set
 * including the given PCI bus and its list of child PCI buses.
 */
unsigned char pci_bus_max_busnr(struct pci_bus* bus)
{
        struct list_head *tmp;
        unsigned char max, n;

        max = bus->subordinate;
        list_for_each(tmp, &bus->children) {
                n = pci_bus_max_busnr(pci_bus_b(tmp));
                if(n > max)
                        max = n;
        }
        return max;
}
EXPORT_SYMBOL_GPL(pci_bus_max_busnr);

#ifdef CONFIG_HAS_IOMEM
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
{
        /*
         * Make sure the BAR is actually a memory resource, not an IO resource
         */
        if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
                WARN_ON(1);
                return NULL;
        }
        return ioremap_nocache(pci_resource_start(pdev, bar),
                                     pci_resource_len(pdev, bar));
}
EXPORT_SYMBOL_GPL(pci_ioremap_bar);
#endif

#if 0
/**
 * pci_max_busnr - returns maximum PCI bus number
 *
 * Returns the highest PCI bus number present in the system global list of
 * PCI buses.
 */
unsigned char __devinit
pci_max_busnr(void)
{
        struct pci_bus *bus = NULL;
        unsigned char max, n;

        max = 0;
        while ((bus = pci_find_next_bus(bus)) != NULL) {
                n = pci_bus_max_busnr(bus);
                if(n > max)
                        max = n;
        }
        return max;
}

#endif  /*  0  */

#define PCI_FIND_CAP_TTL        48

static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
                                   u8 pos, int cap, int *ttl)
{
        u8 id;

        while ((*ttl)--) {
                pci_bus_read_config_byte(bus, devfn, pos, &pos);
                if (pos < 0x40)
                        break;
                pos &= ~3;
                pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
                                         &id);
                if (id == 0xff)
                        break;
                if (id == cap)
                        return pos;
                pos += PCI_CAP_LIST_NEXT;
        }
        return 0;
}

static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
                               u8 pos, int cap)
{
        int ttl = PCI_FIND_CAP_TTL;

        return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
}

int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
{
        return __pci_find_next_cap(dev->bus, dev->devfn,
                                   pos + PCI_CAP_LIST_NEXT, cap);
}
EXPORT_SYMBOL_GPL(pci_find_next_capability);

static int __pci_bus_find_cap_start(struct pci_bus *bus,
                                    unsigned int devfn, u8 hdr_type)
{
        u16 status;

        pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
        if (!(status & PCI_STATUS_CAP_LIST))
                return 0;

        switch (hdr_type) {
        case PCI_HEADER_TYPE_NORMAL:
        case PCI_HEADER_TYPE_BRIDGE:
                return PCI_CAPABILITY_LIST;
        case PCI_HEADER_TYPE_CARDBUS:
                return PCI_CB_CAPABILITY_LIST;
        default:
                return 0;
        }

        return 0;
}

/**
 * pci_find_capability - query for devices' capabilities 
 * @dev: PCI device to query
 * @cap: capability code
 *
 * Tell if a device supports a given PCI capability.
 * Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.  Possible values for @cap:
 *
 *  %PCI_CAP_ID_PM           Power Management 
 *  %PCI_CAP_ID_AGP          Accelerated Graphics Port 
 *  %PCI_CAP_ID_VPD          Vital Product Data 
 *  %PCI_CAP_ID_SLOTID       Slot Identification 
 *  %PCI_CAP_ID_MSI          Message Signalled Interrupts
 *  %PCI_CAP_ID_CHSWP        CompactPCI HotSwap 
 *  %PCI_CAP_ID_PCIX         PCI-X
 *  %PCI_CAP_ID_EXP          PCI Express
 */
int pci_find_capability(struct pci_dev *dev, int cap)
{
        int pos;

        pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
        if (pos)
                pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);

        return pos;
}

/**
 * pci_bus_find_capability - query for devices' capabilities 
 * @bus:   the PCI bus to query
 * @devfn: PCI device to query
 * @cap:   capability code
 *
 * Like pci_find_capability() but works for pci devices that do not have a
 * pci_dev structure set up yet. 
 *
 * Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.
 */
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
{
        int pos;
        u8 hdr_type;

        pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);

        pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
        if (pos)
                pos = __pci_find_next_cap(bus, devfn, pos, cap);

        return pos;
}

/**
 * pci_find_ext_capability - Find an extended capability
 * @dev: PCI device to query
 * @cap: capability code
 *
 * Returns the address of the requested extended capability structure
 * within the device's PCI configuration space or 0 if the device does
 * not support it.  Possible values for @cap:
 *
 *  %PCI_EXT_CAP_ID_ERR         Advanced Error Reporting
 *  %PCI_EXT_CAP_ID_VC          Virtual Channel
 *  %PCI_EXT_CAP_ID_DSN         Device Serial Number
 *  %PCI_EXT_CAP_ID_PWR         Power Budgeting
 */
int pci_find_ext_capability(struct pci_dev *dev, int cap)
{
        u32 header;
        int ttl;
        int pos = PCI_CFG_SPACE_SIZE;

        /* minimum 8 bytes per capability */
        ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;

        if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
                return 0;

        if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
                return 0;

        /*
         * If we have no capabilities, this is indicated by cap ID,
         * cap version and next pointer all being 0.
         */
        if (header == 0)
                return 0;

        while (ttl-- > 0) {
                if (PCI_EXT_CAP_ID(header) == cap)
                        return pos;

                pos = PCI_EXT_CAP_NEXT(header);
                if (pos < PCI_CFG_SPACE_SIZE)
                        break;

                if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
                        break;
        }

        return 0;
}
EXPORT_SYMBOL_GPL(pci_find_ext_capability);

/**
 * pci_bus_find_ext_capability - find an extended capability
 * @bus:   the PCI bus to query
 * @devfn: PCI device to query
 * @cap:   capability code
 *
 * Like pci_find_ext_capability() but works for pci devices that do not have a
 * pci_dev structure set up yet.
 *
 * Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.
 */
int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
                                int cap)
{
        u32 header;
        int ttl;
        int pos = PCI_CFG_SPACE_SIZE;

        /* minimum 8 bytes per capability */
        ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;

        if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
                return 0;
        if (header == 0xffffffff || header == 0)
                return 0;

        while (ttl-- > 0) {
                if (PCI_EXT_CAP_ID(header) == cap)
                        return pos;

                pos = PCI_EXT_CAP_NEXT(header);
                if (pos < PCI_CFG_SPACE_SIZE)
                        break;

                if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
                        break;
        }

        return 0;
}

static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
{
        int rc, ttl = PCI_FIND_CAP_TTL;
        u8 cap, mask;

        if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
                mask = HT_3BIT_CAP_MASK;
        else
                mask = HT_5BIT_CAP_MASK;

        pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
                                      PCI_CAP_ID_HT, &ttl);
        while (pos) {
                rc = pci_read_config_byte(dev, pos + 3, &cap);
                if (rc != PCIBIOS_SUCCESSFUL)
                        return 0;

                if ((cap & mask) == ht_cap)
                        return pos;

                pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
                                              pos + PCI_CAP_LIST_NEXT,
                                              PCI_CAP_ID_HT, &ttl);
        }

        return 0;
}
/**
 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
 * @dev: PCI device to query
 * @pos: Position from which to continue searching
 * @ht_cap: Hypertransport capability code
 *
 * To be used in conjunction with pci_find_ht_capability() to search for
 * all capabilities matching @ht_cap. @pos should always be a value returned
 * from pci_find_ht_capability().
 *
 * NB. To be 100% safe against broken PCI devices, the caller should take
 * steps to avoid an infinite loop.
 */
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
{
        return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
}
EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);

/**
 * pci_find_ht_capability - query a device's Hypertransport capabilities
 * @dev: PCI device to query
 * @ht_cap: Hypertransport capability code
 *
 * Tell if a device supports a given Hypertransport capability.
 * Returns an address within the device's PCI configuration space
 * or 0 in case the device does not support the request capability.
 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
 * which has a Hypertransport capability matching @ht_cap.
 */
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
{
        int pos;

        pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
        if (pos)
                pos = __pci_find_next_ht_cap(dev, pos, ht_cap);

        return pos;
}
EXPORT_SYMBOL_GPL(pci_find_ht_capability);

/**
 * pci_find_parent_resource - return resource region of parent bus of given region
 * @dev: PCI device structure contains resources to be searched
 * @res: child resource record for which parent is sought
 *
 *  For given resource region of given device, return the resource
 *  region of parent bus the given region is contained in or where
 *  it should be allocated from.
 */
struct resource *
pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
{
        const struct pci_bus *bus = dev->bus;
        int i;
        struct resource *best = NULL, *r;

        pci_bus_for_each_resource(bus, r, i) {
                if (!r)
                        continue;
                if (res->start && !(res->start >= r->start && res->end <= r->end))
                        continue;       /* Not contained */
                if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
                        continue;       /* Wrong type */
                if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
                        return r;       /* Exact match */
                /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
                if (r->flags & IORESOURCE_PREFETCH)
                        continue;
                /* .. but we can put a prefetchable resource inside a non-prefetchable one */
                if (!best)
                        best = r;
        }
        return best;
}

/**
 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
 * @dev: PCI device to have its BARs restored
 *
 * Restore the BAR values for a given device, so as to make it
 * accessible by its driver.
 */
static void
pci_restore_bars(struct pci_dev *dev)
{
        int i;

        for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
                pci_update_resource(dev, i);
}

static struct pci_platform_pm_ops *pci_platform_pm;

int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
{
        if (!ops->is_manageable || !ops->set_state || !ops->choose_state
            || !ops->sleep_wake || !ops->can_wakeup)
                return -EINVAL;
        pci_platform_pm = ops;
        return 0;
}

static inline bool platform_pci_power_manageable(struct pci_dev *dev)
{
        return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
}

static inline int platform_pci_set_power_state(struct pci_dev *dev,
                                                pci_power_t t)
{
        return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
}

static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
{
        return pci_platform_pm ?
                        pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
}

static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
{
        return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
}

static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
{
        return pci_platform_pm ?
                        pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
}

static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
{
        return pci_platform_pm ?
                        pci_platform_pm->run_wake(dev, enable) : -ENODEV;
}

/**
 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
 *                           given PCI device
 * @dev: PCI device to handle.
 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
 *
 * RETURN VALUE:
 * -EINVAL if the requested state is invalid.
 * -EIO if device does not support PCI PM or its PM capabilities register has a
 * wrong version, or device doesn't support the requested state.
 * 0 if device already is in the requested state.
 * 0 if device's power state has been successfully changed.
 */
static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
{
        u16 pmcsr;
        bool need_restore = false;

        /* Check if we're already there */
        if (dev->current_state == state)
                return 0;

        if (!dev->pm_cap)
                return -EIO;

        if (state < PCI_D0 || state > PCI_D3hot)
                return -EINVAL;

        /* Validate current state:
         * Can enter D0 from any state, but if we can only go deeper 
         * to sleep if we're already in a low power state
         */
        if (state != PCI_D0 && dev->current_state <= PCI_D3cold
            && dev->current_state > state) {
                dev_err(&dev->dev, "invalid power transition "
                        "(from state %d to %d)\n", dev->current_state, state);
                return -EINVAL;
        }

        /* check if this device supports the desired state */
        if ((state == PCI_D1 && !dev->d1_support)
           || (state == PCI_D2 && !dev->d2_support))
                return -EIO;

        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);

        /* If we're (effectively) in D3, force entire word to 0.
         * This doesn't affect PME_Status, disables PME_En, and
         * sets PowerState to 0.
         */
        switch (dev->current_state) {
        case PCI_D0:
        case PCI_D1:
        case PCI_D2:
                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
                pmcsr |= state;
                break;
        case PCI_D3hot:
        case PCI_D3cold:
        case PCI_UNKNOWN: /* Boot-up */
                if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
                 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
                        need_restore = true;
                /* Fall-through: force to D0 */
        default:
                pmcsr = 0;
                break;
        }

        /* enter specified state */
        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);

        /* Mandatory power management transition delays */
        /* see PCI PM 1.1 5.6.1 table 18 */
        if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
                pci_dev_d3_sleep(dev);
        else if (state == PCI_D2 || dev->current_state == PCI_D2)
                udelay(PCI_PM_D2_DELAY);

        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
        dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
        if (dev->current_state != state && printk_ratelimit())
                dev_info(&dev->dev, "Refused to change power state, "
                        "currently in D%d\n", dev->current_state);

        /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
         * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
         * from D3hot to D0 _may_ perform an internal reset, thereby
         * going to "D0 Uninitialized" rather than "D0 Initialized".
         * For example, at least some versions of the 3c905B and the
         * 3c556B exhibit this behaviour.
         *
         * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
         * devices in a D3hot state at boot.  Consequently, we need to
         * restore at least the BARs so that the device will be
         * accessible to its driver.
         */
        if (need_restore)
                pci_restore_bars(dev);

        if (dev->bus->self)
                pcie_aspm_pm_state_change(dev->bus->self);

        return 0;
}

/**
 * pci_update_current_state - Read PCI power state of given device from its
 *                            PCI PM registers and cache it
 * @dev: PCI device to handle.
 * @state: State to cache in case the device doesn't have the PM capability
 */
void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
{
        if (dev->pm_cap) {
                u16 pmcsr;

                pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
                dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
        } else {
                dev->current_state = state;
        }
}

/**
 * pci_platform_power_transition - Use platform to change device power state
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 */
static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
{
        int error;

        if (platform_pci_power_manageable(dev)) {
                error = platform_pci_set_power_state(dev, state);
                if (!error)
                        pci_update_current_state(dev, state);
                /* Fall back to PCI_D0 if native PM is not supported */
                if (!dev->pm_cap)
                        dev->current_state = PCI_D0;
        } else {
                error = -ENODEV;
                /* Fall back to PCI_D0 if native PM is not supported */
                if (!dev->pm_cap)
                        dev->current_state = PCI_D0;
        }

        return error;
}

/**
 * __pci_start_power_transition - Start power transition of a PCI device
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 */
static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
{
        if (state == PCI_D0)
                pci_platform_power_transition(dev, PCI_D0);
}

/**
 * __pci_complete_power_transition - Complete power transition of a PCI device
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 *
 * This function should not be called directly by device drivers.
 */
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
{
        return state >= PCI_D0 ?
                        pci_platform_power_transition(dev, state) : -EINVAL;
}
EXPORT_SYMBOL_GPL(__pci_complete_power_transition);

/**
 * pci_set_power_state - Set the power state of a PCI device
 * @dev: PCI device to handle.
 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
 *
 * Transition a device to a new power state, using the platform firmware and/or
 * the device's PCI PM registers.
 *
 * RETURN VALUE:
 * -EINVAL if the requested state is invalid.
 * -EIO if device does not support PCI PM or its PM capabilities register has a
 * wrong version, or device doesn't support the requested state.
 * 0 if device already is in the requested state.
 * 0 if device's power state has been successfully changed.
 */
int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
{
        int error;

        /* bound the state we're entering */
        if (state > PCI_D3hot)
                state = PCI_D3hot;
        else if (state < PCI_D0)
                state = PCI_D0;
        else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
                /*
                 * If the device or the parent bridge do not support PCI PM,
                 * ignore the request if we're doing anything other than putting
                 * it into D0 (which would only happen on boot).
                 */
                return 0;

        __pci_start_power_transition(dev, state);

        /* This device is quirked not to be put into D3, so
           don't put it in D3 */
        if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
                return 0;

        error = pci_raw_set_power_state(dev, state);

        if (!__pci_complete_power_transition(dev, state))
                error = 0;
        /*
         * When aspm_policy is "powersave" this call ensures
         * that ASPM is configured.
         */
        if (!error && dev->bus->self)
                pcie_aspm_powersave_config_link(dev->bus->self);

        return error;
}

/**
 * pci_choose_state - Choose the power state of a PCI device
 * @dev: PCI device to be suspended
 * @state: target sleep state for the whole system. This is the value
 *      that is passed to suspend() function.
 *
 * Returns PCI power state suitable for given device and given system
 * message.
 */

pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
{
        pci_power_t ret;

        if (!pci_find_capability(dev, PCI_CAP_ID_PM))
                return PCI_D0;

        ret = platform_pci_choose_state(dev);
        if (ret != PCI_POWER_ERROR)
                return ret;

        switch (state.event) {
        case PM_EVENT_ON:
                return PCI_D0;
        case PM_EVENT_FREEZE:
        case PM_EVENT_PRETHAW:
                /* REVISIT both freeze and pre-thaw "should" use D0 */
        case PM_EVENT_SUSPEND:
        case PM_EVENT_HIBERNATE:
                return PCI_D3hot;
        default:
                dev_info(&dev->dev, "unrecognized suspend event %d\n",
                         state.event);
                BUG();
        }
        return PCI_D0;
}

EXPORT_SYMBOL(pci_choose_state);

#define PCI_EXP_SAVE_REGS       7

#define pcie_cap_has_devctl(type, flags)        1
#define pcie_cap_has_lnkctl(type, flags)                \
                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
                 (type == PCI_EXP_TYPE_ROOT_PORT ||     \
                  type == PCI_EXP_TYPE_ENDPOINT ||      \
                  type == PCI_EXP_TYPE_LEG_END))
#define pcie_cap_has_sltctl(type, flags)                \
                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
                 ((type == PCI_EXP_TYPE_ROOT_PORT) ||   \
                  (type == PCI_EXP_TYPE_DOWNSTREAM &&   \
                   (flags & PCI_EXP_FLAGS_SLOT))))
#define pcie_cap_has_rtctl(type, flags)                 \
                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
                 (type == PCI_EXP_TYPE_ROOT_PORT ||     \
                  type == PCI_EXP_TYPE_RC_EC))
#define pcie_cap_has_devctl2(type, flags)               \
                ((flags & PCI_EXP_FLAGS_VERS) > 1)
#define pcie_cap_has_lnkctl2(type, flags)               \
                ((flags & PCI_EXP_FLAGS_VERS) > 1)
#define pcie_cap_has_sltctl2(type, flags)               \
                ((flags & PCI_EXP_FLAGS_VERS) > 1)

static int pci_save_pcie_state(struct pci_dev *dev)
{
        int pos, i = 0;
        struct pci_cap_saved_state *save_state;
        u16 *cap;
        u16 flags;

        pos = pci_pcie_cap(dev);
        if (!pos)
                return 0;

        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
        if (!save_state) {
                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
                return -ENOMEM;
        }
        cap = (u16 *)&save_state->cap.data[0];

        pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);

        if (pcie_cap_has_devctl(dev->pcie_type, flags))
                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
        if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
                pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
        if (pcie_cap_has_sltctl(dev->pcie_type, flags))
                pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
        if (pcie_cap_has_rtctl(dev->pcie_type, flags))
                pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
        if (pcie_cap_has_devctl2(dev->pcie_type, flags))
                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
        if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
                pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
        if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
                pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);

        return 0;
}

static void pci_restore_pcie_state(struct pci_dev *dev)
{
        int i = 0, pos;
        struct pci_cap_saved_state *save_state;
        u16 *cap;
        u16 flags;

        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
        if (!save_state || pos <= 0)
                return;
        cap = (u16 *)&save_state->cap.data[0];

        pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);

        if (pcie_cap_has_devctl(dev->pcie_type, flags))
                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
        if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
                pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
        if (pcie_cap_has_sltctl(dev->pcie_type, flags))
                pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
        if (pcie_cap_has_rtctl(dev->pcie_type, flags))
                pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
        if (pcie_cap_has_devctl2(dev->pcie_type, flags))
                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
        if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
                pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
        if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
                pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
}


static int pci_save_pcix_state(struct pci_dev *dev)
{
        int pos;
        struct pci_cap_saved_state *save_state;

        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
        if (pos <= 0)
                return 0;

        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
        if (!save_state) {
                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
                return -ENOMEM;
        }

        pci_read_config_word(dev, pos + PCI_X_CMD,
                             (u16 *)save_state->cap.data);

        return 0;
}

static void pci_restore_pcix_state(struct pci_dev *dev)
{
        int i = 0, pos;
        struct pci_cap_saved_state *save_state;
        u16 *cap;

        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
        if (!save_state || pos <= 0)
                return;
        cap = (u16 *)&save_state->cap.data[0];

        pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
}


/**
 * pci_save_state - save the PCI configuration space of a device before suspending
 * @dev: - PCI device that we're dealing with
 */
int
pci_save_state(struct pci_dev *dev)
{
        int i;
        /* XXX: 100% dword access ok here? */
        for (i = 0; i < 16; i++)
                pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
        dev->state_saved = true;
        if ((i = pci_save_pcie_state(dev)) != 0)
                return i;
        if ((i = pci_save_pcix_state(dev)) != 0)
                return i;
        return 0;
}

/** 
 * pci_restore_state - Restore the saved state of a PCI device
 * @dev: - PCI device that we're dealing with
 */
void pci_restore_state(struct pci_dev *dev)
{
        int i;
        u32 val;

        if (!dev->state_saved)
                return;

        /* PCI Express register must be restored first */
        pci_restore_pcie_state(dev);
        pci_restore_ats_state(dev);

        /*
         * The Base Address register should be programmed before the command
         * register(s)
         */
        for (i = 15; i >= 0; i--) {
                pci_read_config_dword(dev, i * 4, &val);
                if (val != dev->saved_config_space[i]) {
                        dev_dbg(&dev->dev, "restoring config "
                                "space at offset %#x (was %#x, writing %#x)\n",
                                i, val, (int)dev->saved_config_space[i]);
                        pci_write_config_dword(dev,i * 4,
                                dev->saved_config_space[i]);
                }
        }
        pci_restore_pcix_state(dev);
        pci_restore_msi_state(dev);
        pci_restore_iov_state(dev);

        dev->state_saved = false;
}

struct pci_saved_state {
        u32 config_space[16];
        struct pci_cap_saved_data cap[0];
};

/**
 * pci_store_saved_state - Allocate and return an opaque struct containing
 *                         the device saved state.
 * @dev: PCI device that we're dealing with
 *

 * Rerturn NULL if no state or error.
 */
struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
{
        struct pci_saved_state *state;
        struct pci_cap_saved_state *tmp;
        struct pci_cap_saved_data *cap;
        struct hlist_node *pos;
        size_t size;

        if (!dev->state_saved)
                return NULL;

        size = sizeof(*state) + sizeof(struct pci_cap_saved_data);

        hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
                size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;

        state = kzalloc(size, GFP_KERNEL);
        if (!state)
                return NULL;

        memcpy(state->config_space, dev->saved_config_space,
               sizeof(state->config_space));

        cap = state->cap;
        hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
                size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
                memcpy(cap, &tmp->cap, len);
                cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
        }
        /* Empty cap_save terminates list */

        return state;
}
EXPORT_SYMBOL_GPL(pci_store_saved_state);

/**
 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
 * @dev: PCI device that we're dealing with
 * @state: Saved state returned from pci_store_saved_state()
 */
int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
{
        struct pci_cap_saved_data *cap;

        dev->state_saved = false;

        if (!state)
                return 0;

        memcpy(dev->saved_config_space, state->config_space,
               sizeof(state->config_space));

        cap = state->cap;
        while (cap->size) {
                struct pci_cap_saved_state *tmp;

                tmp = pci_find_saved_cap(dev, cap->cap_nr);
                if (!tmp || tmp->cap.size != cap->size)
                        return -EINVAL;

                memcpy(tmp->cap.data, cap->data, tmp->cap.size);
                cap = (struct pci_cap_saved_data *)((u8 *)cap +
                       sizeof(struct pci_cap_saved_data) + cap->size);
        }

        dev->state_saved = true;
        return 0;
}
EXPORT_SYMBOL_GPL(pci_load_saved_state);

/**
 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
 *                                 and free the memory allocated for it.
 * @dev: PCI device that we're dealing with
 * @state: Pointer to saved state returned from pci_store_saved_state()
 */
int pci_load_and_free_saved_state(struct pci_dev *dev,
                                  struct pci_saved_state **state)
{
        int ret = pci_load_saved_state(dev, *state);
        kfree(*state);
        *state = NULL;
        return ret;
}
EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);

static int do_pci_enable_device(struct pci_dev *dev, int bars)
{
        int err;

        err = pci_set_power_state(dev, PCI_D0);
        if (err < 0 && err != -EIO)
                return err;
        err = pcibios_enable_device(dev, bars);
        if (err < 0)
                return err;
        pci_fixup_device(pci_fixup_enable, dev);

        return 0;
}

/**
 * pci_reenable_device - Resume abandoned device
 * @dev: PCI device to be resumed
 *
 *  Note this function is a backend of pci_default_resume and is not supposed
 *  to be called by normal code, write proper resume handler and use it instead.
 */
int pci_reenable_device(struct pci_dev *dev)
{
        if (pci_is_enabled(dev))
                return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
        return 0;
}

static int __pci_enable_device_flags(struct pci_dev *dev,
                                     resource_size_t flags)
{
        int err;
        int i, bars = 0;

        /*
         * Power state could be unknown at this point, either due to a fresh
         * boot or a device removal call.  So get the current power state
         * so that things like MSI message writing will behave as expected
         * (e.g. if the device really is in D0 at enable time).
         */
        if (dev->pm_cap) {
                u16 pmcsr;
                pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
                dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
        }

        if (atomic_add_return(1, &dev->enable_cnt) > 1)
                return 0;               /* already enabled */

        /* only skip sriov related */
        for (i = 0; i <= PCI_ROM_RESOURCE; i++)
                if (dev->resource[i].flags & flags)
                        bars |= (1 << i);
        for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
                if (dev->resource[i].flags & flags)
                        bars |= (1 << i);

        err = do_pci_enable_device(dev, bars);
        if (err < 0)
                atomic_dec(&dev->enable_cnt);
        return err;
}

/**
 * pci_enable_device_io - Initialize a device for use with IO space
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable I/O resources. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 */
int pci_enable_device_io(struct pci_dev *dev)
{
        return __pci_enable_device_flags(dev, IORESOURCE_IO);
}

/**
 * pci_enable_device_mem - Initialize a device for use with Memory space
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable Memory resources. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 */
int pci_enable_device_mem(struct pci_dev *dev)
{
        return __pci_enable_device_flags(dev, IORESOURCE_MEM);
}

/**
 * pci_enable_device - Initialize device before it's used by a driver.
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable I/O and memory. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 *
 *  Note we don't actually enable the device many times if we call
 *  this function repeatedly (we just increment the count).
 */
int pci_enable_device(struct pci_dev *dev)
{
        return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
}

/*
 * Managed PCI resources.  This manages device on/off, intx/msi/msix
 * on/off and BAR regions.  pci_dev itself records msi/msix status, so
 * there's no need to track it separately.  pci_devres is initialized
 * when a device is enabled using managed PCI device enable interface.
 */
struct pci_devres {
        unsigned int enabled:1;
        unsigned int pinned:1;
        unsigned int orig_intx:1;
        unsigned int restore_intx:1;
        u32 region_mask;
};

static void pcim_release(struct device *gendev, void *res)
{
        struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
        struct pci_devres *this = res;
        int i;

        if (dev->msi_enabled)
                pci_disable_msi(dev);
        if (dev->msix_enabled)
                pci_disable_msix(dev);

        for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
                if (this->region_mask & (1 << i))
                        pci_release_region(dev, i);

        if (this->restore_intx)
                pci_intx(dev, this->orig_intx);

        if (this->enabled && !this->pinned)
                pci_disable_device(dev);
}

static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
{
        struct pci_devres *dr, *new_dr;

        dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
        if (dr)
                return dr;

        new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
        if (!new_dr)
                return NULL;
        return devres_get(&pdev->dev, new_dr, NULL, NULL);
}

static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
{
        if (pci_is_managed(pdev))
                return devres_find(&pdev->dev, pcim_release, NULL, NULL);
        return NULL;
}

/**
 * pcim_enable_device - Managed pci_enable_device()
 * @pdev: PCI device to be initialized
 *
 * Managed pci_enable_device().
 */
int pcim_enable_device(struct pci_dev *pdev)
{
        struct pci_devres *dr;
        int rc;

        dr = get_pci_dr(pdev);
        if (unlikely(!dr))
                return -ENOMEM;
        if (dr->enabled)
                return 0;

        rc = pci_enable_device(pdev);
        if (!rc) {
                pdev->is_managed = 1;
                dr->enabled = 1;
        }
        return rc;
}

/**
 * pcim_pin_device - Pin managed PCI device
 * @pdev: PCI device to pin
 *
 * Pin managed PCI device @pdev.  Pinned device won't be disabled on
 * driver detach.  @pdev must have been enabled with
 * pcim_enable_device().
 */
void pcim_pin_device(struct pci_dev *pdev)
{
        struct pci_devres *dr;

        dr = find_pci_dr(pdev);
        WARN_ON(!dr || !dr->enabled);
        if (dr)
                dr->pinned = 1;
}

/**
 * pcibios_disable_device - disable arch specific PCI resources for device dev
 * @dev: the PCI device to disable
 *
 * Disables architecture specific PCI resources for the device. This
 * is the default implementation. Architecture implementations can
 * override this.
 */
void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}

static void do_pci_disable_device(struct pci_dev *dev)
{
        u16 pci_command;

        pci_read_config_word(dev, PCI_COMMAND, &pci_command);
        if (pci_command & PCI_COMMAND_MASTER) {
                pci_command &= ~PCI_COMMAND_MASTER;
                pci_write_config_word(dev, PCI_COMMAND, pci_command);
        }

        pcibios_disable_device(dev);
}

/**
 * pci_disable_enabled_device - Disable device without updating enable_cnt
 * @dev: PCI device to disable
 *
 * NOTE: This function is a backend of PCI power management routines and is
 * not supposed to be called drivers.
 */
void pci_disable_enabled_device(struct pci_dev *dev)
{
        if (pci_is_enabled(dev))
                do_pci_disable_device(dev);
}

/**
 * pci_disable_device - Disable PCI device after use
 * @dev: PCI device to be disabled
 *
 * Signal to the system that the PCI device is not in use by the system
 * anymore.  This only involves disabling PCI bus-mastering, if active.
 *
 * Note we don't actually disable the device until all callers of
 * pci_enable_device() have called pci_disable_device().
 */
void
pci_disable_device(struct pci_dev *dev)
{
        struct pci_devres *dr;

        dr = find_pci_dr(dev);
        if (dr)
                dr->enabled = 0;

        if (atomic_sub_return(1, &dev->enable_cnt) != 0)
                return;

        do_pci_disable_device(dev);

        dev->is_busmaster = 0;
}

/**
 * pcibios_set_pcie_reset_state - set reset state for device dev
 * @dev: the PCIe device reset
 * @state: Reset state to enter into
 *
 *
 * Sets the PCIe reset state for the device. This is the default
 * implementation. Architecture implementations can override this.
 */
int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
                                                        enum pcie_reset_state state)
{
        return -EINVAL;
}

/**
 * pci_set_pcie_reset_state - set reset state for device dev
 * @dev: the PCIe device reset
 * @state: Reset state to enter into
 *
 *
 * Sets the PCI reset state for the device.
 */
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
{
        return pcibios_set_pcie_reset_state(dev, state);
}

/**
 * pci_check_pme_status - Check if given device has generated PME.
 * @dev: Device to check.
 *
 * Check the PME status of the device and if set, clear it and clear PME enable
 * (if set).  Return 'true' if PME status and PME enable were both set or
 * 'false' otherwise.
 */
bool pci_check_pme_status(struct pci_dev *dev)
{
        int pmcsr_pos;
        u16 pmcsr;
        bool ret = false;

        if (!dev->pm_cap)
                return false;

        pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
        pci_read_config_word(dev, pmcsr_pos, &pmcsr);
        if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
                return false;

        /* Clear PME status. */
        pmcsr |= PCI_PM_CTRL_PME_STATUS;
        if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
                /* Disable PME to avoid interrupt flood. */
                pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
                ret = true;
        }

        pci_write_config_word(dev, pmcsr_pos, pmcsr);

        return ret;
}

/**
 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
 * @dev: Device to handle.
 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
 *
 * Check if @dev has generated PME and queue a resume request for it in that
 * case.
 */
static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
{
        if (pme_poll_reset && dev->pme_poll)
                dev->pme_poll = false;

        if (pci_check_pme_status(dev)) {
                pci_wakeup_event(dev);
                pm_request_resume(&dev->dev);
        }
        return 0;
}

/**
 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
 * @bus: Top bus of the subtree to walk.
 */
void pci_pme_wakeup_bus(struct pci_bus *bus)
{
        if (bus)
                pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
}

/**
 * pci_pme_capable - check the capability of PCI device to generate PME#
 * @dev: PCI device to handle.
 * @state: PCI state from which device will issue PME#.
 */
bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
{
        if (!dev->pm_cap)
                return false;

        return !!(dev->pme_support & (1 << state));
}

static void pci_pme_list_scan(struct work_struct *work)
{
        struct pci_pme_device *pme_dev, *n;

        mutex_lock(&pci_pme_list_mutex);
        if (!list_empty(&pci_pme_list)) {
                list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
                        if (pme_dev->dev->pme_poll) {
                                pci_pme_wakeup(pme_dev->dev, NULL);
                        } else {
                                list_del(&pme_dev->list);
                                kfree(pme_dev);
                        }
                }
                if (!list_empty(&pci_pme_list))
                        schedule_delayed_work(&pci_pme_work,
                                              msecs_to_jiffies(PME_TIMEOUT));
        }
        mutex_unlock(&pci_pme_list_mutex);
}

/**
 * pci_pme_active - enable or disable PCI device's PME# function
 * @dev: PCI device to handle.
 * @enable: 'true' to enable PME# generation; 'false' to disable it.
 *
 * The caller must verify that the device is capable of generating PME# before
 * calling this function with @enable equal to 'true'.
 */
void pci_pme_active(struct pci_dev *dev, bool enable)
{
        u16 pmcsr;

        if (!dev->pm_cap)
                return;

        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
        /* Clear PME_Status by writing 1 to it and enable PME# */
        pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
        if (!enable)
                pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;

        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);

        /* PCI (as opposed to PCIe) PME requires that the device have
           its PME# line hooked up correctly. Not all hardware vendors
           do this, so the PME never gets delivered and the device
           remains asleep. The easiest way around this is to
           periodically walk the list of suspended devices and check
           whether any have their PME flag set. The assumption is that
           we'll wake up often enough anyway that this won't be a huge
           hit, and the power savings from the devices will still be a
           win. */

        if (dev->pme_poll) {
                struct pci_pme_device *pme_dev;
                if (enable) {
                        pme_dev = kmalloc(sizeof(struct pci_pme_device),
                                          GFP_KERNEL);
                        if (!pme_dev)
                                goto out;
                        pme_dev->dev = dev;
                        mutex_lock(&pci_pme_list_mutex);
                        list_add(&pme_dev->list, &pci_pme_list);
                        if (list_is_singular(&pci_pme_list))
                                schedule_delayed_work(&pci_pme_work,
                                                      msecs_to_jiffies(PME_TIMEOUT));
                        mutex_unlock(&pci_pme_list_mutex);
                } else {
                        mutex_lock(&pci_pme_list_mutex);
                        list_for_each_entry(pme_dev, &pci_pme_list, list) {
                                if (pme_dev->dev == dev) {
                                        list_del(&pme_dev->list);
                                        kfree(pme_dev);
                                        break;
                                }
                        }
                        mutex_unlock(&pci_pme_list_mutex);
                }
        }

out:
        dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
}

/**
 * __pci_enable_wake - enable PCI device as wakeup event source
 * @dev: PCI device affected
 * @state: PCI state from which device will issue wakeup events
 * @runtime: True if the events are to be generated at run time
 * @enable: True to enable event generation; false to disable
 *
 * This enables the device as a wakeup event source, or disables it.
 * When such events involves platform-specific hooks, those hooks are
 * called automatically by this routine.
 *
 * Devices with legacy power management (no standard PCI PM capabilities)
 * always require such platform hooks.
 *
 * RETURN VALUE:
 * 0 is returned on success
 * -EINVAL is returned if device is not supposed to wake up the system
 * Error code depending on the platform is returned if both the platform and
 * the native mechanism fail to enable the generation of wake-up events
 */
int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
                      bool runtime, bool enable)
{
        int ret = 0;

        if (enable && !runtime && !device_may_wakeup(&dev->dev))
                return -EINVAL;

        /* Don't do the same thing twice in a row for one device. */
        if (!!enable == !!dev->wakeup_prepared)
                return 0;

        /*
         * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
         * Anderson we should be doing PME# wake enable followed by ACPI wake
         * enable.  To disable wake-up we call the platform first, for symmetry.
         */

        if (enable) {
                int error;

                if (pci_pme_capable(dev, state))
                        pci_pme_active(dev, true);
                else
                        ret = 1;
                error = runtime ? platform_pci_run_wake(dev, true) :
                                        platform_pci_sleep_wake(dev, true);
                if (ret)
                        ret = error;
                if (!ret)
                        dev->wakeup_prepared = true;
        } else {
                if (runtime)
                        platform_pci_run_wake(dev, false);
                else
                        platform_pci_sleep_wake(dev, false);
                pci_pme_active(dev, false);
                dev->wakeup_prepared = false;
        }

        return ret;
}
EXPORT_SYMBOL(__pci_enable_wake);

/**
 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
 * @dev: PCI device to prepare
 * @enable: True to enable wake-up event generation; false to disable
 *
 * Many drivers want the device to wake up the system from D3_hot or D3_cold
 * and this function allows them to set that up cleanly - pci_enable_wake()
 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
 * ordering constraints.
 *
 * This function only returns error code if the device is not capable of
 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
 * enable wake-up power for it.
 */
int pci_wake_from_d3(struct pci_dev *dev, bool enable)
{
        return pci_pme_capable(dev, PCI_D3cold) ?
                        pci_enable_wake(dev, PCI_D3cold, enable) :
                        pci_enable_wake(dev, PCI_D3hot, enable);
}

/**
 * pci_target_state - find an appropriate low power state for a given PCI dev
 * @dev: PCI device
 *
 * Use underlying platform code to find a supported low power state for @dev.
 * If the platform can't manage @dev, return the deepest state from which it
 * can generate wake events, based on any available PME info.
 */
pci_power_t pci_target_state(struct pci_dev *dev)
{
        pci_power_t target_state = PCI_D3hot;

        if (platform_pci_power_manageable(dev)) {
                /*
                 * Call the platform to choose the target state of the device
                 * and enable wake-up from this state if supported.
                 */
                pci_power_t state = platform_pci_choose_state(dev);

                switch (state) {
                case PCI_POWER_ERROR:
                case PCI_UNKNOWN:
                        break;
                case PCI_D1:
                case PCI_D2:
                        if (pci_no_d1d2(dev))
                                break;
                default:
                        target_state = state;
                }
        } else if (!dev->pm_cap) {
                target_state = PCI_D0;
        } else if (device_may_wakeup(&dev->dev)) {
                /*
                 * Find the deepest state from which the device can generate
                 * wake-up events, make it the target state and enable device
                 * to generate PME#.
                 */
                if (dev->pme_support) {
                        while (target_state
                              && !(dev->pme_support & (1 << target_state)))
                                target_state--;
                }
        }

        return target_state;
}

/**
 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
 * @dev: Device to handle.
 *
 * Choose the power state appropriate for the device depending on whether
 * it can wake up the system and/or is power manageable by the platform
 * (PCI_D3hot is the default) and put the device into that state.
 */
int pci_prepare_to_sleep(struct pci_dev *dev)
{
        pci_power_t target_state = pci_target_state(dev);
        int error;

        if (target_state == PCI_POWER_ERROR)
                return -EIO;

        pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));

        error = pci_set_power_state(dev, target_state);

        if (error)
                pci_enable_wake(dev, target_state, false);

        return error;
}

/**
 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
 * @dev: Device to handle.
 *
 * Disable device's system wake-up capability and put it into D0.
 */
int pci_back_from_sleep(struct pci_dev *dev)
{
        pci_enable_wake(dev, PCI_D0, false);
        return pci_set_power_state(dev, PCI_D0);
}

/**
 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
 * @dev: PCI device being suspended.
 *
 * Prepare @dev to generate wake-up events at run time and put it into a low
 * power state.
 */
int pci_finish_runtime_suspend(struct pci_dev *dev)
{
        pci_power_t target_state = pci_target_state(dev);
        int error;

        if (target_state == PCI_POWER_ERROR)
                return -EIO;

        __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));

        error = pci_set_power_state(dev, target_state);

        if (error)
                __pci_enable_wake(dev, target_state, true, false);

        return error;
}

/**
 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
 * @dev: Device to check.
 *
 * Return true if the device itself is cabable of generating wake-up events
 * (through the platform or using the native PCIe PME) or if the device supports
 * PME and one of its upstream bridges can generate wake-up events.
 */
bool pci_dev_run_wake(struct pci_dev *dev)
{
        struct pci_bus *bus = dev->bus;

        if (device_run_wake(&dev->dev))
                return true;

        if (!dev->pme_support)
                return false;

        while (bus->parent) {
                struct pci_dev *bridge = bus->self;

                if (device_run_wake(&bridge->dev))
                        return true;

                bus = bus->parent;
        }

        /* We have reached the root bus. */
        if (bus->bridge)
                return device_run_wake(bus->bridge);

        return false;
}
EXPORT_SYMBOL_GPL(pci_dev_run_wake);

/**
 * pci_pm_init - Initialize PM functions of given PCI device
 * @dev: PCI device to handle.
 */
void pci_pm_init(struct pci_dev *dev)
{
        int pm;
        u16 pmc;

        pm_runtime_forbid(&dev->dev);
        device_enable_async_suspend(&dev->dev);
        dev->wakeup_prepared = false;

        dev->pm_cap = 0;

        /* find PCI PM capability in list */
        pm = pci_find_capability(dev, PCI_CAP_ID_PM);
        if (!pm)
                return;
        /* Check device's ability to generate PME# */
        pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);

        if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
                dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
                        pmc & PCI_PM_CAP_VER_MASK);
                return;
        }

        dev->pm_cap = pm;
        dev->d3_delay = PCI_PM_D3_WAIT;

        dev->d1_support = false;
        dev->d2_support = false;
        if (!pci_no_d1d2(dev)) {
                if (pmc & PCI_PM_CAP_D1)
                        dev->d1_support = true;
                if (pmc & PCI_PM_CAP_D2)
                        dev->d2_support = true;

                if (dev->d1_support || dev->d2_support)
                        dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
                                   dev->d1_support ? " D1" : "",
                                   dev->d2_support ? " D2" : "");
        }

        pmc &= PCI_PM_CAP_PME_MASK;
        if (pmc) {
                dev_printk(KERN_DEBUG, &dev->dev,
                         "PME# supported from%s%s%s%s%s\n",
                         (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
                         (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
                         (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
                         (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
                         (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
                dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
                dev->pme_poll = true;
                /*
                 * Make device's PM flags reflect the wake-up capability, but
                 * let the user space enable it to wake up the system as needed.
                 */
                device_set_wakeup_capable(&dev->dev, true);
                /* Disable the PME# generation functionality */
                pci_pme_active(dev, false);
        } else {
                dev->pme_support = 0;
        }
}

/**
 * platform_pci_wakeup_init - init platform wakeup if present
 * @dev: PCI device
 *
 * Some devices don't have PCI PM caps but can still generate wakeup
 * events through platform methods (like ACPI events).  If @dev supports
 * platform wakeup events, set the device flag to indicate as much.  This
 * may be redundant if the device also supports PCI PM caps, but double
 * initialization should be safe in that case.
 */
void platform_pci_wakeup_init(struct pci_dev *dev)
{
        if (!platform_pci_can_wakeup(dev))
                return;

        device_set_wakeup_capable(&dev->dev, true);
        platform_pci_sleep_wake(dev, false);
}

/**
 * pci_add_save_buffer - allocate buffer for saving given capability registers
 * @dev: the PCI device
 * @cap: the capability to allocate the buffer for
 * @size: requested size of the buffer
 */
static int pci_add_cap_save_buffer(
        struct pci_dev *dev, char cap, unsigned int size)
{
        int pos;
        struct pci_cap_saved_state *save_state;

        pos = pci_find_capability(dev, cap);
        if (pos <= 0)
                return 0;

        save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
        if (!save_state)
                return -ENOMEM;

        save_state->cap.cap_nr = cap;
        save_state->cap.size = size;
        pci_add_saved_cap(dev, save_state);

        return 0;
}

/**
 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
 * @dev: the PCI device
 */
void pci_allocate_cap_save_buffers(struct pci_dev *dev)
{
        int error;

        error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
                                        PCI_EXP_SAVE_REGS * sizeof(u16));
        if (error)
                dev_err(&dev->dev,
                        "unable to preallocate PCI Express save buffer\n");

        error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
        if (error)
                dev_err(&dev->dev,
                        "unable to preallocate PCI-X save buffer\n");
}

/**
 * pci_enable_ari - enable ARI forwarding if hardware support it
 * @dev: the PCI device
 */
void pci_enable_ari(struct pci_dev *dev)
{
        int pos;
        u32 cap;
        u16 flags, ctrl;
        struct pci_dev *bridge;

        if (!pci_is_pcie(dev) || dev->devfn)
                return;

        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
        if (!pos)
                return;

        bridge = dev->bus->self;
        if (!bridge || !pci_is_pcie(bridge))
                return;

        pos = pci_pcie_cap(bridge);
        if (!pos)
                return;

        /* ARI is a PCIe v2 feature */
        pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
        if ((flags & PCI_EXP_FLAGS_VERS) < 2)
                return;

        pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
        if (!(cap & PCI_EXP_DEVCAP2_ARI))
                return;

        pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
        ctrl |= PCI_EXP_DEVCTL2_ARI;
        pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);

        bridge->ari_enabled = 1;
}

/**
 * pci_enable_ido - enable ID-based ordering on a device
 * @dev: the PCI device
 * @type: which types of IDO to enable
 *
 * Enable ID-based ordering on @dev.  @type can contain the bits
 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
 * which types of transactions are allowed to be re-ordered.
 */
void pci_enable_ido(struct pci_dev *dev, unsigned long type)
{
        int pos;
        u16 ctrl;

        pos = pci_pcie_cap(dev);
        if (!pos)
                return;

        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
        if (type & PCI_EXP_IDO_REQUEST)
                ctrl |= PCI_EXP_IDO_REQ_EN;
        if (type & PCI_EXP_IDO_COMPLETION)
                ctrl |= PCI_EXP_IDO_CMP_EN;
        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
}
EXPORT_SYMBOL(pci_enable_ido);

/**
 * pci_disable_ido - disable ID-based ordering on a device
 * @dev: the PCI device
 * @type: which types of IDO to disable
 */
void pci_disable_ido(struct pci_dev *dev, unsigned long type)
{
        int pos;
        u16 ctrl;

        if (!pci_is_pcie(dev))
                return;

        pos = pci_pcie_cap(dev);
        if (!pos)
                return;

        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);