linux/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
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   1===================================================================
   2Debug Control and Status Register (DCSR) Binding
   3Copyright 2011 Freescale Semiconductor Inc.
   4
   5NOTE: The bindings described in this document are preliminary and subject
   6to change.  Some of the compatible strings that contain only generic names
   7may turn out to be inappropriate, or need additional properties to describe
   8the integration of the block with the rest of the chip.
   9
  10=====================================================================
  11Debug Control and Status Register Memory Map
  12
  13Description
  14
  15This node defines the base address and range for the
  16defined DCSR Memory Map. Child nodes will describe the individual
  17debug blocks defined within this memory space.
  18
  19PROPERTIES
  20
  21        - compatible
  22        Usage: required
  23        Value type: <string>
  24        Definition: Must include "fsl,dcsr" and "simple-bus".
  25        The DCSR space exists in the memory-mapped bus.
  26
  27        - #address-cells
  28        Usage: required
  29        Value type: <u32>
  30        Definition: A standard property.  Defines the number of cells
  31        or representing physical addresses in child nodes.
  32
  33        - #size-cells
  34        Usage: required
  35        Value type: <u32>
  36        Definition: A standard property.  Defines the number of cells
  37        or representing the size of physical addresses in
  38        child nodes.
  39
  40        - ranges
  41        Usage: required
  42        Value type: <prop-encoded-array>
  43        Definition: A standard property. Specifies the physical address
  44        range of the DCSR space.
  45
  46EXAMPLE
  47        dcsr: dcsr@f00000000 {
  48                #address-cells = <1>;
  49                #size-cells = <1>;
  50                compatible = "fsl,dcsr", "simple-bus";
  51                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  52        };
  53
  54=====================================================================
  55Event Processing Unit
  56
  57This node represents the region of DCSR space allocated to the EPU
  58
  59PROPERTIES
  60
  61        - compatible
  62        Usage: required
  63        Value type: <string>
  64        Definition: Must include "fsl,dcsr-epu"
  65
  66        - interrupts
  67        Usage: required
  68        Value type: <prop_encoded-array>
  69        Definition:  Specifies the interrupts generated by the EPU.
  70        The value of the interrupts property consists of three
  71        interrupt specifiers. The format of the specifier is defined
  72        by the binding document describing the node's interrupt parent.
  73
  74        The EPU counters can be configured to assert the performance
  75        monitor interrupt signal based on either counter overflow or value
  76        match. Which counter asserted the interrupt is captured in an EPU
  77        Counter Interrupt Status Register (EPCPUISR).
  78
  79        The EPU unit can also be configured to assert either or both of
  80        two interrupt signals based on debug event sources within the SoC.
  81        The interrupt signals are epu_xt_int0 and epu_xt_int1.
  82        Which event source asserted the interrupt is captured in an EPU
  83        Interrupt Status Register (EPISR0,EPISR1).
  84
  85        Interrupt numbers are lised in order (perfmon, event0, event1).
  86
  87        - interrupt-parent
  88        Usage: required
  89        Value type: <phandle>
  90        Definition: A single <phandle> value that points
  91        to the interrupt parent to which the child domain
  92        is being mapped. Value must be "&mpic"
  93
  94        - reg
  95        Usage: required
  96        Value type: <prop-encoded-array>
  97        Definition: A standard property.  Specifies the physical address
  98        offset and length of the DCSR space registers of the device
  99        configuration block.
 100
 101EXAMPLE
 102        dcsr-epu@0 {
 103                compatible = "fsl,dcsr-epu";
 104                interrupts = <52 2 0 0
 105                              84 2 0 0
 106                              85 2 0 0>;
 107                interrupt-parent = <&mpic>;
 108                reg = <0x0 0x1000>;
 109        };
 110
 111=======================================================================
 112Nexus Port Controller
 113
 114This node represents the region of DCSR space allocated to the NPC
 115
 116PROPERTIES
 117
 118        - compatible
 119        Usage: required
 120        Value type: <string>
 121        Definition: Must include "fsl,dcsr-npc"
 122
 123        - reg
 124        Usage: required
 125        Value type: <prop-encoded-array>
 126        Definition: A standard property.  Specifies the physical address
 127        offset and length of the DCSR space registers of the device
 128        configuration block.
 129        The Nexus Port controller occupies two regions in the DCSR space
 130        with distinct functionality.
 131
 132        The first register range describes the Nexus Port Controller
 133        control and status registers.
 134
 135        The second register range describes the Nexus Port Controller
 136        internal trace buffer. The NPC trace buffer is a small memory buffer
 137        which stages the nexus trace data for transmission via the Aurora port
 138        or to a DDR based trace buffer. In some configurations the NPC trace
 139        buffer can be the only trace buffer used.
 140
 141
 142EXAMPLE
 143                dcsr-npc {
 144                        compatible = "fsl,dcsr-npc";
 145                        reg = <0x1000 0x1000 0x1000000 0x8000>;
 146                };
 147
 148=======================================================================
 149Nexus Concentrator
 150
 151This node represents the region of DCSR space allocated to the NXC
 152
 153PROPERTIES
 154
 155        - compatible
 156        Usage: required
 157        Value type: <string>
 158        Definition: Must include "fsl,dcsr-nxc"
 159
 160        - reg
 161        Usage: required
 162        Value type: <prop-encoded-array>
 163        Definition: A standard property.  Specifies the physical address
 164        offset and length of the DCSR space registers of the device
 165        configuration block.
 166
 167EXAMPLE
 168                dcsr-nxc@2000 {
 169                        compatible = "fsl,dcsr-nxc";
 170                        reg = <0x2000 0x1000>;
 171                };
 172=======================================================================
 173CoreNet Debug Controller
 174
 175This node represents the region of DCSR space allocated to
 176the CoreNet Debug controller.
 177
 178PROPERTIES
 179
 180        - compatible
 181        Usage: required
 182        Value type: <string>
 183        Definition: Must include "fsl,dcsr-corenet"
 184
 185        - reg
 186        Usage: required
 187        Value type: <prop-encoded-array>
 188        Definition: A standard property.  Specifies the physical address
 189        offset and length of the DCSR space registers of the device
 190        configuration block.
 191        The CoreNet Debug controller occupies two regions in the DCSR space
 192        with distinct functionality.
 193
 194        The first register range describes the CoreNet Debug Controller
 195        functionalty to perform transaction and transaction attribute matches.
 196
 197        The second register range describes the CoreNet Debug Controller
 198        functionalty to trigger event notifications and debug traces.
 199
 200EXAMPLE
 201                dcsr-corenet {
 202                        compatible = "fsl,dcsr-corenet";
 203                        reg = <0x8000 0x1000 0xB0000 0x1000>;
 204                };
 205
 206=======================================================================
 207Data Path Debug controller
 208
 209This node represents the region of DCSR space allocated to
 210the DPAA Debug Controller. This controller controls debug configuration
 211for the QMAN and FMAN blocks.
 212
 213PROPERTIES
 214
 215        - compatible
 216        Usage: required
 217        Value type: <string>
 218        Definition: Must include both an identifier specific to the SoC
 219        or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
 220        generic compatible string "fsl,dcsr-dpaa".
 221
 222        - reg
 223        Usage: required
 224        Value type: <prop-encoded-array>
 225        Definition: A standard property.  Specifies the physical address
 226        offset and length of the DCSR space registers of the device
 227        configuration block.
 228
 229EXAMPLE
 230                dcsr-dpaa@9000 {
 231                        compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
 232                        reg = <0x9000 0x1000>;
 233                };
 234
 235=======================================================================
 236OCeaN Debug controller
 237
 238This node represents the region of DCSR space allocated to
 239the OCN Debug Controller.
 240
 241PROPERTIES
 242
 243        - compatible
 244        Usage: required
 245        Value type: <string>
 246        Definition: Must include both an identifier specific to the SoC
 247        or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
 248        generic compatible string "fsl,dcsr-ocn".
 249
 250        - reg
 251        Usage: required
 252        Value type: <prop-encoded-array>
 253        Definition: A standard property.  Specifies the physical address
 254        offset and length of the DCSR space registers of the device
 255        configuration block.
 256
 257EXAMPLE
 258                dcsr-ocn@11000 {
 259                        compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
 260                        reg = <0x11000 0x1000>;
 261                };
 262
 263=======================================================================
 264DDR Controller Debug controller
 265
 266This node represents the region of DCSR space allocated to
 267the OCN Debug Controller.
 268
 269PROPERTIES
 270
 271        - compatible
 272        Usage: required
 273        Value type: <string>
 274        Definition: Must include "fsl,dcsr-ddr"
 275
 276        - dev-handle
 277        Usage: required
 278        Definition: A phandle to associate this debug node with its
 279        component controller.
 280
 281        - reg
 282        Usage: required
 283        Value type: <prop-encoded-array>
 284        Definition: A standard property.  Specifies the physical address
 285        offset and length of the DCSR space registers of the device
 286        configuration block.
 287
 288EXAMPLE
 289                dcsr-ddr@12000 {
 290                        compatible = "fsl,dcsr-ddr";
 291                        dev-handle = <&ddr1>;
 292                        reg = <0x12000 0x1000>;
 293                };
 294
 295=======================================================================
 296Nexus Aurora Link Controller
 297
 298This node represents the region of DCSR space allocated to
 299the NAL Controller.
 300
 301PROPERTIES
 302
 303        - compatible
 304        Usage: required
 305        Value type: <string>
 306        Definition: Must include both an identifier specific to the SoC
 307        or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
 308        generic compatible string "fsl,dcsr-nal".
 309
 310        - reg
 311        Usage: required
 312        Value type: <prop-encoded-array>
 313        Definition: A standard property.  Specifies the physical address
 314        offset and length of the DCSR space registers of the device
 315        configuration block.
 316
 317EXAMPLE
 318                dcsr-nal@18000 {
 319                        compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
 320                        reg = <0x18000 0x1000>;
 321                };
 322
 323
 324=======================================================================
 325Run Control and Power Management
 326
 327This node represents the region of DCSR space allocated to
 328the RCPM Debug Controller. This functionlity is limited to the
 329control the debug operations of the SoC and cores.
 330
 331PROPERTIES
 332
 333        - compatible
 334        Usage: required
 335        Value type: <string>
 336        Definition: Must include both an identifier specific to the SoC
 337        or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
 338        generic compatible string "fsl,dcsr-rcpm".
 339
 340        - reg
 341        Usage: required
 342        Value type: <prop-encoded-array>
 343        Definition: A standard property.  Specifies the physical address
 344        offset and length of the DCSR space registers of the device
 345        configuration block.
 346
 347EXAMPLE
 348                dcsr-rcpm@22000 {
 349                        compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
 350                        reg = <0x22000 0x1000>;
 351                };
 352
 353=======================================================================
 354Core Service Bridge Proxy
 355
 356This node represents the region of DCSR space allocated to
 357the Core Service Bridge Proxies.
 358There is one Core Service Bridge Proxy device for each CPU in the system.
 359This functionlity provides access to the debug operations of the CPU.
 360
 361PROPERTIES
 362
 363        - compatible
 364        Usage: required
 365        Value type: <string>
 366        Definition: Must include both an identifier specific to the cpu
 367        of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
 368        generic compatible string "fsl,dcsr-cpu-sb-proxy".
 369
 370        - cpu-handle
 371        Usage: required
 372        Definition: A phandle to associate this debug node with its cpu.
 373
 374        - reg
 375        Usage: required
 376        Value type: <prop-encoded-array>
 377        Definition: A standard property.  Specifies the physical address
 378        offset and length of the DCSR space registers of the device
 379        configuration block.
 380
 381EXAMPLE
 382                dcsr-cpu-sb-proxy@40000 {
 383                        compatible = "fsl,dcsr-e500mc-sb-proxy",
 384                                     "fsl,dcsr-cpu-sb-proxy";
 385                        cpu-handle = <&cpu0>;
 386                        reg = <0x40000 0x1000>;
 387                };
 388                dcsr-cpu-sb-proxy@41000 {
 389                        compatible = "fsl,dcsr-e500mc-sb-proxy",
 390                                     "fsl,dcsr-cpu-sb-proxy";
 391                        cpu-handle = <&cpu1>;
 392                        reg = <0x41000 0x1000>;
 393                };
 394
 395=======================================================================
 396