1Freescale Reference Board Bindings 2 3This document describes device tree bindings for various devices that 4exist on some Freescale reference boards. 5 6* Board Control and Status (BCSR) 7 8Required properties: 9 10 - compatible : Should be "fsl,<board>-bcsr" 11 - reg : Offset and length of the register set for the device 12 13Example: 14 15 bcsr@f8000000 { 16 compatible = "fsl,mpc8360mds-bcsr"; 17 reg = <f8000000 8000>; 18 }; 19 20* Freescale on-board FPGA 21 22This is the memory-mapped registers for on board FPGA. 23 24Required properities: 25- compatible: should be a board-specific string followed by a string 26 indicating the type of FPGA. Example: 27 "fsl,<board>-fpga", "fsl,fpga-pixis" 28- reg: should contain the address and the length of the FPGA register set. 29- interrupt-parent: should specify phandle for the interrupt controller. 30- interrupts: should specify event (wakeup) IRQ. 31 32Example (P1022DS): 33 34 board-control@3,0 { 35 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis"; 36 reg = <3 0 0x30>; 37 interrupt-parent = <&mpic>; 38 interrupts = <8 8 0 0>; 39 }; 40 41* Freescale BCSR GPIO banks 42 43Some BCSR registers act as simple GPIO controllers, each such 44register can be represented by the gpio-controller node. 45 46Required properities: 47- compatible : Should be "fsl,<board>-bcsr-gpio". 48- reg : Should contain the address and the length of the GPIO bank 49 register. 50- #gpio-cells : Should be two. The first cell is the pin number and the 51 second cell is used to specify optional parameters (currently unused). 52- gpio-controller : Marks the port as GPIO controller. 53 54Example: 55 56 bcsr@1,0 { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 compatible = "fsl,mpc8360mds-bcsr"; 60 reg = <1 0 0x8000>; 61 ranges = <0 1 0 0x8000>; 62 63 bcsr13: gpio-controller@d { 64 #gpio-cells = <2>; 65 compatible = "fsl,mpc8360mds-bcsr-gpio"; 66 reg = <0xd 1>; 67 gpio-controller; 68 }; 69 }; 70