1* Allwinner A1X Pin Controller 2 3The pins controlled by sunXi pin controller are organized in banks, 4each bank has 32 pins. Each pin has 7 multiplexing functions, with 5the first two functions being GPIO in and out. The configuration on 6the pins includes drive strength and pull-up. 7 8Required properties: 9- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are: 10 sun5i-a13. 11- reg: Should contain the register physical address and length for the 12 pin controller. 13 14Please refer to pinctrl-bindings.txt in this directory for details of the 15common pinctrl bindings used by client devices. 16 17A pinctrl node should contain at least one subnodes representing the 18pinctrl groups available on the machine. Each subnode will list the 19pins it needs, and how they should be configured, with regard to muxer 20configuration, drive strength and pullups. If one of these options is 21not set, its actual value will be unspecified. 22 23Required subnode-properties: 24 25- allwinner,pins: List of strings containing the pin name. 26- allwinner,function: Function to mux the pins listed above to. 27 28Optional subnode-properties: 29- allwinner,drive: Integer. Represents the current sent to the pin 30 0: 10 mA 31 1: 20 mA 32 2: 30 mA 33 3: 40 mA 34- allwinner,pull: Integer. 35 0: No resistor 36 1: Pull-up resistor 37 2: Pull-down resistor 38 39Examples: 40 41pinctrl@01c20800 { 42 compatible = "allwinner,sun5i-a13-pinctrl"; 43 reg = <0x01c20800 0x400>; 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 uart1_pins_a: uart1@0 { 48 allwinner,pins = "PE10", "PE11"; 49 allwinner,function = "uart1"; 50 allwinner,drive = <0>; 51 allwinner,pull = <0>; 52 }; 53 54 uart1_pins_b: uart1@1 { 55 allwinner,pins = "PG3", "PG4"; 56 allwinner,function = "uart1"; 57 allwinner,drive = <0>; 58 allwinner,pull = <0>; 59 }; 60}; 61