1* Marvell PXA GPIO controller 2 3Required properties: 4- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio", 5 "intel,pxa27x-gpio", "intel,pxa3xx-gpio", 6 "marvell,pxa93x-gpio", "marvell,mmp-gpio" or 7 "marvell,mmp2-gpio". 8- reg : Address and length of the register set for the device 9- interrupts : Should be the port interrupt shared by all gpio pins. 10 There're three gpio interrupts in arch-pxa, and they're gpio0, 11 gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp, 12 gpio_mux. 13- interrupt-name : Should be the name of irq resource. Each interrupt 14 binds its interrupt-name. 15- interrupt-controller : Identifies the node as an interrupt controller. 16- #interrupt-cells: Specifies the number of cells needed to encode an 17 interrupt source. 18- gpio-controller : Marks the device node as a gpio controller. 19- #gpio-cells : Should be one. It is the pin number. 20 21Example: 22 23 gpio: gpio@d4019000 { 24 compatible = "marvell,mmp-gpio"; 25 reg = <0xd4019000 0x1000>; 26 interrupts = <49>; 27 interrupt-name = "gpio_mux"; 28 gpio-controller; 29 #gpio-cells = <1>; 30 interrupt-controller; 31 #interrupt-cells = <1>; 32 }; 33 34* Marvell Orion GPIO Controller 35 36Required properties: 37- compatible : Should be "marvell,orion-gpio" 38- reg : Address and length of the register set for controller. 39- gpio-controller : So we know this is a gpio controller. 40- ngpio : How many gpios this controller has. 41- interrupts : Up to 4 Interrupts for the controller. 42 43Optional properties: 44- mask-offset : For SMP Orions, offset for Nth CPU 45 46Example: 47 48 gpio0: gpio@10100 { 49 compatible = "marvell,orion-gpio"; 50 #gpio-cells = <2>; 51 gpio-controller; 52 reg = <0x10100 0x40>; 53 ngpio = <32>; 54 interrupts = <35>, <36>, <37>, <38>; 55 }; 56