linux/arch/powerpc/sysdev/mpic.c
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   1/*
   2 *  arch/powerpc/kernel/mpic.c
   3 *
   4 *  Driver for interrupt controllers following the OpenPIC standard, the
   5 *  common implementation beeing IBM's MPIC. This driver also can deal
   6 *  with various broken implementations of this HW.
   7 *
   8 *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9 *  Copyright 2010-2012 Freescale Semiconductor, Inc.
  10 *
  11 *  This file is subject to the terms and conditions of the GNU General Public
  12 *  License.  See the file COPYING in the main directory of this archive
  13 *  for more details.
  14 */
  15
  16#undef DEBUG
  17#undef DEBUG_IPI
  18#undef DEBUG_IRQ
  19#undef DEBUG_LOW
  20
  21#include <linux/types.h>
  22#include <linux/kernel.h>
  23#include <linux/init.h>
  24#include <linux/irq.h>
  25#include <linux/smp.h>
  26#include <linux/interrupt.h>
  27#include <linux/bootmem.h>
  28#include <linux/spinlock.h>
  29#include <linux/pci.h>
  30#include <linux/slab.h>
  31#include <linux/syscore_ops.h>
  32#include <linux/ratelimit.h>
  33
  34#include <asm/ptrace.h>
  35#include <asm/signal.h>
  36#include <asm/io.h>
  37#include <asm/pgtable.h>
  38#include <asm/irq.h>
  39#include <asm/machdep.h>
  40#include <asm/mpic.h>
  41#include <asm/smp.h>
  42
  43#include "mpic.h"
  44
  45#ifdef DEBUG
  46#define DBG(fmt...) printk(fmt)
  47#else
  48#define DBG(fmt...)
  49#endif
  50
  51struct bus_type mpic_subsys = {
  52        .name = "mpic",
  53        .dev_name = "mpic",
  54};
  55EXPORT_SYMBOL_GPL(mpic_subsys);
  56
  57static struct mpic *mpics;
  58static struct mpic *mpic_primary;
  59static DEFINE_RAW_SPINLOCK(mpic_lock);
  60
  61#ifdef CONFIG_PPC32     /* XXX for now */
  62#ifdef CONFIG_IRQ_ALL_CPUS
  63#define distribute_irqs (1)
  64#else
  65#define distribute_irqs (0)
  66#endif
  67#endif
  68
  69#ifdef CONFIG_MPIC_WEIRD
  70static u32 mpic_infos[][MPIC_IDX_END] = {
  71        [0] = { /* Original OpenPIC compatible MPIC */
  72                MPIC_GREG_BASE,
  73                MPIC_GREG_FEATURE_0,
  74                MPIC_GREG_GLOBAL_CONF_0,
  75                MPIC_GREG_VENDOR_ID,
  76                MPIC_GREG_IPI_VECTOR_PRI_0,
  77                MPIC_GREG_IPI_STRIDE,
  78                MPIC_GREG_SPURIOUS,
  79                MPIC_GREG_TIMER_FREQ,
  80
  81                MPIC_TIMER_BASE,
  82                MPIC_TIMER_STRIDE,
  83                MPIC_TIMER_CURRENT_CNT,
  84                MPIC_TIMER_BASE_CNT,
  85                MPIC_TIMER_VECTOR_PRI,
  86                MPIC_TIMER_DESTINATION,
  87
  88                MPIC_CPU_BASE,
  89                MPIC_CPU_STRIDE,
  90                MPIC_CPU_IPI_DISPATCH_0,
  91                MPIC_CPU_IPI_DISPATCH_STRIDE,
  92                MPIC_CPU_CURRENT_TASK_PRI,
  93                MPIC_CPU_WHOAMI,
  94                MPIC_CPU_INTACK,
  95                MPIC_CPU_EOI,
  96                MPIC_CPU_MCACK,
  97
  98                MPIC_IRQ_BASE,
  99                MPIC_IRQ_STRIDE,
 100                MPIC_IRQ_VECTOR_PRI,
 101                MPIC_VECPRI_VECTOR_MASK,
 102                MPIC_VECPRI_POLARITY_POSITIVE,
 103                MPIC_VECPRI_POLARITY_NEGATIVE,
 104                MPIC_VECPRI_SENSE_LEVEL,
 105                MPIC_VECPRI_SENSE_EDGE,
 106                MPIC_VECPRI_POLARITY_MASK,
 107                MPIC_VECPRI_SENSE_MASK,
 108                MPIC_IRQ_DESTINATION
 109        },
 110        [1] = { /* Tsi108/109 PIC */
 111                TSI108_GREG_BASE,
 112                TSI108_GREG_FEATURE_0,
 113                TSI108_GREG_GLOBAL_CONF_0,
 114                TSI108_GREG_VENDOR_ID,
 115                TSI108_GREG_IPI_VECTOR_PRI_0,
 116                TSI108_GREG_IPI_STRIDE,
 117                TSI108_GREG_SPURIOUS,
 118                TSI108_GREG_TIMER_FREQ,
 119
 120                TSI108_TIMER_BASE,
 121                TSI108_TIMER_STRIDE,
 122                TSI108_TIMER_CURRENT_CNT,
 123                TSI108_TIMER_BASE_CNT,
 124                TSI108_TIMER_VECTOR_PRI,
 125                TSI108_TIMER_DESTINATION,
 126
 127                TSI108_CPU_BASE,
 128                TSI108_CPU_STRIDE,
 129                TSI108_CPU_IPI_DISPATCH_0,
 130                TSI108_CPU_IPI_DISPATCH_STRIDE,
 131                TSI108_CPU_CURRENT_TASK_PRI,
 132                TSI108_CPU_WHOAMI,
 133                TSI108_CPU_INTACK,
 134                TSI108_CPU_EOI,
 135                TSI108_CPU_MCACK,
 136
 137                TSI108_IRQ_BASE,
 138                TSI108_IRQ_STRIDE,
 139                TSI108_IRQ_VECTOR_PRI,
 140                TSI108_VECPRI_VECTOR_MASK,
 141                TSI108_VECPRI_POLARITY_POSITIVE,
 142                TSI108_VECPRI_POLARITY_NEGATIVE,
 143                TSI108_VECPRI_SENSE_LEVEL,
 144                TSI108_VECPRI_SENSE_EDGE,
 145                TSI108_VECPRI_POLARITY_MASK,
 146                TSI108_VECPRI_SENSE_MASK,
 147                TSI108_IRQ_DESTINATION
 148        },
 149};
 150
 151#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 152
 153#else /* CONFIG_MPIC_WEIRD */
 154
 155#define MPIC_INFO(name) MPIC_##name
 156
 157#endif /* CONFIG_MPIC_WEIRD */
 158
 159static inline unsigned int mpic_processor_id(struct mpic *mpic)
 160{
 161        unsigned int cpu = 0;
 162
 163        if (!(mpic->flags & MPIC_SECONDARY))
 164                cpu = hard_smp_processor_id();
 165
 166        return cpu;
 167}
 168
 169/*
 170 * Register accessor functions
 171 */
 172
 173
 174static inline u32 _mpic_read(enum mpic_reg_type type,
 175                             struct mpic_reg_bank *rb,
 176                             unsigned int reg)
 177{
 178        switch(type) {
 179#ifdef CONFIG_PPC_DCR
 180        case mpic_access_dcr:
 181                return dcr_read(rb->dhost, reg);
 182#endif
 183        case mpic_access_mmio_be:
 184                return in_be32(rb->base + (reg >> 2));
 185        case mpic_access_mmio_le:
 186        default:
 187                return in_le32(rb->base + (reg >> 2));
 188        }
 189}
 190
 191static inline void _mpic_write(enum mpic_reg_type type,
 192                               struct mpic_reg_bank *rb,
 193                               unsigned int reg, u32 value)
 194{
 195        switch(type) {
 196#ifdef CONFIG_PPC_DCR
 197        case mpic_access_dcr:
 198                dcr_write(rb->dhost, reg, value);
 199                break;
 200#endif
 201        case mpic_access_mmio_be:
 202                out_be32(rb->base + (reg >> 2), value);
 203                break;
 204        case mpic_access_mmio_le:
 205        default:
 206                out_le32(rb->base + (reg >> 2), value);
 207                break;
 208        }
 209}
 210
 211static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 212{
 213        enum mpic_reg_type type = mpic->reg_type;
 214        unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 215                              (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 216
 217        if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 218                type = mpic_access_mmio_be;
 219        return _mpic_read(type, &mpic->gregs, offset);
 220}
 221
 222static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 223{
 224        unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 225                              (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 226
 227        _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 228}
 229
 230static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
 231{
 232        return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
 233               (tm & 3) * MPIC_INFO(TIMER_STRIDE);
 234}
 235
 236static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
 237{
 238        unsigned int offset = mpic_tm_offset(mpic, tm) +
 239                              MPIC_INFO(TIMER_VECTOR_PRI);
 240
 241        return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
 242}
 243
 244static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
 245{
 246        unsigned int offset = mpic_tm_offset(mpic, tm) +
 247                              MPIC_INFO(TIMER_VECTOR_PRI);
 248
 249        _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
 250}
 251
 252static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 253{
 254        unsigned int cpu = mpic_processor_id(mpic);
 255
 256        return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 257}
 258
 259static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 260{
 261        unsigned int cpu = mpic_processor_id(mpic);
 262
 263        _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 264}
 265
 266static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 267{
 268        unsigned int    isu = src_no >> mpic->isu_shift;
 269        unsigned int    idx = src_no & mpic->isu_mask;
 270        unsigned int    val;
 271
 272        val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
 273                         reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 274#ifdef CONFIG_MPIC_BROKEN_REGREAD
 275        if (reg == 0)
 276                val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
 277                        mpic->isu_reg0_shadow[src_no];
 278#endif
 279        return val;
 280}
 281
 282static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 283                                   unsigned int reg, u32 value)
 284{
 285        unsigned int    isu = src_no >> mpic->isu_shift;
 286        unsigned int    idx = src_no & mpic->isu_mask;
 287
 288        _mpic_write(mpic->reg_type, &mpic->isus[isu],
 289                    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 290
 291#ifdef CONFIG_MPIC_BROKEN_REGREAD
 292        if (reg == 0)
 293                mpic->isu_reg0_shadow[src_no] =
 294                        value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 295#endif
 296}
 297
 298#define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
 299#define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
 300#define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
 301#define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
 302#define mpic_tm_read(i)         _mpic_tm_read(mpic,(i))
 303#define mpic_tm_write(i,v)      _mpic_tm_write(mpic,(i),(v))
 304#define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
 305#define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
 306#define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
 307#define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
 308
 309
 310/*
 311 * Low level utility functions
 312 */
 313
 314
 315static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 316                           struct mpic_reg_bank *rb, unsigned int offset,
 317                           unsigned int size)
 318{
 319        rb->base = ioremap(phys_addr + offset, size);
 320        BUG_ON(rb->base == NULL);
 321}
 322
 323#ifdef CONFIG_PPC_DCR
 324static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
 325                          unsigned int offset, unsigned int size)
 326{
 327        phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
 328        rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
 329        BUG_ON(!DCR_MAP_OK(rb->dhost));
 330}
 331
 332static inline void mpic_map(struct mpic *mpic,
 333                            phys_addr_t phys_addr, struct mpic_reg_bank *rb,
 334                            unsigned int offset, unsigned int size)
 335{
 336        if (mpic->flags & MPIC_USES_DCR)
 337                _mpic_map_dcr(mpic, rb, offset, size);
 338        else
 339                _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 340}
 341#else /* CONFIG_PPC_DCR */
 342#define mpic_map(m,p,b,o,s)     _mpic_map_mmio(m,p,b,o,s)
 343#endif /* !CONFIG_PPC_DCR */
 344
 345
 346
 347/* Check if we have one of those nice broken MPICs with a flipped endian on
 348 * reads from IPI registers
 349 */
 350static void __init mpic_test_broken_ipi(struct mpic *mpic)
 351{
 352        u32 r;
 353
 354        mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 355        r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 356
 357        if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 358                printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 359                mpic->flags |= MPIC_BROKEN_IPI;
 360        }
 361}
 362
 363#ifdef CONFIG_MPIC_U3_HT_IRQS
 364
 365/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 366 * to force the edge setting on the MPIC and do the ack workaround.
 367 */
 368static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 369{
 370        if (source >= 128 || !mpic->fixups)
 371                return 0;
 372        return mpic->fixups[source].base != NULL;
 373}
 374
 375
 376static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 377{
 378        struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 379
 380        if (fixup->applebase) {
 381                unsigned int soff = (fixup->index >> 3) & ~3;
 382                unsigned int mask = 1U << (fixup->index & 0x1f);
 383                writel(mask, fixup->applebase + soff);
 384        } else {
 385                raw_spin_lock(&mpic->fixup_lock);
 386                writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 387                writel(fixup->data, fixup->base + 4);
 388                raw_spin_unlock(&mpic->fixup_lock);
 389        }
 390}
 391
 392static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 393                                      bool level)
 394{
 395        struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 396        unsigned long flags;
 397        u32 tmp;
 398
 399        if (fixup->base == NULL)
 400                return;
 401
 402        DBG("startup_ht_interrupt(0x%x) index: %d\n",
 403            source, fixup->index);
 404        raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 405        /* Enable and configure */
 406        writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 407        tmp = readl(fixup->base + 4);
 408        tmp &= ~(0x23U);
 409        if (level)
 410                tmp |= 0x22;
 411        writel(tmp, fixup->base + 4);
 412        raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 413
 414#ifdef CONFIG_PM
 415        /* use the lowest bit inverted to the actual HW,
 416         * set if this fixup was enabled, clear otherwise */
 417        mpic->save_data[source].fixup_data = tmp | 1;
 418#endif
 419}
 420
 421static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
 422{
 423        struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 424        unsigned long flags;
 425        u32 tmp;
 426
 427        if (fixup->base == NULL)
 428                return;
 429
 430        DBG("shutdown_ht_interrupt(0x%x)\n", source);
 431
 432        /* Disable */
 433        raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 434        writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 435        tmp = readl(fixup->base + 4);
 436        tmp |= 1;
 437        writel(tmp, fixup->base + 4);
 438        raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 439
 440#ifdef CONFIG_PM
 441        /* use the lowest bit inverted to the actual HW,
 442         * set if this fixup was enabled, clear otherwise */
 443        mpic->save_data[source].fixup_data = tmp & ~1;
 444#endif
 445}
 446
 447#ifdef CONFIG_PCI_MSI
 448static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 449                                    unsigned int devfn)
 450{
 451        u8 __iomem *base;
 452        u8 pos, flags;
 453        u64 addr = 0;
 454
 455        for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 456             pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 457                u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 458                if (id == PCI_CAP_ID_HT) {
 459                        id = readb(devbase + pos + 3);
 460                        if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 461                                break;
 462                }
 463        }
 464
 465        if (pos == 0)
 466                return;
 467
 468        base = devbase + pos;
 469
 470        flags = readb(base + HT_MSI_FLAGS);
 471        if (!(flags & HT_MSI_FLAGS_FIXED)) {
 472                addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 473                addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 474        }
 475
 476        printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
 477                PCI_SLOT(devfn), PCI_FUNC(devfn),
 478                flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 479
 480        if (!(flags & HT_MSI_FLAGS_ENABLE))
 481                writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 482}
 483#else
 484static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 485                                    unsigned int devfn)
 486{
 487        return;
 488}
 489#endif
 490
 491static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 492                                    unsigned int devfn, u32 vdid)
 493{
 494        int i, irq, n;
 495        u8 __iomem *base;
 496        u32 tmp;
 497        u8 pos;
 498
 499        for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 500             pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 501                u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 502                if (id == PCI_CAP_ID_HT) {
 503                        id = readb(devbase + pos + 3);
 504                        if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 505                                break;
 506                }
 507        }
 508        if (pos == 0)
 509                return;
 510
 511        base = devbase + pos;
 512        writeb(0x01, base + 2);
 513        n = (readl(base + 4) >> 16) & 0xff;
 514
 515        printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 516               " has %d irqs\n",
 517               devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 518
 519        for (i = 0; i <= n; i++) {
 520                writeb(0x10 + 2 * i, base + 2);
 521                tmp = readl(base + 4);
 522                irq = (tmp >> 16) & 0xff;
 523                DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 524                /* mask it , will be unmasked later */
 525                tmp |= 0x1;
 526                writel(tmp, base + 4);
 527                mpic->fixups[irq].index = i;
 528                mpic->fixups[irq].base = base;
 529                /* Apple HT PIC has a non-standard way of doing EOIs */
 530                if ((vdid & 0xffff) == 0x106b)
 531                        mpic->fixups[irq].applebase = devbase + 0x60;
 532                else
 533                        mpic->fixups[irq].applebase = NULL;
 534                writeb(0x11 + 2 * i, base + 2);
 535                mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 536        }
 537}
 538 
 539
 540static void __init mpic_scan_ht_pics(struct mpic *mpic)
 541{
 542        unsigned int devfn;
 543        u8 __iomem *cfgspace;
 544
 545        printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 546
 547        /* Allocate fixups array */
 548        mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
 549        BUG_ON(mpic->fixups == NULL);
 550
 551        /* Init spinlock */
 552        raw_spin_lock_init(&mpic->fixup_lock);
 553
 554        /* Map U3 config space. We assume all IO-APICs are on the primary bus
 555         * so we only need to map 64kB.
 556         */
 557        cfgspace = ioremap(0xf2000000, 0x10000);
 558        BUG_ON(cfgspace == NULL);
 559
 560        /* Now we scan all slots. We do a very quick scan, we read the header
 561         * type, vendor ID and device ID only, that's plenty enough
 562         */
 563        for (devfn = 0; devfn < 0x100; devfn++) {
 564                u8 __iomem *devbase = cfgspace + (devfn << 8);
 565                u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 566                u32 l = readl(devbase + PCI_VENDOR_ID);
 567                u16 s;
 568
 569                DBG("devfn %x, l: %x\n", devfn, l);
 570
 571                /* If no device, skip */
 572                if (l == 0xffffffff || l == 0x00000000 ||
 573                    l == 0x0000ffff || l == 0xffff0000)
 574                        goto next;
 575                /* Check if is supports capability lists */
 576                s = readw(devbase + PCI_STATUS);
 577                if (!(s & PCI_STATUS_CAP_LIST))
 578                        goto next;
 579
 580                mpic_scan_ht_pic(mpic, devbase, devfn, l);
 581                mpic_scan_ht_msi(mpic, devbase, devfn);
 582
 583        next:
 584                /* next device, if function 0 */
 585                if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 586                        devfn += 7;
 587        }
 588}
 589
 590#else /* CONFIG_MPIC_U3_HT_IRQS */
 591
 592static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 593{
 594        return 0;
 595}
 596
 597static void __init mpic_scan_ht_pics(struct mpic *mpic)
 598{
 599}
 600
 601#endif /* CONFIG_MPIC_U3_HT_IRQS */
 602
 603/* Find an mpic associated with a given linux interrupt */
 604static struct mpic *mpic_find(unsigned int irq)
 605{
 606        if (irq < NUM_ISA_INTERRUPTS)
 607                return NULL;
 608
 609        return irq_get_chip_data(irq);
 610}
 611
 612/* Determine if the linux irq is an IPI */
 613static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
 614{
 615        return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 616}
 617
 618/* Determine if the linux irq is a timer */
 619static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
 620{
 621        return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 622}
 623
 624/* Convert a cpu mask from logical to physical cpu numbers. */
 625static inline u32 mpic_physmask(u32 cpumask)
 626{
 627        int i;
 628        u32 mask = 0;
 629
 630        for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
 631                mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 632        return mask;
 633}
 634
 635#ifdef CONFIG_SMP
 636/* Get the mpic structure from the IPI number */
 637static inline struct mpic * mpic_from_ipi(struct irq_data *d)
 638{
 639        return irq_data_get_irq_chip_data(d);
 640}
 641#endif
 642
 643/* Get the mpic structure from the irq number */
 644static inline struct mpic * mpic_from_irq(unsigned int irq)
 645{
 646        return irq_get_chip_data(irq);
 647}
 648
 649/* Get the mpic structure from the irq data */
 650static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
 651{
 652        return irq_data_get_irq_chip_data(d);
 653}
 654
 655/* Send an EOI */
 656static inline void mpic_eoi(struct mpic *mpic)
 657{
 658        mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 659        (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 660}
 661
 662/*
 663 * Linux descriptor level callbacks
 664 */
 665
 666
 667void mpic_unmask_irq(struct irq_data *d)
 668{
 669        unsigned int loops = 100000;
 670        struct mpic *mpic = mpic_from_irq_data(d);
 671        unsigned int src = irqd_to_hwirq(d);
 672
 673        DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
 674
 675        mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 676                       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 677                       ~MPIC_VECPRI_MASK);
 678        /* make sure mask gets to controller before we return to user */
 679        do {
 680                if (!loops--) {
 681                        printk(KERN_ERR "%s: timeout on hwirq %u\n",
 682                               __func__, src);
 683                        break;
 684                }
 685        } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 686}
 687
 688void mpic_mask_irq(struct irq_data *d)
 689{
 690        unsigned int loops = 100000;
 691        struct mpic *mpic = mpic_from_irq_data(d);
 692        unsigned int src = irqd_to_hwirq(d);
 693
 694        DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
 695
 696        mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 697                       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 698                       MPIC_VECPRI_MASK);
 699
 700        /* make sure mask gets to controller before we return to user */
 701        do {
 702                if (!loops--) {
 703                        printk(KERN_ERR "%s: timeout on hwirq %u\n",
 704                               __func__, src);
 705                        break;
 706                }
 707        } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 708}
 709
 710void mpic_end_irq(struct irq_data *d)
 711{
 712        struct mpic *mpic = mpic_from_irq_data(d);
 713
 714#ifdef DEBUG_IRQ
 715        DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 716#endif
 717        /* We always EOI on end_irq() even for edge interrupts since that
 718         * should only lower the priority, the MPIC should have properly
 719         * latched another edge interrupt coming in anyway
 720         */
 721
 722        mpic_eoi(mpic);
 723}
 724
 725#ifdef CONFIG_MPIC_U3_HT_IRQS
 726
 727static void mpic_unmask_ht_irq(struct irq_data *d)
 728{
 729        struct mpic *mpic = mpic_from_irq_data(d);
 730        unsigned int src = irqd_to_hwirq(d);
 731
 732        mpic_unmask_irq(d);
 733
 734        if (irqd_is_level_type(d))
 735                mpic_ht_end_irq(mpic, src);
 736}
 737
 738static unsigned int mpic_startup_ht_irq(struct irq_data *d)
 739{
 740        struct mpic *mpic = mpic_from_irq_data(d);
 741        unsigned int src = irqd_to_hwirq(d);
 742
 743        mpic_unmask_irq(d);
 744        mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
 745
 746        return 0;
 747}
 748
 749static void mpic_shutdown_ht_irq(struct irq_data *d)
 750{
 751        struct mpic *mpic = mpic_from_irq_data(d);
 752        unsigned int src = irqd_to_hwirq(d);
 753
 754        mpic_shutdown_ht_interrupt(mpic, src);
 755        mpic_mask_irq(d);
 756}
 757
 758static void mpic_end_ht_irq(struct irq_data *d)
 759{
 760        struct mpic *mpic = mpic_from_irq_data(d);
 761        unsigned int src = irqd_to_hwirq(d);
 762
 763#ifdef DEBUG_IRQ
 764        DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 765#endif
 766        /* We always EOI on end_irq() even for edge interrupts since that
 767         * should only lower the priority, the MPIC should have properly
 768         * latched another edge interrupt coming in anyway
 769         */
 770
 771        if (irqd_is_level_type(d))
 772                mpic_ht_end_irq(mpic, src);
 773        mpic_eoi(mpic);
 774}
 775#endif /* !CONFIG_MPIC_U3_HT_IRQS */
 776
 777#ifdef CONFIG_SMP
 778
 779static void mpic_unmask_ipi(struct irq_data *d)
 780{
 781        struct mpic *mpic = mpic_from_ipi(d);
 782        unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
 783
 784        DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
 785        mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 786}
 787
 788static void mpic_mask_ipi(struct irq_data *d)
 789{
 790        /* NEVER disable an IPI... that's just plain wrong! */
 791}
 792
 793static void mpic_end_ipi(struct irq_data *d)
 794{
 795        struct mpic *mpic = mpic_from_ipi(d);
 796
 797        /*
 798         * IPIs are marked IRQ_PER_CPU. This has the side effect of
 799         * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 800         * applying to them. We EOI them late to avoid re-entering.
 801         */
 802        mpic_eoi(mpic);
 803}
 804
 805#endif /* CONFIG_SMP */
 806
 807static void mpic_unmask_tm(struct irq_data *d)
 808{
 809        struct mpic *mpic = mpic_from_irq_data(d);
 810        unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 811
 812        DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
 813        mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
 814        mpic_tm_read(src);
 815}
 816
 817static void mpic_mask_tm(struct irq_data *d)
 818{
 819        struct mpic *mpic = mpic_from_irq_data(d);
 820        unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 821
 822        mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
 823        mpic_tm_read(src);
 824}
 825
 826int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 827                      bool force)
 828{
 829        struct mpic *mpic = mpic_from_irq_data(d);
 830        unsigned int src = irqd_to_hwirq(d);
 831
 832        if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
 833                int cpuid = irq_choose_cpu(cpumask);
 834
 835                mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 836        } else {
 837                u32 mask = cpumask_bits(cpumask)[0];
 838
 839                mask &= cpumask_bits(cpu_online_mask)[0];
 840
 841                mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 842                               mpic_physmask(mask));
 843        }
 844
 845        return IRQ_SET_MASK_OK;
 846}
 847
 848static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 849{
 850        /* Now convert sense value */
 851        switch(type & IRQ_TYPE_SENSE_MASK) {
 852        case IRQ_TYPE_EDGE_RISING:
 853                return MPIC_INFO(VECPRI_SENSE_EDGE) |
 854                       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 855        case IRQ_TYPE_EDGE_FALLING:
 856        case IRQ_TYPE_EDGE_BOTH:
 857                return MPIC_INFO(VECPRI_SENSE_EDGE) |
 858                       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 859        case IRQ_TYPE_LEVEL_HIGH:
 860                return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 861                       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 862        case IRQ_TYPE_LEVEL_LOW:
 863        default:
 864                return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 865                       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 866        }
 867}
 868
 869int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 870{
 871        struct mpic *mpic = mpic_from_irq_data(d);
 872        unsigned int src = irqd_to_hwirq(d);
 873        unsigned int vecpri, vold, vnew;
 874
 875        DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 876            mpic, d->irq, src, flow_type);
 877
 878        if (src >= mpic->num_sources)
 879                return -EINVAL;
 880
 881        vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 882
 883        /* We don't support "none" type */
 884        if (flow_type == IRQ_TYPE_NONE)
 885                flow_type = IRQ_TYPE_DEFAULT;
 886
 887        /* Default: read HW settings */
 888        if (flow_type == IRQ_TYPE_DEFAULT) {
 889                switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
 890                               MPIC_INFO(VECPRI_SENSE_MASK))) {
 891                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
 892                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
 893                                flow_type = IRQ_TYPE_EDGE_RISING;
 894                                break;
 895                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
 896                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
 897                                flow_type = IRQ_TYPE_EDGE_FALLING;
 898                                break;
 899                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
 900                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
 901                                flow_type = IRQ_TYPE_LEVEL_HIGH;
 902                                break;
 903                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
 904                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
 905                                flow_type = IRQ_TYPE_LEVEL_LOW;
 906                                break;
 907                }
 908        }
 909
 910        /* Apply to irq desc */
 911        irqd_set_trigger_type(d, flow_type);
 912
 913        /* Apply to HW */
 914        if (mpic_is_ht_interrupt(mpic, src))
 915                vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 916                        MPIC_VECPRI_SENSE_EDGE;
 917        else
 918                vecpri = mpic_type_to_vecpri(mpic, flow_type);
 919
 920        vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 921                        MPIC_INFO(VECPRI_SENSE_MASK));
 922        vnew |= vecpri;
 923        if (vold != vnew)
 924                mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 925
 926        return IRQ_SET_MASK_OK_NOCOPY;
 927}
 928
 929static int mpic_irq_set_wake(struct irq_data *d, unsigned int on)
 930{
 931        struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
 932        struct mpic *mpic = mpic_from_irq_data(d);
 933
 934        if (!(mpic->flags & MPIC_FSL))
 935                return -ENXIO;
 936
 937        if (on)
 938                desc->action->flags |= IRQF_NO_SUSPEND;
 939        else
 940                desc->action->flags &= ~IRQF_NO_SUSPEND;
 941
 942        return 0;
 943}
 944
 945void mpic_set_vector(unsigned int virq, unsigned int vector)
 946{
 947        struct mpic *mpic = mpic_from_irq(virq);
 948        unsigned int src = virq_to_hw(virq);
 949        unsigned int vecpri;
 950
 951        DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
 952            mpic, virq, src, vector);
 953
 954        if (src >= mpic->num_sources)
 955                return;
 956
 957        vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 958        vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
 959        vecpri |= vector;
 960        mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 961}
 962
 963void mpic_set_destination(unsigned int virq, unsigned int cpuid)
 964{
 965        struct mpic *mpic = mpic_from_irq(virq);
 966        unsigned int src = virq_to_hw(virq);
 967
 968        DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
 969            mpic, virq, src, cpuid);
 970
 971        if (src >= mpic->num_sources)
 972                return;
 973
 974        mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 975}
 976
 977static struct irq_chip mpic_irq_chip = {
 978        .irq_mask       = mpic_mask_irq,
 979        .irq_unmask     = mpic_unmask_irq,
 980        .irq_eoi        = mpic_end_irq,
 981        .irq_set_type   = mpic_set_irq_type,
 982        .irq_set_wake   = mpic_irq_set_wake,
 983};
 984
 985#ifdef CONFIG_SMP
 986static struct irq_chip mpic_ipi_chip = {
 987        .irq_mask       = mpic_mask_ipi,
 988        .irq_unmask     = mpic_unmask_ipi,
 989        .irq_eoi        = mpic_end_ipi,
 990};
 991#endif /* CONFIG_SMP */
 992
 993static struct irq_chip mpic_tm_chip = {
 994        .irq_mask       = mpic_mask_tm,
 995        .irq_unmask     = mpic_unmask_tm,
 996        .irq_eoi        = mpic_end_irq,
 997        .irq_set_wake   = mpic_irq_set_wake,
 998};
 999
1000#ifdef CONFIG_MPIC_U3_HT_IRQS
1001static struct irq_chip mpic_irq_ht_chip = {
1002        .irq_startup    = mpic_startup_ht_irq,
1003        .irq_shutdown   = mpic_shutdown_ht_irq,
1004        .irq_mask       = mpic_mask_irq,
1005        .irq_unmask     = mpic_unmask_ht_irq,
1006        .irq_eoi        = mpic_end_ht_irq,
1007        .irq_set_type   = mpic_set_irq_type,
1008};
1009#endif /* CONFIG_MPIC_U3_HT_IRQS */
1010
1011
1012static int mpic_host_match(struct irq_domain *h, struct device_node *node)
1013{
1014        /* Exact match, unless mpic node is NULL */
1015        return h->of_node == NULL || h->of_node == node;
1016}
1017
1018static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1019                         irq_hw_number_t hw)
1020{
1021        struct mpic *mpic = h->host_data;
1022        struct irq_chip *chip;
1023
1024        DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1025
1026        if (hw == mpic->spurious_vec)
1027                return -EINVAL;
1028        if (mpic->protected && test_bit(hw, mpic->protected)) {
1029                pr_warning("mpic: Mapping of source 0x%x failed, "
1030                           "source protected by firmware !\n",\
1031                           (unsigned int)hw);
1032                return -EPERM;
1033        }
1034
1035#ifdef CONFIG_SMP
1036        else if (hw >= mpic->ipi_vecs[0]) {
1037                WARN_ON(mpic->flags & MPIC_SECONDARY);
1038
1039                DBG("mpic: mapping as IPI\n");
1040                irq_set_chip_data(virq, mpic);
1041                irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1042                                         handle_percpu_irq);
1043                return 0;
1044        }
1045#endif /* CONFIG_SMP */
1046
1047        if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1048                WARN_ON(mpic->flags & MPIC_SECONDARY);
1049
1050                DBG("mpic: mapping as timer\n");
1051                irq_set_chip_data(virq, mpic);
1052                irq_set_chip_and_handler(virq, &mpic->hc_tm,
1053                                         handle_fasteoi_irq);
1054                return 0;
1055        }
1056
1057        if (mpic_map_error_int(mpic, virq, hw))
1058                return 0;
1059
1060        if (hw >= mpic->num_sources) {
1061                pr_warning("mpic: Mapping of source 0x%x failed, "
1062                           "source out of range !\n",\
1063                           (unsigned int)hw);
1064                return -EINVAL;
1065        }
1066
1067        mpic_msi_reserve_hwirq(mpic, hw);
1068
1069        /* Default chip */
1070        chip = &mpic->hc_irq;
1071
1072#ifdef CONFIG_MPIC_U3_HT_IRQS
1073        /* Check for HT interrupts, override vecpri */
1074        if (mpic_is_ht_interrupt(mpic, hw))
1075                chip = &mpic->hc_ht_irq;
1076#endif /* CONFIG_MPIC_U3_HT_IRQS */
1077
1078        DBG("mpic: mapping to irq chip @%p\n", chip);
1079
1080        irq_set_chip_data(virq, mpic);
1081        irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1082
1083        /* Set default irq type */
1084        irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1085
1086        /* If the MPIC was reset, then all vectors have already been
1087         * initialized.  Otherwise, a per source lazy initialization
1088         * is done here.
1089         */
1090        if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1091                mpic_set_vector(virq, hw);
1092                mpic_set_destination(virq, mpic_processor_id(mpic));
1093                mpic_irq_set_priority(virq, 8);
1094        }
1095
1096        return 0;
1097}
1098
1099static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1100                           const u32 *intspec, unsigned int intsize,
1101                           irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1102
1103{
1104        struct mpic *mpic = h->host_data;
1105        static unsigned char map_mpic_senses[4] = {
1106                IRQ_TYPE_EDGE_RISING,
1107                IRQ_TYPE_LEVEL_LOW,
1108                IRQ_TYPE_LEVEL_HIGH,
1109                IRQ_TYPE_EDGE_FALLING,
1110        };
1111
1112        *out_hwirq = intspec[0];
1113        if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1114                /*
1115                 * Freescale MPIC with extended intspec:
1116                 * First two cells are as usual.  Third specifies
1117                 * an "interrupt type".  Fourth is type-specific data.
1118                 *
1119                 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1120                 */
1121                switch (intspec[2]) {
1122                case 0:
1123                        break;
1124                case 1:
1125                        if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1126                                break;
1127
1128                        if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1129                                return -EINVAL;
1130
1131                        *out_hwirq = mpic->err_int_vecs[intspec[3]];
1132
1133                        break;
1134                case 2:
1135                        if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1136                                return -EINVAL;
1137
1138                        *out_hwirq = mpic->ipi_vecs[intspec[0]];
1139                        break;
1140                case 3:
1141                        if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1142                                return -EINVAL;
1143
1144                        *out_hwirq = mpic->timer_vecs[intspec[0]];
1145                        break;
1146                default:
1147                        pr_debug("%s: unknown irq type %u\n",
1148                                 __func__, intspec[2]);
1149                        return -EINVAL;
1150                }
1151
1152                *out_flags = map_mpic_senses[intspec[1] & 3];
1153        } else if (intsize > 1) {
1154                u32 mask = 0x3;
1155
1156                /* Apple invented a new race of encoding on machines with
1157                 * an HT APIC. They encode, among others, the index within
1158                 * the HT APIC. We don't care about it here since thankfully,
1159                 * it appears that they have the APIC already properly
1160                 * configured, and thus our current fixup code that reads the
1161                 * APIC config works fine. However, we still need to mask out
1162                 * bits in the specifier to make sure we only get bit 0 which
1163                 * is the level/edge bit (the only sense bit exposed by Apple),
1164                 * as their bit 1 means something else.
1165                 */
1166                if (machine_is(powermac))
1167                        mask = 0x1;
1168                *out_flags = map_mpic_senses[intspec[1] & mask];
1169        } else
1170                *out_flags = IRQ_TYPE_NONE;
1171
1172        DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1173            intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1174
1175        return 0;
1176}
1177
1178/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1179static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1180{
1181        struct irq_chip *chip = irq_desc_get_chip(desc);
1182        struct mpic *mpic = irq_desc_get_handler_data(desc);
1183        unsigned int virq;
1184
1185        BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1186
1187        virq = mpic_get_one_irq(mpic);
1188        if (virq)
1189                generic_handle_irq(virq);
1190
1191        chip->irq_eoi(&desc->irq_data);
1192}
1193
1194static struct irq_domain_ops mpic_host_ops = {
1195        .match = mpic_host_match,
1196        .map = mpic_host_map,
1197        .xlate = mpic_host_xlate,
1198};
1199
1200static u32 fsl_mpic_get_version(struct mpic *mpic)
1201{
1202        u32 brr1;
1203
1204        if (!(mpic->flags & MPIC_FSL))
1205                return 0;
1206
1207        brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1208                        MPIC_FSL_BRR1);
1209
1210        return brr1 & MPIC_FSL_BRR1_VER;
1211}
1212
1213/*
1214 * Exported functions
1215 */
1216
1217u32 fsl_mpic_primary_get_version(void)
1218{
1219        struct mpic *mpic = mpic_primary;
1220
1221        if (mpic)
1222                return fsl_mpic_get_version(mpic);
1223
1224        return 0;
1225}
1226
1227struct mpic * __init mpic_alloc(struct device_node *node,
1228                                phys_addr_t phys_addr,
1229                                unsigned int flags,
1230                                unsigned int isu_size,
1231                                unsigned int irq_count,
1232                                const char *name)
1233{
1234        int i, psize, intvec_top;
1235        struct mpic *mpic;
1236        u32 greg_feature;
1237        const char *vers;
1238        const u32 *psrc;
1239        u32 last_irq;
1240        u32 fsl_version = 0;
1241
1242        /* Default MPIC search parameters */
1243        static const struct of_device_id __initconst mpic_device_id[] = {
1244                { .type       = "open-pic", },
1245                { .compatible = "open-pic", },
1246                {},
1247        };
1248
1249        /*
1250         * If we were not passed a device-tree node, then perform the default
1251         * search for standardized a standardized OpenPIC.
1252         */
1253        if (node) {
1254                node = of_node_get(node);
1255        } else {
1256                node = of_find_matching_node(NULL, mpic_device_id);
1257                if (!node)
1258                        return NULL;
1259        }
1260
1261        /* Pick the physical address from the device tree if unspecified */
1262        if (!phys_addr) {
1263                /* Check if it is DCR-based */
1264                if (of_get_property(node, "dcr-reg", NULL)) {
1265                        flags |= MPIC_USES_DCR;
1266                } else {
1267                        struct resource r;
1268                        if (of_address_to_resource(node, 0, &r))
1269                                goto err_of_node_put;
1270                        phys_addr = r.start;
1271                }
1272        }
1273
1274        /* Read extra device-tree properties into the flags variable */
1275        if (of_get_property(node, "big-endian", NULL))
1276                flags |= MPIC_BIG_ENDIAN;
1277        if (of_get_property(node, "pic-no-reset", NULL))
1278                flags |= MPIC_NO_RESET;
1279        if (of_get_property(node, "single-cpu-affinity", NULL))
1280                flags |= MPIC_SINGLE_DEST_CPU;
1281        if (of_device_is_compatible(node, "fsl,mpic"))
1282                flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1283
1284        mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1285        if (mpic == NULL)
1286                goto err_of_node_put;
1287
1288        mpic->name = name;
1289        mpic->node = node;
1290        mpic->paddr = phys_addr;
1291        mpic->flags = flags;
1292
1293        mpic->hc_irq = mpic_irq_chip;
1294        mpic->hc_irq.name = name;
1295        if (!(mpic->flags & MPIC_SECONDARY))
1296                mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1297#ifdef CONFIG_MPIC_U3_HT_IRQS
1298        mpic->hc_ht_irq = mpic_irq_ht_chip;
1299        mpic->hc_ht_irq.name = name;
1300        if (!(mpic->flags & MPIC_SECONDARY))
1301                mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1302#endif /* CONFIG_MPIC_U3_HT_IRQS */
1303
1304#ifdef CONFIG_SMP
1305        mpic->hc_ipi = mpic_ipi_chip;
1306        mpic->hc_ipi.name = name;
1307#endif /* CONFIG_SMP */
1308
1309        mpic->hc_tm = mpic_tm_chip;
1310        mpic->hc_tm.name = name;
1311
1312        mpic->num_sources = 0; /* so far */
1313
1314        if (mpic->flags & MPIC_LARGE_VECTORS)
1315                intvec_top = 2047;
1316        else
1317                intvec_top = 255;
1318
1319        mpic->timer_vecs[0] = intvec_top - 12;
1320        mpic->timer_vecs[1] = intvec_top - 11;
1321        mpic->timer_vecs[2] = intvec_top - 10;
1322        mpic->timer_vecs[3] = intvec_top - 9;
1323        mpic->timer_vecs[4] = intvec_top - 8;
1324        mpic->timer_vecs[5] = intvec_top - 7;
1325        mpic->timer_vecs[6] = intvec_top - 6;
1326        mpic->timer_vecs[7] = intvec_top - 5;
1327        mpic->ipi_vecs[0]   = intvec_top - 4;
1328        mpic->ipi_vecs[1]   = intvec_top - 3;
1329        mpic->ipi_vecs[2]   = intvec_top - 2;
1330        mpic->ipi_vecs[3]   = intvec_top - 1;
1331        mpic->spurious_vec  = intvec_top;
1332
1333        /* Look for protected sources */
1334        psrc = of_get_property(mpic->node, "protected-sources", &psize);
1335        if (psrc) {
1336                /* Allocate a bitmap with one bit per interrupt */
1337                unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1338                mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1339                BUG_ON(mpic->protected == NULL);
1340                for (i = 0; i < psize/sizeof(u32); i++) {
1341                        if (psrc[i] > intvec_top)
1342                                continue;
1343                        __set_bit(psrc[i], mpic->protected);
1344                }
1345        }
1346
1347#ifdef CONFIG_MPIC_WEIRD
1348        mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1349#endif
1350
1351        /* default register type */
1352        if (mpic->flags & MPIC_BIG_ENDIAN)
1353                mpic->reg_type = mpic_access_mmio_be;
1354        else
1355                mpic->reg_type = mpic_access_mmio_le;
1356
1357        /*
1358         * An MPIC with a "dcr-reg" property must be accessed that way, but
1359         * only if the kernel includes DCR support.
1360         */
1361#ifdef CONFIG_PPC_DCR
1362        if (mpic->flags & MPIC_USES_DCR)
1363                mpic->reg_type = mpic_access_dcr;
1364#else
1365        BUG_ON(mpic->flags & MPIC_USES_DCR);
1366#endif
1367
1368        /* Map the global registers */
1369        mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1370        mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1371
1372        if (mpic->flags & MPIC_FSL) {
1373                int ret;
1374
1375                /*
1376                 * Yes, Freescale really did put global registers in the
1377                 * magic per-cpu area -- and they don't even show up in the
1378                 * non-magic per-cpu copies that this driver normally uses.
1379                 */
1380                mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1381                         MPIC_CPU_THISBASE, 0x1000);
1382
1383                fsl_version = fsl_mpic_get_version(mpic);
1384
1385                /* Error interrupt mask register (EIMR) is required for
1386                 * handling individual device error interrupts. EIMR
1387                 * was added in MPIC version 4.1.
1388                 *
1389                 * Over here we reserve vector number space for error
1390                 * interrupt vectors. This space is stolen from the
1391                 * global vector number space, as in case of ipis
1392                 * and timer interrupts.
1393                 *
1394                 * Available vector space = intvec_top - 12, where 12
1395                 * is the number of vectors which have been consumed by
1396                 * ipis and timer interrupts.
1397                 */
1398                if (fsl_version >= 0x401) {
1399                        ret = mpic_setup_error_int(mpic, intvec_top - 12);
1400                        if (ret)
1401                                return NULL;
1402                }
1403
1404        }
1405
1406        /*
1407         * EPR is only available starting with v4.0.  To support
1408         * platforms that don't know the MPIC version at compile-time,
1409         * such as qemu-e500, turn off coreint if this MPIC doesn't
1410         * support it.  Note that we never enable it if it wasn't
1411         * requested in the first place.
1412         *
1413         * This is done outside the MPIC_FSL check, so that we
1414         * also disable coreint if the MPIC node doesn't have
1415         * an "fsl,mpic" compatible at all.  This will be the case
1416         * with device trees generated by older versions of QEMU.
1417         * fsl_version will be zero if MPIC_FSL is not set.
1418         */
1419        if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
1420                WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
1421                ppc_md.get_irq = mpic_get_irq;
1422        }
1423
1424        /* Reset */
1425
1426        /* When using a device-node, reset requests are only honored if the MPIC
1427         * is allowed to reset.
1428         */
1429        if (!(mpic->flags & MPIC_NO_RESET)) {
1430                printk(KERN_DEBUG "mpic: Resetting\n");
1431                mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1432                           mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1433                           | MPIC_GREG_GCONF_RESET);
1434                while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1435                       & MPIC_GREG_GCONF_RESET)
1436                        mb();
1437        }
1438
1439        /* CoreInt */
1440        if (mpic->flags & MPIC_ENABLE_COREINT)
1441                mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1442                           mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1443                           | MPIC_GREG_GCONF_COREINT);
1444
1445        if (mpic->flags & MPIC_ENABLE_MCK)
1446                mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1447                           mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1448                           | MPIC_GREG_GCONF_MCK);
1449
1450        /*
1451         * The MPIC driver will crash if there are more cores than we
1452         * can initialize, so we may as well catch that problem here.
1453         */
1454        BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1455
1456        /* Map the per-CPU registers */
1457        for_each_possible_cpu(i) {
1458                unsigned int cpu = get_hard_smp_processor_id(i);
1459
1460                mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1461                         MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1462                         0x1000);
1463        }
1464
1465        /*
1466         * Read feature register.  For non-ISU MPICs, num sources as well. On
1467         * ISU MPICs, sources are counted as ISUs are added
1468         */
1469        greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1470
1471        /*
1472         * By default, the last source number comes from the MPIC, but the
1473         * device-tree and board support code can override it on buggy hw.
1474         * If we get passed an isu_size (multi-isu MPIC) then we use that
1475         * as a default instead of the value read from the HW.
1476         */
1477        last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1478                                >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;    
1479        if (isu_size)
1480                last_irq = isu_size  * MPIC_MAX_ISU - 1;
1481        of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1482        if (irq_count)
1483                last_irq = irq_count - 1;
1484
1485        /* Initialize main ISU if none provided */
1486        if (!isu_size) {
1487                isu_size = last_irq + 1;
1488                mpic->num_sources = isu_size;
1489                mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1490                                MPIC_INFO(IRQ_BASE),
1491                                MPIC_INFO(IRQ_STRIDE) * isu_size);
1492        }
1493
1494        mpic->isu_size = isu_size;
1495        mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1496        mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1497
1498        mpic->irqhost = irq_domain_add_linear(mpic->node,
1499                                       intvec_top,
1500                                       &mpic_host_ops, mpic);
1501
1502        /*
1503         * FIXME: The code leaks the MPIC object and mappings here; this
1504         * is very unlikely to fail but it ought to be fixed anyways.
1505         */
1506        if (mpic->irqhost == NULL)
1507                return NULL;
1508
1509        /* Display version */
1510        switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1511        case 1:
1512                vers = "1.0";
1513                break;
1514        case 2:
1515                vers = "1.2";
1516                break;
1517        case 3:
1518                vers = "1.3";
1519                break;
1520        default:
1521                vers = "<unknown>";
1522                break;
1523        }
1524        printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1525               " max %d CPUs\n",
1526               name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1527        printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1528               mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1529
1530        mpic->next = mpics;
1531        mpics = mpic;
1532
1533        if (!(mpic->flags & MPIC_SECONDARY)) {
1534                mpic_primary = mpic;
1535                irq_set_default_host(mpic->irqhost);
1536        }
1537
1538        return mpic;
1539
1540err_of_node_put:
1541        of_node_put(node);
1542        return NULL;
1543}
1544
1545void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1546                            phys_addr_t paddr)
1547{
1548        unsigned int isu_first = isu_num * mpic->isu_size;
1549
1550        BUG_ON(isu_num >= MPIC_MAX_ISU);
1551
1552        mpic_map(mpic,
1553                 paddr, &mpic->isus[isu_num], 0,
1554                 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1555
1556        if ((isu_first + mpic->isu_size) > mpic->num_sources)
1557                mpic->num_sources = isu_first + mpic->isu_size;
1558}
1559
1560void __init mpic_init(struct mpic *mpic)
1561{
1562        int i, cpu;
1563        int num_timers = 4;
1564
1565        BUG_ON(mpic->num_sources == 0);
1566
1567        printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1568
1569        /* Set current processor priority to max */
1570        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1571
1572        if (mpic->flags & MPIC_FSL) {
1573                u32 version = fsl_mpic_get_version(mpic);
1574
1575                /*
1576                 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1577                 * mpc8536).  It is not present in MPIC 2.0 (e.g. mpc8544).
1578                 * I don't know about the status of intermediate versions (or
1579                 * whether they even exist).
1580                 */
1581                if (version >= 0x0301)
1582                        num_timers = 8;
1583        }
1584
1585        /* FSL mpic error interrupt intialization */
1586        if (mpic->flags & MPIC_FSL_HAS_EIMR)
1587                mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1588
1589        /* Initialize timers to our reserved vectors and mask them for now */
1590        for (i = 0; i < num_timers; i++) {
1591                unsigned int offset = mpic_tm_offset(mpic, i);
1592
1593                mpic_write(mpic->tmregs,
1594                           offset + MPIC_INFO(TIMER_DESTINATION),
1595                           1 << hard_smp_processor_id());
1596                mpic_write(mpic->tmregs,
1597                           offset + MPIC_INFO(TIMER_VECTOR_PRI),
1598                           MPIC_VECPRI_MASK |
1599                           (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1600                           (mpic->timer_vecs[0] + i));
1601        }
1602
1603        /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1604        mpic_test_broken_ipi(mpic);
1605        for (i = 0; i < 4; i++) {
1606                mpic_ipi_write(i,
1607                               MPIC_VECPRI_MASK |
1608                               (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1609                               (mpic->ipi_vecs[0] + i));
1610        }
1611
1612        /* Do the HT PIC fixups on U3 broken mpic */
1613        DBG("MPIC flags: %x\n", mpic->flags);
1614        if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1615                mpic_scan_ht_pics(mpic);
1616                mpic_u3msi_init(mpic);
1617        }
1618
1619        mpic_pasemi_msi_init(mpic);
1620
1621        cpu = mpic_processor_id(mpic);
1622
1623        if (!(mpic->flags & MPIC_NO_RESET)) {
1624                for (i = 0; i < mpic->num_sources; i++) {
1625                        /* start with vector = source number, and masked */
1626                        u32 vecpri = MPIC_VECPRI_MASK | i |
1627                                (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1628                
1629                        /* check if protected */
1630                        if (mpic->protected && test_bit(i, mpic->protected))
1631                                continue;
1632                        /* init hw */
1633                        mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1634                        mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1635                }
1636        }
1637        
1638        /* Init spurious vector */
1639        mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1640
1641        /* Disable 8259 passthrough, if supported */
1642        if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1643                mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1644                           mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1645                           | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1646
1647        if (mpic->flags & MPIC_NO_BIAS)
1648                mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1649                        mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1650                        | MPIC_GREG_GCONF_NO_BIAS);
1651
1652        /* Set current processor priority to 0 */
1653        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1654
1655#ifdef CONFIG_PM
1656        /* allocate memory to save mpic state */
1657        mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1658                                  GFP_KERNEL);
1659        BUG_ON(mpic->save_data == NULL);
1660#endif
1661
1662        /* Check if this MPIC is chained from a parent interrupt controller */
1663        if (mpic->flags & MPIC_SECONDARY) {
1664                int virq = irq_of_parse_and_map(mpic->node, 0);
1665                if (virq != NO_IRQ) {
1666                        printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1667                                        mpic->node->full_name, virq);
1668                        irq_set_handler_data(virq, mpic);
1669                        irq_set_chained_handler(virq, &mpic_cascade);
1670                }
1671        }
1672}
1673
1674void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1675{
1676        u32 v;
1677
1678        v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1679        v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1680        v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1681        mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1682}
1683
1684void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1685{
1686        unsigned long flags;
1687        u32 v;
1688
1689        raw_spin_lock_irqsave(&mpic_lock, flags);
1690        v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1691        if (enable)
1692                v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1693        else
1694                v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1695        mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1696        raw_spin_unlock_irqrestore(&mpic_lock, flags);
1697}
1698
1699void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1700{
1701        struct mpic *mpic = mpic_find(irq);
1702        unsigned int src = virq_to_hw(irq);
1703        unsigned long flags;
1704        u32 reg;
1705
1706        if (!mpic)
1707                return;
1708
1709        raw_spin_lock_irqsave(&mpic_lock, flags);
1710        if (mpic_is_ipi(mpic, src)) {
1711                reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1712                        ~MPIC_VECPRI_PRIORITY_MASK;
1713                mpic_ipi_write(src - mpic->ipi_vecs[0],
1714                               reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1715        } else if (mpic_is_tm(mpic, src)) {
1716                reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1717                        ~MPIC_VECPRI_PRIORITY_MASK;
1718                mpic_tm_write(src - mpic->timer_vecs[0],
1719                              reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1720        } else {
1721                reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1722                        & ~MPIC_VECPRI_PRIORITY_MASK;
1723                mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1724                               reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1725        }
1726        raw_spin_unlock_irqrestore(&mpic_lock, flags);
1727}
1728
1729void mpic_setup_this_cpu(void)
1730{
1731#ifdef CONFIG_SMP
1732        struct mpic *mpic = mpic_primary;
1733        unsigned long flags;
1734        u32 msk = 1 << hard_smp_processor_id();
1735        unsigned int i;
1736
1737        BUG_ON(mpic == NULL);
1738
1739        DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1740
1741        raw_spin_lock_irqsave(&mpic_lock, flags);
1742
1743        /* let the mpic know we want intrs. default affinity is 0xffffffff
1744         * until changed via /proc. That's how it's done on x86. If we want
1745         * it differently, then we should make sure we also change the default
1746         * values of irq_desc[].affinity in irq.c.
1747         */
1748        if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1749                for (i = 0; i < mpic->num_sources ; i++)
1750                        mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1751                                mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1752        }
1753
1754        /* Set current processor priority to 0 */
1755        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1756
1757        raw_spin_unlock_irqrestore(&mpic_lock, flags);
1758#endif /* CONFIG_SMP */
1759}
1760
1761int mpic_cpu_get_priority(void)
1762{
1763        struct mpic *mpic = mpic_primary;
1764
1765        return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1766}
1767
1768void mpic_cpu_set_priority(int prio)
1769{
1770        struct mpic *mpic = mpic_primary;
1771
1772        prio &= MPIC_CPU_TASKPRI_MASK;
1773        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1774}
1775
1776void mpic_teardown_this_cpu(int secondary)
1777{
1778        struct mpic *mpic = mpic_primary;
1779        unsigned long flags;
1780        u32 msk = 1 << hard_smp_processor_id();
1781        unsigned int i;
1782
1783        BUG_ON(mpic == NULL);
1784
1785        DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1786        raw_spin_lock_irqsave(&mpic_lock, flags);
1787
1788        /* let the mpic know we don't want intrs.  */
1789        for (i = 0; i < mpic->num_sources ; i++)
1790                mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1791                        mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1792
1793        /* Set current processor priority to max */
1794        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1795        /* We need to EOI the IPI since not all platforms reset the MPIC
1796         * on boot and new interrupts wouldn't get delivered otherwise.
1797         */
1798        mpic_eoi(mpic);
1799
1800        raw_spin_unlock_irqrestore(&mpic_lock, flags);
1801}
1802
1803
1804static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1805{
1806        u32 src;
1807
1808        src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1809#ifdef DEBUG_LOW
1810        DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1811#endif
1812        if (unlikely(src == mpic->spurious_vec)) {
1813                if (mpic->flags & MPIC_SPV_EOI)
1814                        mpic_eoi(mpic);
1815                return NO_IRQ;
1816        }
1817        if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1818                printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1819                                   mpic->name, (int)src);
1820                mpic_eoi(mpic);
1821                return NO_IRQ;
1822        }
1823
1824        return irq_linear_revmap(mpic->irqhost, src);
1825}
1826
1827unsigned int mpic_get_one_irq(struct mpic *mpic)
1828{
1829        return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1830}
1831
1832unsigned int mpic_get_irq(void)
1833{
1834        struct mpic *mpic = mpic_primary;
1835
1836        BUG_ON(mpic == NULL);
1837
1838        return mpic_get_one_irq(mpic);
1839}
1840
1841unsigned int mpic_get_coreint_irq(void)
1842{
1843#ifdef CONFIG_BOOKE
1844        struct mpic *mpic = mpic_primary;
1845        u32 src;
1846
1847        BUG_ON(mpic == NULL);
1848
1849        src = mfspr(SPRN_EPR);
1850
1851        if (unlikely(src == mpic->spurious_vec)) {
1852                if (mpic->flags & MPIC_SPV_EOI)
1853                        mpic_eoi(mpic);
1854                return NO_IRQ;
1855        }
1856        if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1857                printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1858                                   mpic->name, (int)src);
1859                return NO_IRQ;
1860        }
1861
1862        return irq_linear_revmap(mpic->irqhost, src);
1863#else
1864        return NO_IRQ;
1865#endif
1866}
1867
1868unsigned int mpic_get_mcirq(void)
1869{
1870        struct mpic *mpic = mpic_primary;
1871
1872        BUG_ON(mpic == NULL);
1873
1874        return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1875}
1876
1877#ifdef CONFIG_SMP
1878void mpic_request_ipis(void)
1879{
1880        struct mpic *mpic = mpic_primary;
1881        int i;
1882        BUG_ON(mpic == NULL);
1883
1884        printk(KERN_INFO "mpic: requesting IPIs...\n");
1885
1886        for (i = 0; i < 4; i++) {
1887                unsigned int vipi = irq_create_mapping(mpic->irqhost,
1888                                                       mpic->ipi_vecs[0] + i);
1889                if (vipi == NO_IRQ) {
1890                        printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1891                        continue;
1892                }
1893                smp_request_message_ipi(vipi, i);
1894        }
1895}
1896
1897void smp_mpic_message_pass(int cpu, int msg)
1898{
1899        struct mpic *mpic = mpic_primary;
1900        u32 physmask;
1901
1902        BUG_ON(mpic == NULL);
1903
1904        /* make sure we're sending something that translates to an IPI */
1905        if ((unsigned int)msg > 3) {
1906                printk("SMP %d: smp_message_pass: unknown msg %d\n",
1907                       smp_processor_id(), msg);
1908                return;
1909        }
1910
1911#ifdef DEBUG_IPI
1912        DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1913#endif
1914
1915        physmask = 1 << get_hard_smp_processor_id(cpu);
1916
1917        mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1918                       msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1919}
1920
1921int __init smp_mpic_probe(void)
1922{
1923        int nr_cpus;
1924
1925        DBG("smp_mpic_probe()...\n");
1926
1927        nr_cpus = cpumask_weight(cpu_possible_mask);
1928
1929        DBG("nr_cpus: %d\n", nr_cpus);
1930
1931        if (nr_cpus > 1)
1932                mpic_request_ipis();
1933
1934        return nr_cpus;
1935}
1936
1937void smp_mpic_setup_cpu(int cpu)
1938{
1939        mpic_setup_this_cpu();
1940}
1941
1942void mpic_reset_core(int cpu)
1943{
1944        struct mpic *mpic = mpic_primary;
1945        u32 pir;
1946        int cpuid = get_hard_smp_processor_id(cpu);
1947        int i;
1948
1949        /* Set target bit for core reset */
1950        pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1951        pir |= (1 << cpuid);
1952        mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1953        mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1954
1955        /* Restore target bit after reset complete */
1956        pir &= ~(1 << cpuid);
1957        mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1958        mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1959
1960        /* Perform 15 EOI on each reset core to clear pending interrupts.
1961         * This is required for FSL CoreNet based devices */
1962        if (mpic->flags & MPIC_FSL) {
1963                for (i = 0; i < 15; i++) {
1964                        _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1965                                      MPIC_CPU_EOI, 0);
1966                }
1967        }
1968}
1969#endif /* CONFIG_SMP */
1970
1971#ifdef CONFIG_PM
1972static void mpic_suspend_one(struct mpic *mpic)
1973{
1974        int i;
1975
1976        for (i = 0; i < mpic->num_sources; i++) {
1977                mpic->save_data[i].vecprio =
1978                        mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1979                mpic->save_data[i].dest =
1980                        mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1981        }
1982}
1983
1984static int mpic_suspend(void)
1985{
1986        struct mpic *mpic = mpics;
1987
1988        while (mpic) {
1989                mpic_suspend_one(mpic);
1990                mpic = mpic->next;
1991        }
1992
1993        return 0;
1994}
1995
1996static void mpic_resume_one(struct mpic *mpic)
1997{
1998        int i;
1999
2000        for (i = 0; i < mpic->num_sources; i++) {
2001                mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
2002                               mpic->save_data[i].vecprio);
2003                mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
2004                               mpic->save_data[i].dest);
2005
2006#ifdef CONFIG_MPIC_U3_HT_IRQS
2007        if (mpic->fixups) {
2008                struct mpic_irq_fixup *fixup = &mpic->fixups[i];
2009
2010                if (fixup->base) {
2011                        /* we use the lowest bit in an inverted meaning */
2012                        if ((mpic->save_data[i].fixup_data & 1) == 0)
2013                                continue;
2014
2015                        /* Enable and configure */
2016                        writeb(0x10 + 2 * fixup->index, fixup->base + 2);
2017
2018                        writel(mpic->save_data[i].fixup_data & ~1,
2019                               fixup->base + 4);
2020                }
2021        }
2022#endif
2023        } /* end for loop */
2024}
2025
2026static void mpic_resume(void)
2027{
2028        struct mpic *mpic = mpics;
2029
2030        while (mpic) {
2031                mpic_resume_one(mpic);
2032                mpic = mpic->next;
2033        }
2034}
2035
2036static struct syscore_ops mpic_syscore_ops = {
2037        .resume = mpic_resume,
2038        .suspend = mpic_suspend,
2039};
2040
2041static int mpic_init_sys(void)
2042{
2043        register_syscore_ops(&mpic_syscore_ops);
2044        subsys_system_register(&mpic_subsys, NULL);
2045
2046        return 0;
2047}
2048
2049device_initcall(mpic_init_sys);
2050#endif
2051