linux/arch/powerpc/sysdev/dart_iommu.c
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   1/*
   2 * arch/powerpc/sysdev/dart_iommu.c
   3 *
   4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   5 * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
   6 *                    IBM Corporation
   7 *
   8 * Based on pSeries_iommu.c:
   9 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  10 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
  11 *
  12 * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
  13 *
  14 *
  15 * This program is free software; you can redistribute it and/or modify
  16 * it under the terms of the GNU General Public License as published by
  17 * the Free Software Foundation; either version 2 of the License, or
  18 * (at your option) any later version.
  19 *
  20 * This program is distributed in the hope that it will be useful,
  21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 * GNU General Public License for more details.
  24 *
  25 * You should have received a copy of the GNU General Public License
  26 * along with this program; if not, write to the Free Software
  27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  28 */
  29
  30#include <linux/init.h>
  31#include <linux/types.h>
  32#include <linux/mm.h>
  33#include <linux/spinlock.h>
  34#include <linux/string.h>
  35#include <linux/pci.h>
  36#include <linux/dma-mapping.h>
  37#include <linux/vmalloc.h>
  38#include <linux/suspend.h>
  39#include <linux/memblock.h>
  40#include <linux/gfp.h>
  41#include <asm/io.h>
  42#include <asm/prom.h>
  43#include <asm/iommu.h>
  44#include <asm/pci-bridge.h>
  45#include <asm/machdep.h>
  46#include <asm/cacheflush.h>
  47#include <asm/ppc-pci.h>
  48
  49#include "dart.h"
  50
  51/* Physical base address and size of the DART table */
  52unsigned long dart_tablebase; /* exported to htab_initialize */
  53static unsigned long dart_tablesize;
  54
  55/* Virtual base address of the DART table */
  56static u32 *dart_vbase;
  57#ifdef CONFIG_PM
  58static u32 *dart_copy;
  59#endif
  60
  61/* Mapped base address for the dart */
  62static unsigned int __iomem *dart;
  63
  64/* Dummy val that entries are set to when unused */
  65static unsigned int dart_emptyval;
  66
  67static struct iommu_table iommu_table_dart;
  68static int iommu_table_dart_inited;
  69static int dart_dirty;
  70static int dart_is_u4;
  71
  72#define DART_U4_BYPASS_BASE     0x8000000000ull
  73
  74#define DBG(...)
  75
  76static DEFINE_SPINLOCK(invalidate_lock);
  77
  78static inline void dart_tlb_invalidate_all(void)
  79{
  80        unsigned long l = 0;
  81        unsigned int reg, inv_bit;
  82        unsigned long limit;
  83        unsigned long flags;
  84
  85        spin_lock_irqsave(&invalidate_lock, flags);
  86
  87        DBG("dart: flush\n");
  88
  89        /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
  90         * control register and wait for it to clear.
  91         *
  92         * Gotcha: Sometimes, the DART won't detect that the bit gets
  93         * set. If so, clear it and set it again.
  94         */
  95
  96        limit = 0;
  97
  98        inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
  99retry:
 100        l = 0;
 101        reg = DART_IN(DART_CNTL);
 102        reg |= inv_bit;
 103        DART_OUT(DART_CNTL, reg);
 104
 105        while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
 106                l++;
 107        if (l == (1L << limit)) {
 108                if (limit < 4) {
 109                        limit++;
 110                        reg = DART_IN(DART_CNTL);
 111                        reg &= ~inv_bit;
 112                        DART_OUT(DART_CNTL, reg);
 113                        goto retry;
 114                } else
 115                        panic("DART: TLB did not flush after waiting a long "
 116                              "time. Buggy U3 ?");
 117        }
 118
 119        spin_unlock_irqrestore(&invalidate_lock, flags);
 120}
 121
 122static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
 123{
 124        unsigned int reg;
 125        unsigned int l, limit;
 126        unsigned long flags;
 127
 128        spin_lock_irqsave(&invalidate_lock, flags);
 129
 130        reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
 131                (bus_rpn & DART_CNTL_U4_IONE_MASK);
 132        DART_OUT(DART_CNTL, reg);
 133
 134        limit = 0;
 135wait_more:
 136        l = 0;
 137        while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
 138                rmb();
 139                l++;
 140        }
 141
 142        if (l == (1L << limit)) {
 143                if (limit < 4) {
 144                        limit++;
 145                        goto wait_more;
 146                } else
 147                        panic("DART: TLB did not flush after waiting a long "
 148                              "time. Buggy U4 ?");
 149        }
 150
 151        spin_unlock_irqrestore(&invalidate_lock, flags);
 152}
 153
 154static void dart_flush(struct iommu_table *tbl)
 155{
 156        mb();
 157        if (dart_dirty) {
 158                dart_tlb_invalidate_all();
 159                dart_dirty = 0;
 160        }
 161}
 162
 163static int dart_build(struct iommu_table *tbl, long index,
 164                       long npages, unsigned long uaddr,
 165                       enum dma_data_direction direction,
 166                       struct dma_attrs *attrs)
 167{
 168        unsigned int *dp;
 169        unsigned int rpn;
 170        long l;
 171
 172        DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
 173
 174        dp = ((unsigned int*)tbl->it_base) + index;
 175
 176        /* On U3, all memory is contiguous, so we can move this
 177         * out of the loop.
 178         */
 179        l = npages;
 180        while (l--) {
 181                rpn = __pa(uaddr) >> DART_PAGE_SHIFT;
 182
 183                *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
 184
 185                uaddr += DART_PAGE_SIZE;
 186        }
 187
 188        /* make sure all updates have reached memory */
 189        mb();
 190        in_be32((unsigned __iomem *)dp);
 191        mb();
 192
 193        if (dart_is_u4) {
 194                rpn = index;
 195                while (npages--)
 196                        dart_tlb_invalidate_one(rpn++);
 197        } else {
 198                dart_dirty = 1;
 199        }
 200        return 0;
 201}
 202
 203
 204static void dart_free(struct iommu_table *tbl, long index, long npages)
 205{
 206        unsigned int *dp;
 207
 208        /* We don't worry about flushing the TLB cache. The only drawback of
 209         * not doing it is that we won't catch buggy device drivers doing
 210         * bad DMAs, but then no 32-bit architecture ever does either.
 211         */
 212
 213        DBG("dart: free at: %lx, %lx\n", index, npages);
 214
 215        dp  = ((unsigned int *)tbl->it_base) + index;
 216
 217        while (npages--)
 218                *(dp++) = dart_emptyval;
 219}
 220
 221
 222static int __init dart_init(struct device_node *dart_node)
 223{
 224        unsigned int i;
 225        unsigned long tmp, base, size;
 226        struct resource r;
 227
 228        if (dart_tablebase == 0 || dart_tablesize == 0) {
 229                printk(KERN_INFO "DART: table not allocated, using "
 230                       "direct DMA\n");
 231                return -ENODEV;
 232        }
 233
 234        if (of_address_to_resource(dart_node, 0, &r))
 235                panic("DART: can't get register base ! ");
 236
 237        /* Make sure nothing from the DART range remains in the CPU cache
 238         * from a previous mapping that existed before the kernel took
 239         * over
 240         */
 241        flush_dcache_phys_range(dart_tablebase,
 242                                dart_tablebase + dart_tablesize);
 243
 244        /* Allocate a spare page to map all invalid DART pages. We need to do
 245         * that to work around what looks like a problem with the HT bridge
 246         * prefetching into invalid pages and corrupting data
 247         */
 248        tmp = memblock_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
 249        dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
 250                                         DARTMAP_RPNMASK);
 251
 252        /* Map in DART registers */
 253        dart = ioremap(r.start, resource_size(&r));
 254        if (dart == NULL)
 255                panic("DART: Cannot map registers!");
 256
 257        /* Map in DART table */
 258        dart_vbase = ioremap(__pa(dart_tablebase), dart_tablesize);
 259
 260        /* Fill initial table */
 261        for (i = 0; i < dart_tablesize/4; i++)
 262                dart_vbase[i] = dart_emptyval;
 263
 264        /* Initialize DART with table base and enable it. */
 265        base = dart_tablebase >> DART_PAGE_SHIFT;
 266        size = dart_tablesize >> DART_PAGE_SHIFT;
 267        if (dart_is_u4) {
 268                size &= DART_SIZE_U4_SIZE_MASK;
 269                DART_OUT(DART_BASE_U4, base);
 270                DART_OUT(DART_SIZE_U4, size);
 271                DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
 272        } else {
 273                size &= DART_CNTL_U3_SIZE_MASK;
 274                DART_OUT(DART_CNTL,
 275                         DART_CNTL_U3_ENABLE |
 276                         (base << DART_CNTL_U3_BASE_SHIFT) |
 277                         (size << DART_CNTL_U3_SIZE_SHIFT));
 278        }
 279
 280        /* Invalidate DART to get rid of possible stale TLBs */
 281        dart_tlb_invalidate_all();
 282
 283        printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
 284               dart_is_u4 ? "U4" : "U3");
 285
 286        return 0;
 287}
 288
 289static void iommu_table_dart_setup(void)
 290{
 291        iommu_table_dart.it_busno = 0;
 292        iommu_table_dart.it_offset = 0;
 293        /* it_size is in number of entries */
 294        iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
 295
 296        /* Initialize the common IOMMU code */
 297        iommu_table_dart.it_base = (unsigned long)dart_vbase;
 298        iommu_table_dart.it_index = 0;
 299        iommu_table_dart.it_blocksize = 1;
 300        iommu_init_table(&iommu_table_dart, -1);
 301
 302        /* Reserve the last page of the DART to avoid possible prefetch
 303         * past the DART mapped area
 304         */
 305        set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
 306}
 307
 308static void dma_dev_setup_dart(struct device *dev)
 309{
 310        /* We only have one iommu table on the mac for now, which makes
 311         * things simple. Setup all PCI devices to point to this table
 312         */
 313        if (get_dma_ops(dev) == &dma_direct_ops)
 314                set_dma_offset(dev, DART_U4_BYPASS_BASE);
 315        else
 316                set_iommu_table_base(dev, &iommu_table_dart);
 317}
 318
 319static void pci_dma_dev_setup_dart(struct pci_dev *dev)
 320{
 321        dma_dev_setup_dart(&dev->dev);
 322}
 323
 324static void pci_dma_bus_setup_dart(struct pci_bus *bus)
 325{
 326        if (!iommu_table_dart_inited) {
 327                iommu_table_dart_inited = 1;
 328                iommu_table_dart_setup();
 329        }
 330}
 331
 332static bool dart_device_on_pcie(struct device *dev)
 333{
 334        struct device_node *np = of_node_get(dev->of_node);
 335
 336        while(np) {
 337                if (of_device_is_compatible(np, "U4-pcie") ||
 338                    of_device_is_compatible(np, "u4-pcie")) {
 339                        of_node_put(np);
 340                        return true;
 341                }
 342                np = of_get_next_parent(np);
 343        }
 344        return false;
 345}
 346
 347static int dart_dma_set_mask(struct device *dev, u64 dma_mask)
 348{
 349        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
 350                return -EIO;
 351
 352        /* U4 supports a DART bypass, we use it for 64-bit capable
 353         * devices to improve performances. However, that only works
 354         * for devices connected to U4 own PCIe interface, not bridged
 355         * through hypertransport. We need the device to support at
 356         * least 40 bits of addresses.
 357         */
 358        if (dart_device_on_pcie(dev) && dma_mask >= DMA_BIT_MASK(40)) {
 359                dev_info(dev, "Using 64-bit DMA iommu bypass\n");
 360                set_dma_ops(dev, &dma_direct_ops);
 361        } else {
 362                dev_info(dev, "Using 32-bit DMA via iommu\n");
 363                set_dma_ops(dev, &dma_iommu_ops);
 364        }
 365        dma_dev_setup_dart(dev);
 366
 367        *dev->dma_mask = dma_mask;
 368        return 0;
 369}
 370
 371void __init iommu_init_early_dart(void)
 372{
 373        struct device_node *dn;
 374
 375        /* Find the DART in the device-tree */
 376        dn = of_find_compatible_node(NULL, "dart", "u3-dart");
 377        if (dn == NULL) {
 378                dn = of_find_compatible_node(NULL, "dart", "u4-dart");
 379                if (dn == NULL)
 380                        return; /* use default direct_dma_ops */
 381                dart_is_u4 = 1;
 382        }
 383
 384        /* Initialize the DART HW */
 385        if (dart_init(dn) != 0)
 386                goto bail;
 387
 388        /* Setup low level TCE operations for the core IOMMU code */
 389        ppc_md.tce_build = dart_build;
 390        ppc_md.tce_free  = dart_free;
 391        ppc_md.tce_flush = dart_flush;
 392
 393        /* Setup bypass if supported */
 394        if (dart_is_u4)
 395                ppc_md.dma_set_mask = dart_dma_set_mask;
 396
 397        ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart;
 398        ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart;
 399
 400        /* Setup pci_dma ops */
 401        set_pci_dma_ops(&dma_iommu_ops);
 402        return;
 403
 404 bail:
 405        /* If init failed, use direct iommu and null setup functions */
 406        ppc_md.pci_dma_dev_setup = NULL;
 407        ppc_md.pci_dma_bus_setup = NULL;
 408
 409        /* Setup pci_dma ops */
 410        set_pci_dma_ops(&dma_direct_ops);
 411}
 412
 413#ifdef CONFIG_PM
 414static void iommu_dart_save(void)
 415{
 416        memcpy(dart_copy, dart_vbase, 2*1024*1024);
 417}
 418
 419static void iommu_dart_restore(void)
 420{
 421        memcpy(dart_vbase, dart_copy, 2*1024*1024);
 422        dart_tlb_invalidate_all();
 423}
 424
 425static int __init iommu_init_late_dart(void)
 426{
 427        unsigned long tbasepfn;
 428        struct page *p;
 429
 430        /* if no dart table exists then we won't need to save it
 431         * and the area has also not been reserved */
 432        if (!dart_tablebase)
 433                return 0;
 434
 435        tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT;
 436        register_nosave_region_late(tbasepfn,
 437                                    tbasepfn + ((1<<24) >> PAGE_SHIFT));
 438
 439        /* For suspend we need to copy the dart contents because
 440         * it is not part of the regular mapping (see above) and
 441         * thus not saved automatically. The memory for this copy
 442         * must be allocated early because we need 2 MB. */
 443        p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT);
 444        BUG_ON(!p);
 445        dart_copy = page_address(p);
 446
 447        ppc_md.iommu_save = iommu_dart_save;
 448        ppc_md.iommu_restore = iommu_dart_restore;
 449
 450        return 0;
 451}
 452
 453late_initcall(iommu_init_late_dart);
 454#endif
 455
 456void __init alloc_dart_table(void)
 457{
 458        /* Only reserve DART space if machine has more than 1GB of RAM
 459         * or if requested with iommu=on on cmdline.
 460         *
 461         * 1GB of RAM is picked as limit because some default devices
 462         * (i.e. Airport Extreme) have 30 bit address range limits.
 463         */
 464
 465        if (iommu_is_off)
 466                return;
 467
 468        if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull)
 469                return;
 470
 471        /* 512 pages (2MB) is max DART tablesize. */
 472        dart_tablesize = 1UL << 21;
 473        /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
 474         * will blow up an entire large page anyway in the kernel mapping
 475         */
 476        dart_tablebase = (unsigned long)
 477                __va(memblock_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
 478
 479        printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase);
 480}
 481