linux/arch/arm64/kernel/smp.c
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   1/*
   2 * SMP initialisation and IPI support
   3 * Based on arch/arm/kernel/smp.c
   4 *
   5 * Copyright (C) 2012 ARM Ltd.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include <linux/delay.h>
  21#include <linux/init.h>
  22#include <linux/spinlock.h>
  23#include <linux/sched.h>
  24#include <linux/interrupt.h>
  25#include <linux/cache.h>
  26#include <linux/profile.h>
  27#include <linux/errno.h>
  28#include <linux/mm.h>
  29#include <linux/err.h>
  30#include <linux/cpu.h>
  31#include <linux/smp.h>
  32#include <linux/seq_file.h>
  33#include <linux/irq.h>
  34#include <linux/percpu.h>
  35#include <linux/clockchips.h>
  36#include <linux/completion.h>
  37#include <linux/of.h>
  38
  39#include <asm/atomic.h>
  40#include <asm/cacheflush.h>
  41#include <asm/cputype.h>
  42#include <asm/mmu_context.h>
  43#include <asm/pgtable.h>
  44#include <asm/pgalloc.h>
  45#include <asm/processor.h>
  46#include <asm/smp_plat.h>
  47#include <asm/sections.h>
  48#include <asm/tlbflush.h>
  49#include <asm/ptrace.h>
  50
  51/*
  52 * as from 2.5, kernels no longer have an init_tasks structure
  53 * so we need some other way of telling a new secondary core
  54 * where to place its SVC stack
  55 */
  56struct secondary_data secondary_data;
  57volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
  58
  59enum ipi_msg_type {
  60        IPI_RESCHEDULE,
  61        IPI_CALL_FUNC,
  62        IPI_CALL_FUNC_SINGLE,
  63        IPI_CPU_STOP,
  64};
  65
  66static DEFINE_RAW_SPINLOCK(boot_lock);
  67
  68/*
  69 * Write secondary_holding_pen_release in a way that is guaranteed to be
  70 * visible to all observers, irrespective of whether they're taking part
  71 * in coherency or not.  This is necessary for the hotplug code to work
  72 * reliably.
  73 */
  74static void write_pen_release(u64 val)
  75{
  76        void *start = (void *)&secondary_holding_pen_release;
  77        unsigned long size = sizeof(secondary_holding_pen_release);
  78
  79        secondary_holding_pen_release = val;
  80        __flush_dcache_area(start, size);
  81}
  82
  83/*
  84 * Boot a secondary CPU, and assign it the specified idle task.
  85 * This also gives us the initial stack to use for this CPU.
  86 */
  87static int boot_secondary(unsigned int cpu, struct task_struct *idle)
  88{
  89        unsigned long timeout;
  90
  91        /*
  92         * Set synchronisation state between this boot processor
  93         * and the secondary one
  94         */
  95        raw_spin_lock(&boot_lock);
  96
  97        /*
  98         * Update the pen release flag.
  99         */
 100        write_pen_release(cpu_logical_map(cpu));
 101
 102        /*
 103         * Send an event, causing the secondaries to read pen_release.
 104         */
 105        sev();
 106
 107        timeout = jiffies + (1 * HZ);
 108        while (time_before(jiffies, timeout)) {
 109                if (secondary_holding_pen_release == INVALID_HWID)
 110                        break;
 111                udelay(10);
 112        }
 113
 114        /*
 115         * Now the secondary core is starting up let it run its
 116         * calibrations, then wait for it to finish
 117         */
 118        raw_spin_unlock(&boot_lock);
 119
 120        return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
 121}
 122
 123static DECLARE_COMPLETION(cpu_running);
 124
 125int __cpu_up(unsigned int cpu, struct task_struct *idle)
 126{
 127        int ret;
 128
 129        /*
 130         * We need to tell the secondary core where to find its stack and the
 131         * page tables.
 132         */
 133        secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
 134        __flush_dcache_area(&secondary_data, sizeof(secondary_data));
 135
 136        /*
 137         * Now bring the CPU into our world.
 138         */
 139        ret = boot_secondary(cpu, idle);
 140        if (ret == 0) {
 141                /*
 142                 * CPU was successfully started, wait for it to come online or
 143                 * time out.
 144                 */
 145                wait_for_completion_timeout(&cpu_running,
 146                                            msecs_to_jiffies(1000));
 147
 148                if (!cpu_online(cpu)) {
 149                        pr_crit("CPU%u: failed to come online\n", cpu);
 150                        ret = -EIO;
 151                }
 152        } else {
 153                pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
 154        }
 155
 156        secondary_data.stack = NULL;
 157
 158        return ret;
 159}
 160
 161/*
 162 * This is the secondary CPU boot entry.  We're using this CPUs
 163 * idle thread stack, but a set of temporary page tables.
 164 */
 165asmlinkage void secondary_start_kernel(void)
 166{
 167        struct mm_struct *mm = &init_mm;
 168        unsigned int cpu = smp_processor_id();
 169
 170        printk("CPU%u: Booted secondary processor\n", cpu);
 171
 172        /*
 173         * All kernel threads share the same mm context; grab a
 174         * reference and switch to it.
 175         */
 176        atomic_inc(&mm->mm_count);
 177        current->active_mm = mm;
 178        cpumask_set_cpu(cpu, mm_cpumask(mm));
 179
 180        /*
 181         * TTBR0 is only used for the identity mapping at this stage. Make it
 182         * point to zero page to avoid speculatively fetching new entries.
 183         */
 184        cpu_set_reserved_ttbr0();
 185        flush_tlb_all();
 186
 187        preempt_disable();
 188        trace_hardirqs_off();
 189
 190        /*
 191         * Let the primary processor know we're out of the
 192         * pen, then head off into the C entry point
 193         */
 194        write_pen_release(INVALID_HWID);
 195
 196        /*
 197         * Synchronise with the boot thread.
 198         */
 199        raw_spin_lock(&boot_lock);
 200        raw_spin_unlock(&boot_lock);
 201
 202        /*
 203         * OK, now it's safe to let the boot CPU continue.  Wait for
 204         * the CPU migration code to notice that the CPU is online
 205         * before we continue.
 206         */
 207        set_cpu_online(cpu, true);
 208        complete(&cpu_running);
 209
 210        /*
 211         * Enable GIC and timers.
 212         */
 213        notify_cpu_starting(cpu);
 214
 215        local_irq_enable();
 216        local_fiq_enable();
 217
 218        /*
 219         * OK, it's off to the idle thread for us
 220         */
 221        cpu_startup_entry(CPUHP_ONLINE);
 222}
 223
 224void __init smp_cpus_done(unsigned int max_cpus)
 225{
 226        unsigned long bogosum = loops_per_jiffy * num_online_cpus();
 227
 228        pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
 229                num_online_cpus(), bogosum / (500000/HZ),
 230                (bogosum / (5000/HZ)) % 100);
 231}
 232
 233void __init smp_prepare_boot_cpu(void)
 234{
 235}
 236
 237static void (*smp_cross_call)(const struct cpumask *, unsigned int);
 238
 239static const struct smp_enable_ops *enable_ops[] __initconst = {
 240        &smp_spin_table_ops,
 241        &smp_psci_ops,
 242        NULL,
 243};
 244
 245static const struct smp_enable_ops *smp_enable_ops[NR_CPUS];
 246
 247static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name)
 248{
 249        const struct smp_enable_ops **ops = enable_ops;
 250
 251        while (*ops) {
 252                if (!strcmp(name, (*ops)->name))
 253                        return *ops;
 254
 255                ops++;
 256        }
 257
 258        return NULL;
 259}
 260
 261/*
 262 * Enumerate the possible CPU set from the device tree and build the
 263 * cpu logical map array containing MPIDR values related to logical
 264 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
 265 */
 266void __init smp_init_cpus(void)
 267{
 268        const char *enable_method;
 269        struct device_node *dn = NULL;
 270        int i, cpu = 1;
 271        bool bootcpu_valid = false;
 272
 273        while ((dn = of_find_node_by_type(dn, "cpu"))) {
 274                const u32 *cell;
 275                u64 hwid;
 276
 277                /*
 278                 * A cpu node with missing "reg" property is
 279                 * considered invalid to build a cpu_logical_map
 280                 * entry.
 281                 */
 282                cell = of_get_property(dn, "reg", NULL);
 283                if (!cell) {
 284                        pr_err("%s: missing reg property\n", dn->full_name);
 285                        goto next;
 286                }
 287                hwid = of_read_number(cell, of_n_addr_cells(dn));
 288
 289                /*
 290                 * Non affinity bits must be set to 0 in the DT
 291                 */
 292                if (hwid & ~MPIDR_HWID_BITMASK) {
 293                        pr_err("%s: invalid reg property\n", dn->full_name);
 294                        goto next;
 295                }
 296
 297                /*
 298                 * Duplicate MPIDRs are a recipe for disaster. Scan
 299                 * all initialized entries and check for
 300                 * duplicates. If any is found just ignore the cpu.
 301                 * cpu_logical_map was initialized to INVALID_HWID to
 302                 * avoid matching valid MPIDR values.
 303                 */
 304                for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
 305                        if (cpu_logical_map(i) == hwid) {
 306                                pr_err("%s: duplicate cpu reg properties in the DT\n",
 307                                        dn->full_name);
 308                                goto next;
 309                        }
 310                }
 311
 312                /*
 313                 * The numbering scheme requires that the boot CPU
 314                 * must be assigned logical id 0. Record it so that
 315                 * the logical map built from DT is validated and can
 316                 * be used.
 317                 */
 318                if (hwid == cpu_logical_map(0)) {
 319                        if (bootcpu_valid) {
 320                                pr_err("%s: duplicate boot cpu reg property in DT\n",
 321                                        dn->full_name);
 322                                goto next;
 323                        }
 324
 325                        bootcpu_valid = true;
 326
 327                        /*
 328                         * cpu_logical_map has already been
 329                         * initialized and the boot cpu doesn't need
 330                         * the enable-method so continue without
 331                         * incrementing cpu.
 332                         */
 333                        continue;
 334                }
 335
 336                if (cpu >= NR_CPUS)
 337                        goto next;
 338
 339                /*
 340                 * We currently support only the "spin-table" enable-method.
 341                 */
 342                enable_method = of_get_property(dn, "enable-method", NULL);
 343                if (!enable_method) {
 344                        pr_err("%s: missing enable-method property\n",
 345                                dn->full_name);
 346                        goto next;
 347                }
 348
 349                smp_enable_ops[cpu] = smp_get_enable_ops(enable_method);
 350
 351                if (!smp_enable_ops[cpu]) {
 352                        pr_err("%s: invalid enable-method property: %s\n",
 353                               dn->full_name, enable_method);
 354                        goto next;
 355                }
 356
 357                if (smp_enable_ops[cpu]->init_cpu(dn, cpu))
 358                        goto next;
 359
 360                pr_debug("cpu logical map 0x%llx\n", hwid);
 361                cpu_logical_map(cpu) = hwid;
 362next:
 363                cpu++;
 364        }
 365
 366        /* sanity check */
 367        if (cpu > NR_CPUS)
 368                pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
 369                           cpu, NR_CPUS);
 370
 371        if (!bootcpu_valid) {
 372                pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
 373                return;
 374        }
 375
 376        /*
 377         * All the cpus that made it to the cpu_logical_map have been
 378         * validated so set them as possible cpus.
 379         */
 380        for (i = 0; i < NR_CPUS; i++)
 381                if (cpu_logical_map(i) != INVALID_HWID)
 382                        set_cpu_possible(i, true);
 383}
 384
 385void __init smp_prepare_cpus(unsigned int max_cpus)
 386{
 387        int cpu, err;
 388        unsigned int ncores = num_possible_cpus();
 389
 390        /*
 391         * are we trying to boot more cores than exist?
 392         */
 393        if (max_cpus > ncores)
 394                max_cpus = ncores;
 395
 396        /* Don't bother if we're effectively UP */
 397        if (max_cpus <= 1)
 398                return;
 399
 400        /*
 401         * Initialise the present map (which describes the set of CPUs
 402         * actually populated at the present time) and release the
 403         * secondaries from the bootloader.
 404         *
 405         * Make sure we online at most (max_cpus - 1) additional CPUs.
 406         */
 407        max_cpus--;
 408        for_each_possible_cpu(cpu) {
 409                if (max_cpus == 0)
 410                        break;
 411
 412                if (cpu == smp_processor_id())
 413                        continue;
 414
 415                if (!smp_enable_ops[cpu])
 416                        continue;
 417
 418                err = smp_enable_ops[cpu]->prepare_cpu(cpu);
 419                if (err)
 420                        continue;
 421
 422                set_cpu_present(cpu, true);
 423                max_cpus--;
 424        }
 425}
 426
 427
 428void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
 429{
 430        smp_cross_call = fn;
 431}
 432
 433void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 434{
 435        smp_cross_call(mask, IPI_CALL_FUNC);
 436}
 437
 438void arch_send_call_function_single_ipi(int cpu)
 439{
 440        smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
 441}
 442
 443static const char *ipi_types[NR_IPI] = {
 444#define S(x,s)  [x - IPI_RESCHEDULE] = s
 445        S(IPI_RESCHEDULE, "Rescheduling interrupts"),
 446        S(IPI_CALL_FUNC, "Function call interrupts"),
 447        S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
 448        S(IPI_CPU_STOP, "CPU stop interrupts"),
 449};
 450
 451void show_ipi_list(struct seq_file *p, int prec)
 452{
 453        unsigned int cpu, i;
 454
 455        for (i = 0; i < NR_IPI; i++) {
 456                seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE,
 457                           prec >= 4 ? " " : "");
 458                for_each_present_cpu(cpu)
 459                        seq_printf(p, "%10u ",
 460                                   __get_irq_stat(cpu, ipi_irqs[i]));
 461                seq_printf(p, "      %s\n", ipi_types[i]);
 462        }
 463}
 464
 465u64 smp_irq_stat_cpu(unsigned int cpu)
 466{
 467        u64 sum = 0;
 468        int i;
 469
 470        for (i = 0; i < NR_IPI; i++)
 471                sum += __get_irq_stat(cpu, ipi_irqs[i]);
 472
 473        return sum;
 474}
 475
 476static DEFINE_RAW_SPINLOCK(stop_lock);
 477
 478/*
 479 * ipi_cpu_stop - handle IPI from smp_send_stop()
 480 */
 481static void ipi_cpu_stop(unsigned int cpu)
 482{
 483        if (system_state == SYSTEM_BOOTING ||
 484            system_state == SYSTEM_RUNNING) {
 485                raw_spin_lock(&stop_lock);
 486                pr_crit("CPU%u: stopping\n", cpu);
 487                dump_stack();
 488                raw_spin_unlock(&stop_lock);
 489        }
 490
 491        set_cpu_online(cpu, false);
 492
 493        local_fiq_disable();
 494        local_irq_disable();
 495
 496        while (1)
 497                cpu_relax();
 498}
 499
 500/*
 501 * Main handler for inter-processor interrupts
 502 */
 503void handle_IPI(int ipinr, struct pt_regs *regs)
 504{
 505        unsigned int cpu = smp_processor_id();
 506        struct pt_regs *old_regs = set_irq_regs(regs);
 507
 508        if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI)
 509                __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]);
 510
 511        switch (ipinr) {
 512        case IPI_RESCHEDULE:
 513                scheduler_ipi();
 514                break;
 515
 516        case IPI_CALL_FUNC:
 517                irq_enter();
 518                generic_smp_call_function_interrupt();
 519                irq_exit();
 520                break;
 521
 522        case IPI_CALL_FUNC_SINGLE:
 523                irq_enter();
 524                generic_smp_call_function_single_interrupt();
 525                irq_exit();
 526                break;
 527
 528        case IPI_CPU_STOP:
 529                irq_enter();
 530                ipi_cpu_stop(cpu);
 531                irq_exit();
 532                break;
 533
 534        default:
 535                pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
 536                break;
 537        }
 538        set_irq_regs(old_regs);
 539}
 540
 541void smp_send_reschedule(int cpu)
 542{
 543        smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 544}
 545
 546void smp_send_stop(void)
 547{
 548        unsigned long timeout;
 549
 550        if (num_online_cpus() > 1) {
 551                cpumask_t mask;
 552
 553                cpumask_copy(&mask, cpu_online_mask);
 554                cpu_clear(smp_processor_id(), mask);
 555
 556                smp_cross_call(&mask, IPI_CPU_STOP);
 557        }
 558
 559        /* Wait up to one second for other CPUs to stop */
 560        timeout = USEC_PER_SEC;
 561        while (num_online_cpus() > 1 && timeout--)
 562                udelay(1);
 563
 564        if (num_online_cpus() > 1)
 565                pr_warning("SMP: failed to stop secondary CPUs\n");
 566}
 567
 568/*
 569 * not supported here
 570 */
 571int setup_profiling_timer(unsigned int multiplier)
 572{
 573        return -EINVAL;
 574}
 575