1* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX 2 3Required properties: 4- compatible : Should be "fsl,<chip>-sdma" 5- reg : Should contain SDMA registers location and length 6- interrupts : Should contain SDMA interrupt 7- #dma-cells : Must be <3>. 8 The first cell specifies the DMA request/event ID. See details below 9 about the second and third cell. 10- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM 11 scripts firmware 12 13The second cell of dma phandle specifies the peripheral type of DMA transfer. 14The full ID of peripheral types can be found below. 15 16 ID transfer type 17 --------------------- 18 0 MCU domain SSI 19 1 Shared SSI 20 2 MMC 21 3 SDHC 22 4 MCU domain UART 23 5 Shared UART 24 6 FIRI 25 7 MCU domain CSPI 26 8 Shared CSPI 27 9 SIM 28 10 ATA 29 11 CCM 30 12 External peripheral 31 13 Memory Stick Host Controller 32 14 Shared Memory Stick Host Controller 33 15 DSP 34 16 Memory 35 17 FIFO type Memory 36 18 SPDIF 37 19 IPU Memory 38 20 ASRC 39 21 ESAI 40 41The third cell specifies the transfer priority as below. 42 43 ID transfer priority 44 ------------------------- 45 0 High 46 1 Medium 47 2 Low 48 49Examples: 50 51sdma@83fb0000 { 52 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 53 reg = <0x83fb0000 0x4000>; 54 interrupts = <6>; 55 #dma-cells = <3>; 56 fsl,sdma-ram-script-name = "sdma-imx51.bin"; 57}; 58 59DMA clients connected to the i.MX SDMA controller must use the format 60described in the dma.txt file. 61 62Examples: 63 64ssi2: ssi@70014000 { 65 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 66 reg = <0x70014000 0x4000>; 67 interrupts = <30>; 68 clocks = <&clks 49>; 69 dmas = <&sdma 24 1 0>, 70 <&sdma 25 1 0>; 71 dma-names = "rx", "tx"; 72 fsl,fifo-depth = <15>; 73}; 74