linux/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
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   1NVIDIA Tegra30 Clock And Reset Controller
   2
   3This binding uses the common clock binding:
   4Documentation/devicetree/bindings/clock/clock-bindings.txt
   5
   6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
   7for muxing and gating Tegra's clocks, and setting their rates.
   8
   9Required properties :
  10- compatible : Should be "nvidia,tegra30-car"
  11- reg : Should contain CAR registers location and length
  12- clocks : Should contain phandle and clock specifiers for two clocks:
  13  the 32 KHz "32k_in", and the board-specific oscillator "osc".
  14- #clock-cells : Should be 1.
  15  In clock consumers, this cell represents the clock ID exposed by the CAR.
  16
  17  The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
  18  registers. These IDs often match those in the CAR's RST_DEVICES registers,
  19  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
  20  this case, those clocks are assigned IDs above 160 in order to highlight
  21  this issue. Implementations that interpret these clock IDs as bit values
  22  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  23  explicitly handle these special cases.
  24
  25  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
  26  above.
  27
  28  0     cpu
  29  1     unassigned
  30  2     unassigned
  31  3     unassigned
  32  4     rtc
  33  5     timer
  34  6     uarta
  35  7     unassigned      (register bit affects uartb and vfir)
  36  8     gpio
  37  9     sdmmc2
  38  10    unassigned      (register bit affects spdif_in and spdif_out)
  39  11    i2s1
  40  12    i2c1
  41  13    ndflash
  42  14    sdmmc1
  43  15    sdmmc4
  44  16    unassigned
  45  17    pwm
  46  18    i2s2
  47  19    epp
  48  20    unassigned      (register bit affects vi and vi_sensor)
  49  21    2d
  50  22    usbd
  51  23    isp
  52  24    3d
  53  25    unassigned
  54  26    disp2
  55  27    disp1
  56  28    host1x
  57  29    vcp
  58  30    i2s0
  59  31    cop_cache
  60
  61  32    mc
  62  33    ahbdma
  63  34    apbdma
  64  35    unassigned
  65  36    kbc
  66  37    statmon
  67  38    pmc
  68  39    unassigned      (register bit affects fuse and fuse_burn)
  69  40    kfuse
  70  41    sbc1
  71  42    nor
  72  43    unassigned
  73  44    sbc2
  74  45    unassigned
  75  46    sbc3
  76  47    i2c5
  77  48    dsia
  78  49    unassigned      (register bit affects cve and tvo)
  79  50    mipi
  80  51    hdmi
  81  52    csi
  82  53    tvdac
  83  54    i2c2
  84  55    uartc
  85  56    unassigned
  86  57    emc
  87  58    usb2
  88  59    usb3
  89  60    mpe
  90  61    vde
  91  62    bsea
  92  63    bsev
  93
  94  64    speedo
  95  65    uartd
  96  66    uarte
  97  67    i2c3
  98  68    sbc4
  99  69    sdmmc3
 100  70    pcie
 101  71    owr
 102  72    afi
 103  73    csite
 104  74    pciex
 105  75    avpucq
 106  76    la
 107  77    unassigned
 108  78    unassigned
 109  79    dtv
 110  80    ndspeed
 111  81    i2cslow
 112  82    dsib
 113  83    unassigned
 114  84    irama
 115  85    iramb
 116  86    iramc
 117  87    iramd
 118  88    cram2
 119  89    unassigned
 120  90    audio_2x        a/k/a audio_2x_sync_clk
 121  91    unassigned
 122  92    csus
 123  93    cdev2
 124  94    cdev1
 125  95    unassigned
 126
 127  96    cpu_g
 128  97    cpu_lp
 129  98    3d2
 130  99    mselect
 131  100   tsensor
 132  101   i2s3
 133  102   i2s4
 134  103   i2c4
 135  104   sbc5
 136  105   sbc6
 137  106   d_audio
 138  107   apbif
 139  108   dam0
 140  109   dam1
 141  110   dam2
 142  111   hda2codec_2x
 143  112   atomics
 144  113   audio0_2x
 145  114   audio1_2x
 146  115   audio2_2x
 147  116   audio3_2x
 148  117   audio4_2x
 149  118   audio5_2x
 150  119   actmon
 151  120   extern1
 152  121   extern2
 153  122   extern3
 154  123   sata_oob
 155  124   sata
 156  125   hda
 157  127   se
 158  128   hda2hdmi
 159  129   sata_cold
 160
 161  160   uartb
 162  161   vfir
 163  162   spdif_in
 164  163   spdif_out
 165  164   vi
 166  165   vi_sensor
 167  166   fuse
 168  167   fuse_burn
 169  168   cve
 170  169   tvo
 171
 172  170   clk_32k
 173  171   clk_m
 174  172   clk_m_div2
 175  173   clk_m_div4
 176  174   pll_ref
 177  175   pll_c
 178  176   pll_c_out1
 179  177   pll_m
 180  178   pll_m_out1
 181  179   pll_p
 182  180   pll_p_out1
 183  181   pll_p_out2
 184  182   pll_p_out3
 185  183   pll_p_out4
 186  184   pll_a
 187  185   pll_a_out0
 188  186   pll_d
 189  187   pll_d_out0
 190  188   pll_d2
 191  189   pll_d2_out0
 192  190   pll_u
 193  191   pll_x
 194  192   pll_x_out0
 195  193   pll_e
 196  194   spdif_in_sync
 197  195   i2s0_sync
 198  196   i2s1_sync
 199  197   i2s2_sync
 200  198   i2s3_sync
 201  199   i2s4_sync
 202  200   vimclk
 203  201   audio0
 204  202   audio1
 205  203   audio2
 206  204   audio3
 207  205   audio4
 208  206   audio5
 209  207   clk_out_1 (extern1)
 210  208   clk_out_2 (extern2)
 211  209   clk_out_3 (extern3)
 212  210   sclk
 213  211   blink
 214  212   cclk_g
 215  213   cclk_lp
 216  214   twd
 217  215   cml0
 218  216   cml1
 219  217   hclk
 220  218   pclk
 221
 222Example SoC include file:
 223
 224/ {
 225        tegra_car: clock {
 226                compatible = "nvidia,tegra30-car";
 227                reg = <0x60006000 0x1000>;
 228                #clock-cells = <1>;
 229        };
 230
 231        usb@c5004000 {
 232                clocks = <&tegra_car 58>; /* usb2 */
 233        };
 234};
 235
 236Example board file:
 237
 238/ {
 239        clocks {
 240                compatible = "simple-bus";
 241                #address-cells = <1>;
 242                #size-cells = <0>;
 243
 244                osc: clock@0 {
 245                        compatible = "fixed-clock";
 246                        reg = <0>;
 247                        #clock-cells = <0>;
 248                        clock-frequency = <12000000>;
 249                };
 250
 251                clk_32k: clock@1 {
 252                        compatible = "fixed-clock";
 253                        reg = <1>;
 254                        #clock-cells = <0>;
 255                        clock-frequency = <32768>;
 256                };
 257        };
 258
 259        &tegra_car {
 260                clocks = <&clk_32k> <&osc>;
 261        };
 262};
 263