linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
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   1Samsung GPIO and Pin Mux/Config controller
   2
   3Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
   4controller. It controls the input/output settings on the available pads/pins
   5and also provides ability to multiplex and configure the output of various
   6on-chip controllers onto these pads.
   7
   8Required Properties:
   9- compatible: should be one of the following.
  10  - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
  11  - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
  12  - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
  13  - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
  14
  15- reg: Base address of the pin controller hardware module and length of
  16  the address space it occupies.
  17
  18- Pin banks as child nodes: Pin banks of the controller are represented by child
  19  nodes of the controller node. Bank name is taken from name of the node. Each
  20  bank node must contain following properties:
  21
  22  - gpio-controller: identifies the node as a gpio controller and pin bank.
  23  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
  24    binding is used, the amount of cells must be specified as 2. See generic
  25    GPIO binding documentation for description of particular cells.
  26
  27- Pin mux/config groups as child nodes: The pin mux (selecting pin function
  28  mode) and pin config (pull up/down, driver strength) settings are represented
  29  as child nodes of the pin-controller node. There should be atleast one
  30  child node and there is no limit on the count of these child nodes.
  31
  32  The child node should contain a list of pin(s) on which a particular pin
  33  function selection or pin configuration (or both) have to applied. This
  34  list of pins is specified using the property name "samsung,pins". There
  35  should be atleast one pin specfied for this property and there is no upper
  36  limit on the count of pins that can be specified. The pins are specified
  37  using pin names which are derived from the hardware manual of the SoC. As
  38  an example, the pins in GPA0 bank of the pin controller can be represented
  39  as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
  40  The format of the pin names should be (as per the hardware manual)
  41  "[pin bank name]-[pin number within the bank]".
  42
  43  The pin function selection that should be applied on the pins listed in the
  44  child node is specified using the "samsung,pin-function" property. The value
  45  of this property that should be applied to each of the pins listed in the
  46  "samsung,pins" property should be picked from the hardware manual of the SoC
  47  for the specified pin group. This property is optional in the child node if
  48  no specific function selection is desired for the pins listed in the child
  49  node. The value of this property is used as-is to program the pin-controller
  50  function selector register of the pin-bank.
  51
  52  The child node can also optionally specify one or more of the pin
  53  configuration that should be applied on all the pins listed in the
  54  "samsung,pins" property of the child node. The following pin configuration
  55  properties are supported.
  56
  57  - samsung,pin-pud: Pull up/down configuration.
  58  - samsung,pin-drv: Drive strength configuration.
  59  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
  60  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
  61
  62  The values specified by these config properties should be derived from the
  63  hardware manual and these values are programmed as-is into the pin
  64  pull up/down and driver strength register of the pin-controller.
  65
  66  Note: A child should include atleast a pin function selection property or
  67  pin configuration property (one or more) or both.
  68
  69  The client nodes that require a particular pin function selection and/or
  70  pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
  71  file.
  72
  73External GPIO and Wakeup Interrupts:
  74
  75The controller supports two types of external interrupts over gpio. The first
  76is the external gpio interrupt and second is the external wakeup interrupts.
  77The difference between the two is that the external wakeup interrupts can be
  78used as system wakeup events.
  79
  80A. External GPIO Interrupts: For supporting external gpio interrupts, the
  81   following properties should be specified in the pin-controller device node.
  82
  83   - interrupt-parent: phandle of the interrupt parent to which the external
  84     GPIO interrupts are forwarded to.
  85   - interrupts: interrupt specifier for the controller. The format and value of
  86     the interrupt specifier depends on the interrupt parent for the controller.
  87
  88   In addition, following properties must be present in node of every bank
  89   of pins supporting GPIO interrupts:
  90
  91   - interrupt-controller: identifies the controller node as interrupt-parent.
  92   - #interrupt-cells: the value of this property should be 2.
  93     - First Cell: represents the external gpio interrupt number local to the
  94       external gpio interrupt space of the controller.
  95     - Second Cell: flags to identify the type of the interrupt
  96       - 1 = rising edge triggered
  97       - 2 = falling edge triggered
  98       - 3 = rising and falling edge triggered
  99       - 4 = high level triggered
 100       - 8 = low level triggered
 101
 102B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
 103   child node representing the external wakeup interrupt controller should be
 104   included in the pin-controller device node. This child node should include
 105   the following properties.
 106
 107   - compatible: identifies the type of the external wakeup interrupt controller
 108     The possible values are:
 109     - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
 110       found on Samsung S3C64xx SoCs,
 111     - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
 112       found on Samsung Exynos4210 SoC.
 113   - interrupt-parent: phandle of the interrupt parent to which the external
 114     wakeup interrupts are forwarded to.
 115   - interrupts: interrupt used by multiplexed wakeup interrupts.
 116
 117   In addition, following properties must be present in node of every bank
 118   of pins supporting wake-up interrupts:
 119
 120   - interrupt-controller: identifies the node as interrupt-parent.
 121   - #interrupt-cells: the value of this property should be 2
 122     - First Cell: represents the external wakeup interrupt number local to
 123       the external wakeup interrupt space of the controller.
 124     - Second Cell: flags to identify the type of the interrupt
 125       - 1 = rising edge triggered
 126       - 2 = falling edge triggered
 127       - 3 = rising and falling edge triggered
 128       - 4 = high level triggered
 129       - 8 = low level triggered
 130
 131   Node of every bank of pins supporting direct wake-up interrupts (without
 132   multiplexing) must contain following properties:
 133
 134   - interrupt-parent: phandle of the interrupt parent to which the external
 135     wakeup interrupts are forwarded to.
 136   - interrupts: interrupts of the interrupt parent which are used for external
 137     wakeup interrupts from pins of the bank, must contain interrupts for all
 138     pins of the bank.
 139
 140Aliases:
 141
 142All the pin controller nodes should be represented in the aliases node using
 143the following format 'pinctrl{n}' where n is a unique number for the alias.
 144
 145Example: A pin-controller node with pin banks:
 146
 147        pinctrl_0: pinctrl@11400000 {
 148                compatible = "samsung,exynos4210-pinctrl";
 149                reg = <0x11400000 0x1000>;
 150                interrupts = <0 47 0>;
 151
 152                /* ... */
 153
 154                /* Pin bank without external interrupts */
 155                gpy0: gpy0 {
 156                        gpio-controller;
 157                        #gpio-cells = <2>;
 158                };
 159
 160                /* ... */
 161
 162                /* Pin bank with external GPIO or muxed wake-up interrupts */
 163                gpj0: gpj0 {
 164                        gpio-controller;
 165                        #gpio-cells = <2>;
 166
 167                        interrupt-controller;
 168                        #interrupt-cells = <2>;
 169                };
 170
 171                /* ... */
 172
 173                /* Pin bank with external direct wake-up interrupts */
 174                gpx0: gpx0 {
 175                        gpio-controller;
 176                        #gpio-cells = <2>;
 177
 178                        interrupt-controller;
 179                        interrupt-parent = <&gic>;
 180                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
 181                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
 182                        #interrupt-cells = <2>;
 183                };
 184
 185                /* ... */
 186        };
 187
 188Example 1: A pin-controller node with pin groups.
 189
 190        pinctrl_0: pinctrl@11400000 {
 191                compatible = "samsung,exynos4210-pinctrl";
 192                reg = <0x11400000 0x1000>;
 193                interrupts = <0 47 0>;
 194
 195                /* ... */
 196
 197                uart0_data: uart0-data {
 198                        samsung,pins = "gpa0-0", "gpa0-1";
 199                        samsung,pin-function = <2>;
 200                        samsung,pin-pud = <0>;
 201                        samsung,pin-drv = <0>;
 202                };
 203
 204                uart0_fctl: uart0-fctl {
 205                        samsung,pins = "gpa0-2", "gpa0-3";
 206                        samsung,pin-function = <2>;
 207                        samsung,pin-pud = <0>;
 208                        samsung,pin-drv = <0>;
 209                };
 210
 211                uart1_data: uart1-data {
 212                        samsung,pins = "gpa0-4", "gpa0-5";
 213                        samsung,pin-function = <2>;
 214                        samsung,pin-pud = <0>;
 215                        samsung,pin-drv = <0>;
 216                };
 217
 218                uart1_fctl: uart1-fctl {
 219                        samsung,pins = "gpa0-6", "gpa0-7";
 220                        samsung,pin-function = <2>;
 221                        samsung,pin-pud = <0>;
 222                        samsung,pin-drv = <0>;
 223                };
 224
 225                i2c2_bus: i2c2-bus {
 226                        samsung,pins = "gpa0-6", "gpa0-7";
 227                        samsung,pin-function = <3>;
 228                        samsung,pin-pud = <3>;
 229                        samsung,pin-drv = <0>;
 230                };
 231        };
 232
 233Example 2: A pin-controller node with external wakeup interrupt controller node.
 234
 235        pinctrl_1: pinctrl@11000000 {
 236                compatible = "samsung,exynos4210-pinctrl";
 237                reg = <0x11000000 0x1000>;
 238                interrupts = <0 46 0>
 239
 240                /* ... */
 241
 242                wakeup-interrupt-controller {
 243                        compatible = "samsung,exynos4210-wakeup-eint";
 244                        interrupt-parent = <&gic>;
 245                        interrupts = <0 32 0>;
 246                };
 247        };
 248
 249Example 3: A uart client node that supports 'default' and 'flow-control' states.
 250
 251        uart@13800000 {
 252                compatible = "samsung,exynos4210-uart";
 253                reg = <0x13800000 0x100>;
 254                interrupts = <0 52 0>;
 255                pinctrl-names = "default", "flow-control;
 256                pinctrl-0 = <&uart0_data>;
 257                pinctrl-1 = <&uart0_data &uart0_fctl>;
 258        };
 259
 260Example 4: Set up the default pin state for uart controller.
 261
 262        static int s3c24xx_serial_probe(struct platform_device *pdev) {
 263                struct pinctrl *pinctrl;
 264
 265                /* ... */
 266
 267                pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 268        }
 269