linux/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
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   1One-register-per-pin type device tree based pinctrl driver
   2
   3Required properties:
   4- compatible : "pinctrl-single" or "pinconf-single".
   5  "pinctrl-single" means that pinconf isn't supported.
   6  "pinconf-single" means that generic pinconf is supported.
   7
   8- reg : offset and length of the register set for the mux registers
   9
  10- pinctrl-single,register-width : pinmux register access width in bits
  11
  12- pinctrl-single,function-mask : mask of allowed pinmux function bits
  13  in the pinmux register
  14
  15Optional properties:
  16- pinctrl-single,function-off : function off mode for disabled state if
  17  available and same for all registers; if not specified, disabling of
  18  pin functions is ignored
  19
  20- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
  21  more than one pin
  22
  23- pinctrl-single,drive-strength : array of value that are used to configure
  24  drive strength in the pinmux register. They're value of drive strength
  25  current and drive strength mask.
  26
  27                /* drive strength current, mask */
  28                pinctrl-single,power-source = <0x30 0xf0>;
  29
  30- pinctrl-single,bias-pullup : array of value that are used to configure the
  31  input bias pullup in the pinmux register.
  32
  33                /* input, enabled pullup bits, disabled pullup bits, mask */
  34                pinctrl-single,bias-pullup = <0 1 0 1>;
  35
  36- pinctrl-single,bias-pulldown : array of value that are used to configure the
  37  input bias pulldown in the pinmux register.
  38
  39                /* input, enabled pulldown bits, disabled pulldown bits, mask */
  40                pinctrl-single,bias-pulldown = <2 2 0 2>;
  41
  42  * Two bits to control input bias pullup and pulldown: User should use
  43    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
  44    pullup, and the other one bit means pulldown.
  45  * Three bits to control input bias enable, pullup and pulldown. User should
  46    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
  47    enable bit should be included in pullup or pulldown bits.
  48  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
  49    pinctrl-single,bias-disable. Because pinctrl single driver could implement
  50    it by calling pulldown, pullup disabled.
  51
  52- pinctrl-single,input-schmitt : array of value that are used to configure
  53  input schmitt in the pinmux register. In some silicons, there're two input
  54  schmitt value (rising-edge & falling-edge) in the pinmux register.
  55
  56                /* input schmitt value, mask */
  57                pinctrl-single,input-schmitt = <0x30 0x70>;
  58
  59- pinctrl-single,input-schmitt-enable : array of value that are used to
  60  configure input schmitt enable or disable in the pinmux register.
  61
  62                /* input, enable bits, disable bits, mask */
  63                pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
  64
  65- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
  66  range. They're value of subnode phandle, pin base in pinctrl device, pin
  67  number in this range, GPIO function value of this GPIO range.
  68  The number of parameters is depend on #pinctrl-single,gpio-range-cells
  69  property.
  70
  71                /* pin base, nr pins & gpio function */
  72                pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
  73
  74This driver assumes that there is only one register for each pin (unless the
  75pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
  76specified in the pinctrl-bindings.txt document in this directory.
  77
  78The pin configuration nodes for pinctrl-single are specified as pinctrl
  79register offset and value pairs using pinctrl-single,pins. Only the bits
  80specified in pinctrl-single,function-mask are updated. For example, setting
  81a pin for a device could be done with:
  82
  83        pinctrl-single,pins = <0xdc 0x118>;
  84
  85Where 0xdc is the offset from the pinctrl register base address for the
  86device pinctrl register, and 0x118 contains the desired value of the
  87pinctrl register. See the device example and static board pins example
  88below for more information.
  89
  90In case when one register changes more than one pin's mux the
  91pinctrl-single,bits need to be used which takes three parameters:
  92
  93        pinctrl-single,bits = <0xdc 0x18, 0xff>;
  94
  95Where 0xdc is the offset from the pinctrl register base address for the
  96device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
  97be used when applying this change to the register.
  98
  99
 100Optional sub-node: In case some pins could be configured as GPIO in the pinmux
 101register, those pins could be defined as a GPIO range. This sub-node is required
 102by pinctrl-single,gpio-range property.
 103
 104Required properties in sub-node:
 105- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
 106  pinctrl-single,gpio-range property.
 107
 108        range: gpio-range {
 109                #pinctrl-single,gpio-range-cells = <3>;
 110        };
 111
 112
 113Example:
 114
 115/* SoC common file */
 116
 117/* first controller instance for pins in core domain */
 118pmx_core: pinmux@4a100040 {
 119        compatible = "pinctrl-single";
 120        reg = <0x4a100040 0x0196>;
 121        #address-cells = <1>;
 122        #size-cells = <0>;
 123        pinctrl-single,register-width = <16>;
 124        pinctrl-single,function-mask = <0xffff>;
 125};
 126
 127/* second controller instance for pins in wkup domain */
 128pmx_wkup: pinmux@4a31e040 {
 129        compatible = "pinctrl-single";
 130        reg = <0x4a31e040 0x0038>;
 131        #address-cells = <1>;
 132        #size-cells = <0>;
 133        pinctrl-single,register-width = <16>;
 134        pinctrl-single,function-mask = <0xffff>;
 135};
 136
 137control_devconf0: pinmux@48002274 {
 138        compatible = "pinctrl-single";
 139        reg = <0x48002274 4>;   /* Single register */
 140        #address-cells = <1>;
 141        #size-cells = <0>;
 142        pinctrl-single,bit-per-mux;
 143        pinctrl-single,register-width = <32>;
 144        pinctrl-single,function-mask = <0x5F>;
 145};
 146
 147/* third controller instance for pins in gpio domain */
 148pmx_gpio: pinmux@d401e000 {
 149        compatible = "pinconf-single";
 150        reg = <0xd401e000 0x0330>;
 151        #address-cells = <1>;
 152        #size-cells = <1>;
 153        ranges;
 154
 155        pinctrl-single,register-width = <32>;
 156        pinctrl-single,function-mask = <7>;
 157
 158        /* sparse GPIO range could be supported */
 159        pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
 160                                &range 12 1 0 &range 13 29 1
 161                                &range 43 1 0 &range 44 49 1
 162                                &range 94 1 1 &range 96 2 1>;
 163
 164        range: gpio-range {
 165                #pinctrl-single,gpio-range-cells = <3>;
 166        };
 167};
 168
 169
 170/* board specific .dts file */
 171
 172&pmx_core {
 173
 174        /*
 175         * map all board specific static pins enabled by the pinctrl driver
 176         * itself during the boot (or just set them up in the bootloader)
 177         */
 178        pinctrl-names = "default";
 179        pinctrl-0 = <&board_pins>;
 180
 181        board_pins: pinmux_board_pins {
 182                pinctrl-single,pins = <
 183                        0x6c 0xf
 184                        0x6e 0xf
 185                        0x70 0xf
 186                        0x72 0xf
 187                >;
 188        };
 189
 190        uart0_pins: pinmux_uart0_pins {
 191                pinctrl-single,pins = <
 192                        0x208 0         /* UART0_RXD (IOCFG138) */
 193                        0x20c 0         /* UART0_TXD (IOCFG139) */
 194                >;
 195                pinctrl-single,bias-pulldown = <0 2 2>;
 196                pinctrl-single,bias-pullup = <0 1 1>;
 197        };
 198
 199        /* map uart2 pins */
 200        uart2_pins: pinmux_uart2_pins {
 201                pinctrl-single,pins = <
 202                        0xd8 0x118
 203                        0xda 0
 204                        0xdc 0x118
 205                        0xde 0
 206                >;
 207        };
 208};
 209
 210&control_devconf0 {
 211        mcbsp1_pins: pinmux_mcbsp1_pins {
 212                pinctrl-single,bits = <
 213                        0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
 214                >;
 215        };
 216
 217        mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
 218                pinctrl-single,bits = <
 219                        0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
 220                >;
 221        };
 222
 223};
 224
 225&uart1 {
 226       pinctrl-names = "default";
 227       pinctrl-0 = <&uart0_pins>;
 228};
 229
 230&uart2 {
 231       pinctrl-names = "default";
 232       pinctrl-0 = <&uart2_pins>;
 233};
 234