1Samsung S3C24XX Interrupt Controllers 2 3The S3C24XX SoCs contain a custom set of interrupt controllers providing a 4varying number of interrupt sources. The set consists of a main- and sub- 5controller and on newer SoCs even a second main controller. 6 7Required properties: 8- compatible: Compatible property value should be "samsung,s3c2410-irq" 9 for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later. 10 11- reg: Physical base address of the controller and length of memory mapped 12 region. 13 14- interrupt-controller : Identifies the node as an interrupt controller 15 16- #interrupt-cells : Specifies the number of cells needed to encode an 17 interrupt source. The value shall be 4 and interrupt descriptor shall 18 have the following format: 19 <ctrl_num parent_irq ctrl_irq type> 20 21 ctrl_num contains the controller to use: 22 - 0 ... main controller 23 - 1 ... sub controller 24 - 2 ... second main controller on s3c2416 and s3c2450 25 parent_irq contains the parent bit in the main controller and will be 26 ignored in main controllers 27 ctrl_irq contains the interrupt bit of the controller 28 type contains the trigger type to use 29 30Example: 31 32 interrupt-controller@4a000000 { 33 compatible = "samsung,s3c2410-irq"; 34 reg = <0x4a000000 0x100>; 35 interrupt-controller; 36 #interrupt-cells=<4>; 37 }; 38 39 [...] 40 41 serial@50000000 { 42 compatible = "samsung,s3c2410-uart"; 43 reg = <0x50000000 0x4000>; 44 interrupt-parent = <&subintc>; 45 interrupts = <1 28 0 4>, <1 28 1 4>; 46 }; 47 48 rtc@57000000 { 49 compatible = "samsung,s3c2410-rtc"; 50 reg = <0x57000000 0x100>; 51 interrupt-parent = <&intc>; 52 interrupts = <0 30 0 3>, <0 8 0 3>; 53 }; 54