1Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. 2 3Reference 4[1] Si5351A/B/C Data Sheet 5 http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf 6 7The Si5351a/b/c are programmable i2c clock generators with upto 8 output 8clocks. Si5351a also has a reduced pin-count package (MSOP10) where only 93 output clocks are accessible. The internal structure of the clock 10generators can be found in [1]. 11 12==I2C device node== 13 14Required properties: 15- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}". 16- reg: i2c device address, shall be 0x60 or 0x61. 17- #clock-cells: from common clock binding; shall be set to 1. 18- clocks: from common clock binding; list of parent clock 19 handles, shall be xtal reference clock or xtal and clkin for 20 si5351c only. 21- #address-cells: shall be set to 1. 22- #size-cells: shall be set to 0. 23 24Optional properties: 25- silabs,pll-source: pair of (number, source) for each pll. Allows 26 to overwrite clock source of pll A (number=0) or B (number=1). 27 28==Child nodes== 29 30Each of the clock outputs can be overwritten individually by 31using a child node to the I2C device node. If a child node for a clock 32output is not set, the eeprom configuration is not overwritten. 33 34Required child node properties: 35- reg: number of clock output. 36 37Optional child node properties: 38- silabs,clock-source: source clock of the output divider stage N, shall be 39 0 = multisynth N 40 1 = multisynth 0 for output clocks 0-3, else multisynth4 41 2 = xtal 42 3 = clkin (si5351c only) 43- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. 44- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth 45 divider. 46- silabs,pll-master: boolean, multisynth can change pll frequency. 47 48==Example== 49 50/* 25MHz reference crystal */ 51ref25: ref25M { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <25000000>; 55}; 56 57i2c-master-node { 58 59 /* Si5351a msop10 i2c clock generator */ 60 si5351a: clock-generator@60 { 61 compatible = "silabs,si5351a-msop"; 62 reg = <0x60>; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 #clock-cells = <1>; 66 67 /* connect xtal input to 25MHz reference */ 68 clocks = <&ref25>; 69 70 /* connect xtal input as source of pll0 and pll1 */ 71 silabs,pll-source = <0 0>, <1 0>; 72 73 /* 74 * overwrite clkout0 configuration with: 75 * - 8mA output drive strength 76 * - pll0 as clock source of multisynth0 77 * - multisynth0 as clock source of output divider 78 * - multisynth0 can change pll0 79 * - set initial clock frequency of 74.25MHz 80 */ 81 clkout0 { 82 reg = <0>; 83 silabs,drive-strength = <8>; 84 silabs,multisynth-source = <0>; 85 silabs,clock-source = <0>; 86 silabs,pll-master; 87 clock-frequency = <74250000>; 88 }; 89 90 /* 91 * overwrite clkout1 configuration with: 92 * - 4mA output drive strength 93 * - pll1 as clock source of multisynth1 94 * - multisynth1 as clock source of output divider 95 * - multisynth1 can change pll1 96 */ 97 clkout1 { 98 reg = <1>; 99 silabs,drive-strength = <4>; 100 silabs,multisynth-source = <1>; 101 silabs,clock-source = <0>; 102 pll-master; 103 }; 104 105 /* 106 * overwrite clkout2 configuration with: 107 * - xtal as clock source of output divider 108 */ 109 clkout2 { 110 reg = <2>; 111 silabs,clock-source = <2>; 112 }; 113 }; 114}; 115