1* Samsung Exynos5250 Clock Controller 2 3The Exynos5250 clock controller generates and supplies clock to various 4controllers within the Exynos5250 SoC. 5 6Required Properties: 7 8- comptible: should be one of the following. 9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC. 10 11- reg: physical base address of the controller and length of memory mapped 12 region. 13 14- #clock-cells: should be 1. 15 16The following is the list of clocks generated by the controller. Each clock is 17assigned an identifier and client nodes use this identifier to specify the 18clock which they consume. 19 20 21 [Core Clocks] 22 23 Clock ID 24 ---------------------------- 25 26 fin_pll 1 27 28 [Clock Gate for Special Clocks] 29 30 Clock ID 31 ---------------------------- 32 33 sclk_cam_bayer 128 34 sclk_cam0 129 35 sclk_cam1 130 36 sclk_gscl_wa 131 37 sclk_gscl_wb 132 38 sclk_fimd1 133 39 sclk_mipi1 134 40 sclk_dp 135 41 sclk_hdmi 136 42 sclk_pixel 137 43 sclk_audio0 138 44 sclk_mmc0 139 45 sclk_mmc1 140 46 sclk_mmc2 141 47 sclk_mmc3 142 48 sclk_sata 143 49 sclk_usb3 144 50 sclk_jpeg 145 51 sclk_uart0 146 52 sclk_uart1 147 53 sclk_uart2 148 54 sclk_uart3 149 55 sclk_pwm 150 56 sclk_audio1 151 57 sclk_audio2 152 58 sclk_spdif 153 59 sclk_spi0 154 60 sclk_spi1 155 61 sclk_spi2 156 62 63 64 [Peripheral Clock Gates] 65 66 Clock ID 67 ---------------------------- 68 69 gscl0 256 70 gscl1 257 71 gscl2 258 72 gscl3 259 73 gscl_wa 260 74 gscl_wb 261 75 smmu_gscl0 262 76 smmu_gscl1 263 77 smmu_gscl2 264 78 smmu_gscl3 265 79 mfc 266 80 smmu_mfcl 267 81 smmu_mfcr 268 82 rotator 269 83 jpeg 270 84 mdma1 271 85 smmu_rotator 272 86 smmu_jpeg 273 87 smmu_mdma1 274 88 pdma0 275 89 pdma1 276 90 sata 277 91 usbotg 278 92 mipi_hsi 279 93 sdmmc0 280 94 sdmmc1 281 95 sdmmc2 282 96 sdmmc3 283 97 sromc 284 98 usb2 285 99 usb3 286 100 sata_phyctrl 287 101 sata_phyi2c 288 102 uart0 289 103 uart1 290 104 uart2 291 105 uart3 292 106 uart4 293 107 i2c0 294 108 i2c1 295 109 i2c2 296 110 i2c3 297 111 i2c4 298 112 i2c5 299 113 i2c6 300 114 i2c7 301 115 i2c_hdmi 302 116 adc 303 117 spi0 304 118 spi1 305 119 spi2 306 120 i2s1 307 121 i2s2 308 122 pcm1 309 123 pcm2 310 124 pwm 311 125 spdif 312 126 ac97 313 127 hsi2c0 314 128 hsi2c1 315 129 hs12c2 316 130 hs12c3 317 131 chipid 318 132 sysreg 319 133 pmu 320 134 cmu_top 321 135 cmu_core 322 136 cmu_mem 323 137 tzpc0 324 138 tzpc1 325 139 tzpc2 326 140 tzpc3 327 141 tzpc4 328 142 tzpc5 329 143 tzpc6 330 144 tzpc7 331 145 tzpc8 332 146 tzpc9 333 147 hdmi_cec 334 148 mct 335 149 wdt 336 150 rtc 337 151 tmu 338 152 fimd1 339 153 mie1 340 154 dsim0 341 155 dp 342 156 mixer 343 157 hdmi 345 158 159Example 1: An example of a clock controller node is listed below. 160 161 clock: clock-controller@0x10010000 { 162 compatible = "samsung,exynos5250-clock"; 163 reg = <0x10010000 0x30000>; 164 #clock-cells = <1>; 165 }; 166 167Example 2: UART controller node that consumes the clock generated by the clock 168 controller. Refer to the standard clock bindings for information 169 about 'clocks' and 'clock-names' property. 170 171 serial@13820000 { 172 compatible = "samsung,exynos4210-uart"; 173 reg = <0x13820000 0x100>; 174 interrupts = <0 54 0>; 175 clocks = <&clock 314>, <&clock 153>; 176 clock-names = "uart", "clk_uart_baud0"; 177 }; 178