1NVIDIA Tegra Power Management Controller (PMC) 2 3The PMC block interacts with an external Power Management Unit. The PMC 4mostly controls the entry and exit of the system from different sleep 5modes. It provides power-gating controllers for SoC and CPU power-islands. 6 7Required properties: 8- name : Should be pmc 9- compatible : Should contain "nvidia,tegra<chip>-pmc". 10- reg : Offset and length of the register set for the device 11- clocks : Must contain an entry for each entry in clock-names. 12- clock-names : Must include the following entries: 13 "pclk" (The Tegra clock of that name), 14 "clk32k_in" (The 32KHz clock input to Tegra). 15 16Optional properties: 17- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. 18 The PMU is an external Power Management Unit, whose interrupt output 19 signal is fed into the PMC. This signal is optionally inverted, and then 20 fed into the ARM GIC. The PMC is not involved in the detection or 21 handling of this interrupt signal, merely its inversion. 22- nvidia,suspend-mode : The suspend mode that the platform should use. 23 Valid values are 0, 1 and 2: 24 0 (LP0): CPU + Core voltage off and DRAM in self-refresh 25 1 (LP1): CPU voltage off and DRAM in self-refresh 26 2 (LP2): CPU voltage off 27- nvidia,core-power-req-active-high : Boolean, core power request active-high 28- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high 29- nvidia,combined-power-req : Boolean, combined power request for CPU & Core 30- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) 31 is enabled. 32 33Required properties when nvidia,suspend-mode is specified: 34- nvidia,cpu-pwr-good-time : CPU power good time in uS. 35- nvidia,cpu-pwr-off-time : CPU power off time in uS. 36- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time> 37 Core power good time in uS. 38- nvidia,core-pwr-off-time : Core power off time in uS. 39 40Required properties when nvidia,suspend-mode=<0>: 41- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector 42 The LP0 vector contains the warm boot code that is executed by AVP when 43 resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 44 processor and always being the first boot processor when chip is power on 45 or resume from deep sleep mode. When the system is resumed from the deep 46 sleep mode, the warm boot code will restore some PLLs, clocks and then 47 bring up CPU0 for resuming the system. 48 49Example: 50 51/ SoC dts including file 52pmc@7000f400 { 53 compatible = "nvidia,tegra20-pmc"; 54 reg = <0x7000e400 0x400>; 55 clocks = <&tegra_car 110>, <&clk32k_in>; 56 clock-names = "pclk", "clk32k_in"; 57 nvidia,invert-interrupt; 58 nvidia,suspend-mode = <1>; 59 nvidia,cpu-pwr-good-time = <2000>; 60 nvidia,cpu-pwr-off-time = <100>; 61 nvidia,core-pwr-good-time = <3845 3845>; 62 nvidia,core-pwr-off-time = <458>; 63 nvidia,core-power-req-active-high; 64 nvidia,sys-clock-req-active-high; 65 nvidia,lp0-vec = <0xbdffd000 0x2000>; 66}; 67 68/ Tegra board dts file 69{ 70 ... 71 clocks { 72 compatible = "simple-bus"; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 clk32k_in: clock { 77 compatible = "fixed-clock"; 78 reg=<0>; 79 #clock-cells = <0>; 80 clock-frequency = <32768>; 81 }; 82 }; 83 ... 84}; 85