1* ARM architected timer 2 3ARM cores may have a per-core architected timer, which provides per-cpu timers. 4 5The timer is attached to a GIC to deliver its per-processor interrupts. 6 7** Timer node properties: 8 9- compatible : Should at least contain one of 10 "arm,armv7-timer" 11 "arm,armv8-timer" 12 13- interrupts : Interrupt list for secure, non-secure, virtual and 14 hypervisor timers, in that order. 15 16- clock-frequency : The frequency of the main counter, in Hz. Optional. 17 18Example: 19 20 timer { 21 compatible = "arm,cortex-a15-timer", 22 "arm,armv7-timer"; 23 interrupts = <1 13 0xf08>, 24 <1 14 0xf08>, 25 <1 11 0xf08>, 26 <1 10 0xf08>; 27 clock-frequency = <100000000>; 28 }; 29