LXR linux/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt

   1Lantiq XWAY pinmux controller
   2
   3Required properties:
   4- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
   5- reg: Should contain the physical address and length of the gpio/pinmux
   6  register range
   7
   8Please refer to pinctrl-bindings.txt in this directory for details of the
   9common pinctrl bindings used by client devices, including the meaning of the
  10phrase "pin configuration node".
  11
  12Lantiq's pin configuration nodes act as a container for an abitrary number of
  13subnodes. Each of these subnodes represents some desired configuration for a
  14pin, a group, or a list of pins or groups. This configuration can include the
  15mux function to select on those group(s), and two pin configuration parameters:
  16pull-up and open-drain
  17
  18The name of each subnode is not important as long as it is unique; all subnodes
  19should be enumerated and processed purely based on their content.
  20
  21Each subnode only affects those parameters that are explicitly listed. In
  22other words, a subnode that lists a mux function but no pin configuration
  23parameters implies no information about any pin configuration parameters.
  24Similarly, a pin subnode that describes a pullup parameter implies no
  25information about e.g. the mux function.
  26
  27We support 2 types of nodes.
  28
  29Definition of mux function groups:
  30
  31Required subnode-properties:
  32- lantiq,groups : An array of strings. Each string contains the name of a group.
  33  Valid values for these names are listed below.
  34- lantiq,function: A string containing the name of the function to mux to the
  35  group. Valid values for function names are listed below.
  36
  37Valid values for group and function names:
  38
  39  mux groups:
  40    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
  41    ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
  42    spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
  43    gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
  44    req3
  45
  46  additional mux groups (XR9 only):
  47    mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
  48
  49  functions:
  50    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
  51
  52
  53
  54Definition of pin configurations:
  55
  56Required subnode-properties:
  57- lantiq,pins : An array of strings. Each string contains the name of a pin.
  58  Valid values for these names are listed below.
  59
  60Optional subnode-properties:
  61- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
  62    0: none, 1: down, 2: up.
  63- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
  64
  65Valid values for XWAY pin names:
  66  Pinconf pins can be referenced via the names io0-io31.
  67
  68Valid values for XR9 pin names:
  69  Pinconf pins can be referenced via the names io0-io55.
  70
  71Example:
  72        gpio: pinmux@E100B10 {
  73                compatible = "lantiq,pinctrl-xway";
  74                pinctrl-names = "default";
  75                pinctrl-0 = <&state_default>;
  76
  77                #gpio-cells = <2>;
  78                gpio-controller;
  79                reg = <0xE100B10 0xA0>;
  80
  81                state_default: pinmux {
  82                        stp {
  83                                lantiq,groups = "stp";
  84                                lantiq,function = "stp";
  85                        };
  86                        pci {
  87                                lantiq,groups = "gnt1";
  88                                lantiq,function = "pci";
  89                        };
  90                        conf_out {
  91                                lantiq,pins = "io4", "io5", "io6"; /* stp */
  92                                lantiq,open-drain;
  93                                lantiq,pull = <0>;
  94                        };
  95                };
  96        };
  97
  98