LXR linux/arch/mips/pci/fixup-cobalt.c

   1/*
   2 * Cobalt Qube/Raq PCI support
   3 *
   4 * This file is subject to the terms and conditions of the GNU General Public
   5 * License.  See the file "COPYING" in the main directory of this archive
   6 * for more details.
   7 *
   8 * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
   9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
  10 */
  11#include <linux/types.h>
  12#include <linux/pci.h>
  13#include <linux/kernel.h>
  14#include <linux/init.h>
  15
  16#include <asm/pci.h>
  17#include <asm/io.h>
  18#include <asm/gt64120.h>
  19
  20#include <cobalt.h>
  21#include <irq.h>
  22
  23/*
  24 * PCI slot numbers
  25 */
  26#define COBALT_PCICONF_CPU      0x06
  27#define COBALT_PCICONF_ETH0     0x07
  28#define COBALT_PCICONF_RAQSCSI  0x08
  29#define COBALT_PCICONF_VIA      0x09
  30#define COBALT_PCICONF_PCISLOT  0x0A
  31#define COBALT_PCICONF_ETH1     0x0C
  32
  33/*
  34 * The Cobalt board ID information.  The boards have an ID number wired
  35 * into the VIA that is available in the high nibble of register 94.
  36 */
  37#define VIA_COBALT_BRD_ID_REG  0x94
  38#define VIA_COBALT_BRD_REG_to_ID(reg)   ((unsigned char)(reg) >> 4)
  39
  40static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
  41{
  42        if (dev->devfn == PCI_DEVFN(0, 0) &&
  43                (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
  44
  45                dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
  46
  47                printk(KERN_INFO "Galileo: fixed bridge class\n");
  48        }
  49}
  50
  51DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
  52         qube_raq_galileo_early_fixup);
  53
  54static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
  55                                                       struct resource *res)
  56{
  57        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
  58        unsigned long offset = hose->io_offset;
  59        struct resource orig = *res;
  60
  61        if (!(res->flags & IORESOURCE_IO) ||
  62            !(res->flags & IORESOURCE_PCI_FIXED))
  63                return;
  64
  65        res->start -= offset;
  66        res->end -= offset;
  67        dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
  68                   &orig, res);
  69}
  70
  71static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
  72{
  73        u32 class;
  74        u8 progif;
  75
  76        /*
  77         * If the IDE controller is in legacy mode, pci_setup_device() fills in
  78         * the resources with the legacy addresses that normally appear on the
  79         * PCI bus, just as if we had read them from a BAR.
  80         *
  81         * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
  82         * will never appear on the PCI bus because it converts memory accesses
  83         * in the PCI I/O region (which is never at address zero) into I/O port
  84         * accesses with no address translation.
  85         *
  86         * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
  87         * to physical address 0x100001f0 will become a PCI access to I/O port
  88         * 0x100001f0.  There's no way to generate an access to I/O port 0x1f0,
  89         * but the VT82C586 IDE controller does respond at 0x100001f0 because
  90         * it only decodes the low 24 bits of the address.
  91         *
  92         * When this quirk runs, the pci_dev resources should contain bus
  93         * addresses, not Linux I/O port numbers, so convert legacy addresses
  94         * like 0x1f0 to bus addresses like 0x100001f0.  Later, we'll convert
  95         * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
  96         */
  97        class = dev->class >> 8;
  98        if (class != PCI_CLASS_STORAGE_IDE)
  99                return;
 100
 101        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
 102        if ((progif & 1) == 0) {
 103                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
 104                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
 105        }
 106        if ((progif & 4) == 0) {
 107                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
 108                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
 109        }
 110}
 111
 112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
 113          cobalt_legacy_ide_fixup);
 114
 115static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 116{
 117        unsigned short cfgword;
 118        unsigned char lt;
 119
 120        /* Enable Bus Mastering and fast back to back. */
 121        pci_read_config_word(dev, PCI_COMMAND, &cfgword);
 122        cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
 123        pci_write_config_word(dev, PCI_COMMAND, cfgword);
 124
 125        /* Enable both ide interfaces. ROM only enables primary one.  */
 126        pci_write_config_byte(dev, 0x40, 0xb);
 127
 128        /* Set latency timer to reasonable value. */
 129        pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
 130        if (lt < 64)
 131                pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 132        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 133}
 134
 135DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
 136         qube_raq_via_bmIDE_fixup);
 137
 138static void qube_raq_galileo_fixup(struct pci_dev *dev)
 139{
 140        if (dev->devfn != PCI_DEVFN(0, 0))
 141                return;
 142
 143        /* Fix PCI latency-timer and cache-line-size values in Galileo
 144         * host bridge.
 145         */
 146        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 147        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 148
 149        /*
 150         * The code described by the comment below has been removed
 151         * as it causes bus mastering by the Ethernet controllers
 152         * to break under any kind of network load. We always set
 153         * the retry timeouts to their maximum.
 154         *
 155         * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
 156         *
 157         * On all machines prior to Q2, we had the STOP line disconnected
 158         * from Galileo to VIA on PCI.  The new Galileo does not function
 159         * correctly unless we have it connected.
 160         *
 161         * Therefore we must set the disconnect/retry cycle values to
 162         * something sensible when using the new Galileo.
 163         */
 164
 165        printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
 166
 167#if 0
 168        if (dev->revision >= 0x10) {
 169                /* New Galileo, assumes PCI stop line to VIA is connected. */
 170                GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
 171        } else if (dev->revision == 0x1 || dev->revision == 0x2)
 172#endif
 173        {
 174                signed int timeo;
 175                /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
 176                timeo = GT_READ(GT_PCI0_TOR_OFS);
 177                /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
 178                GT_WRITE(GT_PCI0_TOR_OFS,
 179                        (0xff << 16) |          /* retry count */
 180                        (0xff << 8) |           /* timeout 1   */
 181                        0xff);                  /* timeout 0   */
 182
 183                /* enable PCI retry exceeded interrupt */
 184                GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
 185        }
 186}
 187
 188DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
 189         qube_raq_galileo_fixup);
 190
 191int cobalt_board_id;
 192
 193static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
 194{
 195        u8 id;
 196        int retval;
 197
 198        retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
 199        if (retval) {
 200                panic("Cannot read board ID");
 201                return;
 202        }
 203
 204        cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
 205
 206        printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
 207}
 208
 209DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
 210         qube_raq_via_board_id_fixup);
 211
 212static char irq_tab_qube1[] __initdata = {
 213  [COBALT_PCICONF_CPU]     = 0,
 214  [COBALT_PCICONF_ETH0]    = QUBE1_ETH0_IRQ,
 215  [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
 216  [COBALT_PCICONF_VIA]     = 0,
 217  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
 218  [COBALT_PCICONF_ETH1]    = 0
 219};
 220
 221static char irq_tab_cobalt[] __initdata = {
 222  [COBALT_PCICONF_CPU]     = 0,
 223  [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
 224  [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
 225  [COBALT_PCICONF_VIA]     = 0,
 226  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
 227  [COBALT_PCICONF_ETH1]    = ETH1_IRQ
 228};
 229
 230static char irq_tab_raq2[] __initdata = {
 231  [COBALT_PCICONF_CPU]     = 0,
 232  [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
 233  [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
 234  [COBALT_PCICONF_VIA]     = 0,
 235  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
 236  [COBALT_PCICONF_ETH1]    = ETH1_IRQ
 237};
 238
 239int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 240{
 241        if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
 242                return irq_tab_qube1[slot];
 243
 244        if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
 245                return irq_tab_raq2[slot];
 246
 247        return irq_tab_cobalt[slot];
 248}
 249
 250/* Do platform specific device initialization at pci_enable_device() time */
 251int pcibios_plat_dev_init(struct pci_dev *dev)
 252{
 253        return 0;
 254}
 255