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16#include <linux/errno.h>
17#include <linux/init.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/timex.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24
25#include <linux/debugfs.h>
26#include <linux/seq_file.h>
27
28#include <asm/io.h>
29#include <asm/mipsregs.h>
30#include <asm/irq_cpu.h>
31
32#include <asm/mach-jz4740/base.h>
33
34static void __iomem *jz_intc_base;
35static uint32_t jz_intc_wakeup;
36static uint32_t jz_intc_saved;
37
38#define JZ_REG_INTC_STATUS 0x00
39#define JZ_REG_INTC_MASK 0x04
40#define JZ_REG_INTC_SET_MASK 0x08
41#define JZ_REG_INTC_CLEAR_MASK 0x0c
42#define JZ_REG_INTC_PENDING 0x10
43
44#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
45
46static inline unsigned long intc_irq_bit(struct irq_data *data)
47{
48 return (unsigned long)irq_data_get_irq_chip_data(data);
49}
50
51static void intc_irq_unmask(struct irq_data *data)
52{
53 writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
54}
55
56static void intc_irq_mask(struct irq_data *data)
57{
58 writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
59}
60
61static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
62{
63 if (on)
64 jz_intc_wakeup |= intc_irq_bit(data);
65 else
66 jz_intc_wakeup &= ~intc_irq_bit(data);
67
68 return 0;
69}
70
71static struct irq_chip intc_irq_type = {
72 .name = "INTC",
73 .irq_mask = intc_irq_mask,
74 .irq_mask_ack = intc_irq_mask,
75 .irq_unmask = intc_irq_unmask,
76 .irq_set_wake = intc_irq_set_wake,
77};
78
79static irqreturn_t jz4740_cascade(int irq, void *data)
80{
81 uint32_t irq_reg;
82
83 irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
84
85 if (irq_reg)
86 generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
87
88 return IRQ_HANDLED;
89}
90
91static struct irqaction jz4740_cascade_action = {
92 .handler = jz4740_cascade,
93 .name = "JZ4740 cascade interrupt",
94};
95
96void __init arch_init_irq(void)
97{
98 int i;
99 mips_cpu_irq_init();
100
101 jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
102
103
104 writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
105
106 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
107 irq_set_chip_data(i, (void *)IRQ_BIT(i));
108 irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
109 }
110
111 setup_irq(2, &jz4740_cascade_action);
112}
113
114asmlinkage void plat_irq_dispatch(void)
115{
116 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
117 if (pending & STATUSF_IP2)
118 do_IRQ(2);
119 else if (pending & STATUSF_IP3)
120 do_IRQ(3);
121 else
122 spurious_interrupt();
123}
124
125void jz4740_intc_suspend(void)
126{
127 jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
128 writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
129 writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
130}
131
132void jz4740_intc_resume(void)
133{
134 writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
135 writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
136}
137
138#ifdef CONFIG_DEBUG_FS
139
140static inline void intc_seq_reg(struct seq_file *s, const char *name,
141 unsigned int reg)
142{
143 seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
144}
145
146static int intc_regs_show(struct seq_file *s, void *unused)
147{
148 intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
149 intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
150 intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
151
152 return 0;
153}
154
155static int intc_regs_open(struct inode *inode, struct file *file)
156{
157 return single_open(file, intc_regs_show, NULL);
158}
159
160static const struct file_operations intc_regs_operations = {
161 .open = intc_regs_open,
162 .read = seq_read,
163 .llseek = seq_lseek,
164 .release = single_release,
165};
166
167static int __init intc_debugfs_init(void)
168{
169 (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
170 NULL, NULL, &intc_regs_operations);
171 return 0;
172}
173subsys_initcall(intc_debugfs_init);
174
175#endif
176
