LXR linux/arch/mips/jazz/irq.c

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1992 Linus Torvalds
   7 * Copyright (C) 1994 - 2001, 2003, 07 Ralf Baechle
   8 */
   9#include <linux/clockchips.h>
  10#include <linux/init.h>
  11#include <linux/interrupt.h>
  12#include <linux/kernel.h>
  13#include <linux/smp.h>
  14#include <linux/spinlock.h>
  15#include <linux/irq.h>
  16
  17#include <asm/irq_cpu.h>
  18#include <asm/i8253.h>
  19#include <asm/i8259.h>
  20#include <asm/io.h>
  21#include <asm/jazz.h>
  22#include <asm/pgtable.h>
  23
  24static DEFINE_RAW_SPINLOCK(r4030_lock);
  25
  26static void enable_r4030_irq(struct irq_data *d)
  27{
  28        unsigned int mask = 1 << (d->irq - JAZZ_IRQ_START);
  29        unsigned long flags;
  30
  31        raw_spin_lock_irqsave(&r4030_lock, flags);
  32        mask |= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
  33        r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
  34        raw_spin_unlock_irqrestore(&r4030_lock, flags);
  35}
  36
  37void disable_r4030_irq(struct irq_data *d)
  38{
  39        unsigned int mask = ~(1 << (d->irq - JAZZ_IRQ_START));
  40        unsigned long flags;
  41
  42        raw_spin_lock_irqsave(&r4030_lock, flags);
  43        mask &= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
  44        r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
  45        raw_spin_unlock_irqrestore(&r4030_lock, flags);
  46}
  47
  48static struct irq_chip r4030_irq_type = {
  49        .name = "R4030",
  50        .irq_mask = disable_r4030_irq,
  51        .irq_unmask = enable_r4030_irq,
  52};
  53
  54void __init init_r4030_ints(void)
  55{
  56        int i;
  57
  58        for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
  59                irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
  60
  61        r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
  62        r4030_read_reg16(JAZZ_IO_IRQ_SOURCE);           /* clear pending IRQs */
  63        r4030_read_reg32(JAZZ_R4030_INVAL_ADDR);        /* clear error bits */
  64}
  65
  66/*
  67 * On systems with i8259-style interrupt controllers we assume for
  68 * driver compatibility reasons interrupts 0 - 15 to be the i8259
  69 * interrupts even if the hardware uses a different interrupt numbering.
  70 */
  71void __init arch_init_irq(void)
  72{
  73        /*
  74         * this is a hack to get back the still needed wired mapping
  75         * killed by init_mm()
  76         */
  77
  78        /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
  79        add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
  80        /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
  81        add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
  82        /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
  83        add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
  84
  85        init_i8259_irqs();                      /* Integrated i8259  */
  86        mips_cpu_irq_init();
  87        init_r4030_ints();
  88
  89        change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
  90}
  91
  92asmlinkage void plat_irq_dispatch(void)
  93{
  94        unsigned int pending = read_c0_cause() & read_c0_status();
  95        unsigned int irq;
  96
  97        if (pending & IE_IRQ4) {
  98                r4030_read_reg32(JAZZ_TIMER_REGISTER);
  99                do_IRQ(JAZZ_TIMER_IRQ);
 100        } else if (pending & IE_IRQ2) {
 101                irq = *(volatile u8 *)JAZZ_EISA_IRQ_ACK;
 102                do_IRQ(irq);
 103        } else if (pending & IE_IRQ1) {
 104                irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2;
 105                if (likely(irq > 0))
 106                        do_IRQ(irq + JAZZ_IRQ_START - 1);
 107                else
 108                        panic("Unimplemented loc_no_irq handler");
 109        }
 110}
 111
 112static void r4030_set_mode(enum clock_event_mode mode,
 113                           struct clock_event_device *evt)
 114{
 115        /* Nothing to do ...  */
 116}
 117
 118struct clock_event_device r4030_clockevent = {
 119        .name           = "r4030",
 120        .features       = CLOCK_EVT_FEAT_PERIODIC,
 121        .rating         = 300,
 122        .irq            = JAZZ_TIMER_IRQ,
 123        .set_mode       = r4030_set_mode,
 124};
 125
 126static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
 127{
 128        struct clock_event_device *cd = dev_id;
 129
 130        cd->event_handler(cd);
 131        return IRQ_HANDLED;
 132}
 133
 134static struct irqaction r4030_timer_irqaction = {
 135        .handler        = r4030_timer_interrupt,
 136        .flags          = IRQF_DISABLED | IRQF_TIMER,
 137        .name           = "R4030 timer",
 138};
 139
 140void __init plat_time_init(void)
 141{
 142        struct clock_event_device *cd = &r4030_clockevent;
 143        struct irqaction *action = &r4030_timer_irqaction;
 144        unsigned int cpu = smp_processor_id();
 145
 146        BUG_ON(HZ != 100);
 147
 148        cd->cpumask             = cpumask_of(cpu);
 149        clockevents_register_device(cd);
 150        action->dev_id = cd;
 151        setup_irq(JAZZ_TIMER_IRQ, action);
 152
 153        /*
 154         * Set clock to 100Hz.
 155         *
 156         * The R4030 timer receives an input clock of 1kHz which is divieded by
 157         * a programmable 4-bit divider.  This makes it fairly inflexible.
 158         */
 159        r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
 160        setup_pit_timer();
 161}
 162