/*
 *
 *  hda_intel.c - Implementation of primary alsa driver code base
 *                for Intel HD Audio.
 *
 *  Copyright(c) 2004 Intel Corporation. All rights reserved.
 *
 *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
 *                     PeiSen Hou <pshou@realtek.com.tw>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the Free
 *  Software Foundation; either version 2 of the License, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc., 59
 *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 *  CONTACTS:
 *
 *  Matt Jared          matt.jared@intel.com
 *  Andy Kopp           andy.kopp@intel.com
 *  Dan Kogan           dan.d.kogan@intel.com
 *
 *  CHANGES:
 *
 *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
 * 
 */

#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/mutex.h>
#include <linux/reboot.h>
#include <sound/core.h>
#include <sound/initval.h>
#include "hda_codec.h"


static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
static char *model[SNDRV_CARDS];
static int position_fix[SNDRV_CARDS];
static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
static int probe_only[SNDRV_CARDS];
static int single_cmd;
static int enable_msi = -1;
#ifdef CONFIG_SND_HDA_PATCH_LOADER
static char *patch[SNDRV_CARDS];
#endif
#ifdef CONFIG_SND_HDA_INPUT_BEEP
static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
                                        CONFIG_SND_HDA_INPUT_BEEP_MODE};
#endif

module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
module_param_array(model, charp, NULL, 0444);
MODULE_PARM_DESC(model, "Use the given board model.");
module_param_array(position_fix, int, NULL, 0444);
MODULE_PARM_DESC(position_fix, "DMA pointer read method."
                 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
module_param_array(bdl_pos_adj, int, NULL, 0644);
MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
module_param_array(probe_mask, int, NULL, 0444);
MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
module_param_array(probe_only, int, NULL, 0444);
MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
module_param(single_cmd, bool, 0444);
MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
                 "(for debugging only).");
module_param(enable_msi, int, 0444);
MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
#ifdef CONFIG_SND_HDA_PATCH_LOADER
module_param_array(patch, charp, NULL, 0444);
MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
#endif
#ifdef CONFIG_SND_HDA_INPUT_BEEP
module_param_array(beep_mode, int, NULL, 0444);
MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
                            "(0=off, 1=on, 2=mute switch on/off) (default=1).");
#endif

#ifdef CONFIG_SND_HDA_POWER_SAVE
static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
module_param(power_save, int, 0644);
MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
                 "(in second, 0 = disable).");

/* reset the HD-audio controller in power save mode.
 * this may give more power-saving, but will take longer time to
 * wake up.
 */
static int power_save_controller = 1;
module_param(power_save_controller, bool, 0644);
MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
#endif

MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
                         "{Intel, ICH6M},"
                         "{Intel, ICH7},"
                         "{Intel, ESB2},"
                         "{Intel, ICH8},"
                         "{Intel, ICH9},"
                         "{Intel, ICH10},"
                         "{Intel, PCH},"
                         "{Intel, CPT},"
                         "{Intel, PBG},"
                         "{Intel, SCH},"
                         "{ATI, SB450},"
                         "{ATI, SB600},"
                         "{ATI, RS600},"
                         "{ATI, RS690},"
                         "{ATI, RS780},"
                         "{ATI, R600},"
                         "{ATI, RV630},"
                         "{ATI, RV610},"
                         "{ATI, RV670},"
                         "{ATI, RV635},"
                         "{ATI, RV620},"
                         "{ATI, RV770},"
                         "{VIA, VT8251},"
                         "{VIA, VT8237A},"
                         "{SiS, SIS966},"
                         "{ULI, M5461}}");
MODULE_DESCRIPTION("Intel HDA driver");

#ifdef CONFIG_SND_VERBOSE_PRINTK
#define SFX     /* nop */
#else
#define SFX     "hda-intel: "
#endif

/*
 * registers
 */
#define ICH6_REG_GCAP                   0x00
#define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
#define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
#define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
#define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
#define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
#define ICH6_REG_VMIN                   0x02
#define ICH6_REG_VMAJ                   0x03
#define ICH6_REG_OUTPAY                 0x04
#define ICH6_REG_INPAY                  0x06
#define ICH6_REG_GCTL                   0x08
#define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
#define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
#define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
#define ICH6_REG_WAKEEN                 0x0c
#define ICH6_REG_STATESTS               0x0e
#define ICH6_REG_GSTS                   0x10
#define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
#define ICH6_REG_INTCTL                 0x20
#define ICH6_REG_INTSTS                 0x24
#define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
#define ICH6_REG_SYNC                   0x34    
#define ICH6_REG_CORBLBASE              0x40
#define ICH6_REG_CORBUBASE              0x44
#define ICH6_REG_CORBWP                 0x48
#define ICH6_REG_CORBRP                 0x4a
#define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
#define ICH6_REG_CORBCTL                0x4c
#define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
#define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
#define ICH6_REG_CORBSTS                0x4d
#define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
#define ICH6_REG_CORBSIZE               0x4e

#define ICH6_REG_RIRBLBASE              0x50
#define ICH6_REG_RIRBUBASE              0x54
#define ICH6_REG_RIRBWP                 0x58
#define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
#define ICH6_REG_RINTCNT                0x5a
#define ICH6_REG_RIRBCTL                0x5c
#define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
#define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
#define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
#define ICH6_REG_RIRBSTS                0x5d
#define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
#define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
#define ICH6_REG_RIRBSIZE               0x5e

#define ICH6_REG_IC                     0x60
#define ICH6_REG_IR                     0x64
#define ICH6_REG_IRS                    0x68
#define   ICH6_IRS_VALID        (1<<1)
#define   ICH6_IRS_BUSY         (1<<0)

#define ICH6_REG_DPLBASE                0x70
#define ICH6_REG_DPUBASE                0x74
#define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */
#define ICH6_REG_SD_CTL                 0x00
#define ICH6_REG_SD_STS                 0x03
#define ICH6_REG_SD_LPIB                0x04
#define ICH6_REG_SD_CBL                 0x08
#define ICH6_REG_SD_LVI                 0x0c
#define ICH6_REG_SD_FIFOW               0x0e
#define ICH6_REG_SD_FIFOSIZE            0x10
#define ICH6_REG_SD_FORMAT              0x12
#define ICH6_REG_SD_BDLPL               0x18
#define ICH6_REG_SD_BDLPU               0x1c

/* PCI space */
#define ICH6_PCIREG_TCSEL       0x44

/*
 * other constants
 */

/* max number of SDs */
/* ICH, ATI and VIA have 4 playback and 4 capture */
#define ICH6_NUM_CAPTURE        4
#define ICH6_NUM_PLAYBACK       4

/* ULI has 6 playback and 5 capture */
#define ULI_NUM_CAPTURE         5
#define ULI_NUM_PLAYBACK        6

/* ATI HDMI has 1 playback and 0 capture */
#define ATIHDMI_NUM_CAPTURE     0
#define ATIHDMI_NUM_PLAYBACK    1

/* TERA has 4 playback and 3 capture */
#define TERA_NUM_CAPTURE        3
#define TERA_NUM_PLAYBACK       4

/* this number is statically defined for simplicity */
#define MAX_AZX_DEV             16

/* max number of fragments - we may use more if allocating more pages for BDL */
#define BDL_SIZE                4096
#define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
#define AZX_MAX_FRAG            32
/* max buffer size - no h/w limit, you can increase as you like */
#define AZX_MAX_BUF_SIZE        (1024*1024*1024)

/* RIRB int mask: overrun[2], response[0] */
#define RIRB_INT_RESPONSE       0x01
#define RIRB_INT_OVERRUN        0x04
#define RIRB_INT_MASK           0x05

/* STATESTS int mask: S3,SD2,SD1,SD0 */
#define AZX_MAX_CODECS          8
#define AZX_DEFAULT_CODECS      4
#define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)

/* SD_CTL bits */
#define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
#define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
#define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
#define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
#define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
#define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
#define SD_CTL_STREAM_TAG_SHIFT 20

/* SD_CTL and SD_STS */
#define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
#define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
#define SD_INT_COMPLETE         0x04    /* completion interrupt */
#define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
                                 SD_INT_COMPLETE)

/* SD_STS */
#define SD_STS_FIFO_READY       0x20    /* FIFO ready */

/* INTCTL and INTSTS */
#define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
#define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
#define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */

/* below are so far hardcoded - should read registers in future */
#define ICH6_MAX_CORB_ENTRIES   256
#define ICH6_MAX_RIRB_ENTRIES   256

/* position fix mode */
enum {
        POS_FIX_AUTO,
        POS_FIX_LPIB,
        POS_FIX_POSBUF,
        POS_FIX_VIACOMBO,
};

/* Defines for ATI HD Audio support in SB450 south bridge */
#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
#define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02

/* Defines for Nvidia HDA support */
#define NVIDIA_HDA_TRANSREG_ADDR      0x4e
#define NVIDIA_HDA_ENABLE_COHBITS     0x0f
#define NVIDIA_HDA_ISTRM_COH          0x4d
#define NVIDIA_HDA_OSTRM_COH          0x4c
#define NVIDIA_HDA_ENABLE_COHBIT      0x01

/* Defines for Intel SCH HDA snoop control */
#define INTEL_SCH_HDA_DEVC      0x78
#define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)

/* Define IN stream 0 FIFO size offset in VIA controller */
#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
/* Define VIA HD Audio Device ID*/
#define VIA_HDAC_DEVICE_ID              0x3288

/* HD Audio class code */
#define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403

/*
 */

struct azx_dev {
        struct snd_dma_buffer bdl; /* BDL buffer */
        u32 *posbuf;            /* position buffer pointer */

        unsigned int bufsize;   /* size of the play buffer in bytes */
        unsigned int period_bytes; /* size of the period in bytes */
        unsigned int frags;     /* number for period in the play buffer */
        unsigned int fifo_size; /* FIFO size */
        unsigned long start_wallclk;    /* start + minimum wallclk */
        unsigned long period_wallclk;   /* wallclk for period */

        void __iomem *sd_addr;  /* stream descriptor pointer */

        u32 sd_int_sta_mask;    /* stream int status mask */

        /* pcm support */
        struct snd_pcm_substream *substream;    /* assigned substream,
                                                 * set in PCM open
                                                 */
        unsigned int format_val;        /* format value to be set in the
                                         * controller and the codec
                                         */
        unsigned char stream_tag;       /* assigned stream */
        unsigned char index;            /* stream index */
        int device;                     /* last device number assigned to */

        unsigned int opened :1;
        unsigned int running :1;
        unsigned int irq_pending :1;
        /*
         * For VIA:
         *  A flag to ensure DMA position is 0
         *  when link position is not greater than FIFO size
         */
        unsigned int insufficient :1;
};

/* CORB/RIRB */
struct azx_rb {
        u32 *buf;               /* CORB/RIRB buffer
                                 * Each CORB entry is 4byte, RIRB is 8byte
                                 */
        dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
        /* for RIRB */
        unsigned short rp, wp;  /* read/write pointers */
        int cmds[AZX_MAX_CODECS];       /* number of pending requests */
        u32 res[AZX_MAX_CODECS];        /* last read value */
};

struct azx {
        struct snd_card *card;
        struct pci_dev *pci;
        int dev_index;

        /* chip type specific */
        int driver_type;
        int playback_streams;
        int playback_index_offset;
        int capture_streams;
        int capture_index_offset;
        int num_streams;

        /* pci resources */
        unsigned long addr;
        void __iomem *remap_addr;
        int irq;

        /* locks */
        spinlock_t reg_lock;
        struct mutex open_mutex;

        /* streams (x num_streams) */
        struct azx_dev *azx_dev;

        /* PCM */
        struct snd_pcm *pcm[HDA_MAX_PCMS];

        /* HD codec */
        unsigned short codec_mask;
        int  codec_probe_mask; /* copied from probe_mask option */
        struct hda_bus *bus;
        unsigned int beep_mode;

        /* CORB/RIRB */
        struct azx_rb corb;
        struct azx_rb rirb;

        /* CORB/RIRB and position buffers */
        struct snd_dma_buffer rb;
        struct snd_dma_buffer posbuf;

        /* flags */
        int position_fix[2]; /* for both playback/capture streams */
        int poll_count;
        unsigned int running :1;
        unsigned int initialized :1;
        unsigned int single_cmd :1;
        unsigned int polling_mode :1;
        unsigned int msi :1;
        unsigned int irq_pending_warned :1;
        unsigned int probing :1; /* codec probing phase */

        /* for debugging */
        unsigned int last_cmd[AZX_MAX_CODECS];

        /* for pending irqs */
        struct work_struct irq_pending_work;

        /* reboot notifier (for mysterious hangup problem at power-down) */
        struct notifier_block reboot_notifier;
};

/* driver types */
enum {
        AZX_DRIVER_ICH,
        AZX_DRIVER_PCH,
        AZX_DRIVER_SCH,
        AZX_DRIVER_ATI,
        AZX_DRIVER_ATIHDMI,
        AZX_DRIVER_VIA,
        AZX_DRIVER_SIS,
        AZX_DRIVER_ULI,
        AZX_DRIVER_NVIDIA,
        AZX_DRIVER_TERA,
        AZX_DRIVER_CTX,
        AZX_DRIVER_GENERIC,
        AZX_NUM_DRIVERS, /* keep this as last entry */
};

static char *driver_short_names[] __devinitdata = {
        [AZX_DRIVER_ICH] = "HDA Intel",
        [AZX_DRIVER_PCH] = "HDA Intel PCH",
        [AZX_DRIVER_SCH] = "HDA Intel MID",
        [AZX_DRIVER_ATI] = "HDA ATI SB",
        [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
        [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
        [AZX_DRIVER_SIS] = "HDA SIS966",
        [AZX_DRIVER_ULI] = "HDA ULI M5461",
        [AZX_DRIVER_NVIDIA] = "HDA NVidia",
        [AZX_DRIVER_TERA] = "HDA Teradici", 
        [AZX_DRIVER_CTX] = "HDA Creative", 
        [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
};

/*
 * macros for easy use
 */
#define azx_writel(chip,reg,value) \
        writel(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readl(chip,reg) \
        readl((chip)->remap_addr + ICH6_REG_##reg)
#define azx_writew(chip,reg,value) \
        writew(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readw(chip,reg) \
        readw((chip)->remap_addr + ICH6_REG_##reg)
#define azx_writeb(chip,reg,value) \
        writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readb(chip,reg) \
        readb((chip)->remap_addr + ICH6_REG_##reg)

#define azx_sd_writel(dev,reg,value) \
        writel(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readl(dev,reg) \
        readl((dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_writew(dev,reg,value) \
        writew(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readw(dev,reg) \
        readw((dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_writeb(dev,reg,value) \
        writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readb(dev,reg) \
        readb((dev)->sd_addr + ICH6_REG_##reg)

/* for pcm support */
#define get_azx_dev(substream) (substream->runtime->private_data)

static int azx_acquire_irq(struct azx *chip, int do_disconnect);
static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
/*
 * Interface for HD codec
 */

/*
 * CORB / RIRB interface
 */
static int azx_alloc_cmd_io(struct azx *chip)
{
        int err;

        /* single page (at least 4096 bytes) must suffice for both ringbuffes */
        err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
                                  snd_dma_pci_data(chip->pci),
                                  PAGE_SIZE, &chip->rb);
        if (err < 0) {
                snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
                return err;
        }
        return 0;
}

static void azx_init_cmd_io(struct azx *chip)
{
        spin_lock_irq(&chip->reg_lock);
        /* CORB set up */
        chip->corb.addr = chip->rb.addr;
        chip->corb.buf = (u32 *)chip->rb.area;
        azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
        azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));

        /* set the corb size to 256 entries (ULI requires explicitly) */
        azx_writeb(chip, CORBSIZE, 0x02);
        /* set the corb write pointer to 0 */
        azx_writew(chip, CORBWP, 0);
        /* reset the corb hw read pointer */
        azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
        /* enable corb dma */
        azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);

        /* RIRB set up */
        chip->rirb.addr = chip->rb.addr + 2048;
        chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
        chip->rirb.wp = chip->rirb.rp = 0;
        memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
        azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
        azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));

        /* set the rirb size to 256 entries (ULI requires explicitly) */
        azx_writeb(chip, RIRBSIZE, 0x02);
        /* reset the rirb hw write pointer */
        azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
        /* set N=1, get RIRB response interrupt for new entry */
        if (chip->driver_type == AZX_DRIVER_CTX)
                azx_writew(chip, RINTCNT, 0xc0);
        else
                azx_writew(chip, RINTCNT, 1);
        /* enable rirb dma and response irq */
        azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
        spin_unlock_irq(&chip->reg_lock);
}

static void azx_free_cmd_io(struct azx *chip)
{
        spin_lock_irq(&chip->reg_lock);
        /* disable ringbuffer DMAs */
        azx_writeb(chip, RIRBCTL, 0);
        azx_writeb(chip, CORBCTL, 0);
        spin_unlock_irq(&chip->reg_lock);
}

static unsigned int azx_command_addr(u32 cmd)
{
        unsigned int addr = cmd >> 28;

        if (addr >= AZX_MAX_CODECS) {
                snd_BUG();
                addr = 0;
        }

        return addr;
}

static unsigned int azx_response_addr(u32 res)
{
        unsigned int addr = res & 0xf;

        if (addr >= AZX_MAX_CODECS) {
                snd_BUG();
                addr = 0;
        }

        return addr;
}

/* send a command */
static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
{
        struct azx *chip = bus->private_data;
        unsigned int addr = azx_command_addr(val);
        unsigned int wp;

        spin_lock_irq(&chip->reg_lock);

        /* add command to corb */
        wp = azx_readb(chip, CORBWP);
        wp++;
        wp %= ICH6_MAX_CORB_ENTRIES;

        chip->rirb.cmds[addr]++;
        chip->corb.buf[wp] = cpu_to_le32(val);
        azx_writel(chip, CORBWP, wp);

        spin_unlock_irq(&chip->reg_lock);

        return 0;
}

#define ICH6_RIRB_EX_UNSOL_EV   (1<<4)

/* retrieve RIRB entry - called from interrupt handler */
static void azx_update_rirb(struct azx *chip)
{
        unsigned int rp, wp;
        unsigned int addr;
        u32 res, res_ex;

        wp = azx_readb(chip, RIRBWP);
        if (wp == chip->rirb.wp)
                return;
        chip->rirb.wp = wp;

        while (chip->rirb.rp != wp) {
                chip->rirb.rp++;
                chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;

                rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
                res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
                res = le32_to_cpu(chip->rirb.buf[rp]);
                addr = azx_response_addr(res_ex);
                if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
                        snd_hda_queue_unsol_event(chip->bus, res, res_ex);
                else if (chip->rirb.cmds[addr]) {
                        chip->rirb.res[addr] = res;
                        smp_wmb();
                        chip->rirb.cmds[addr]--;
                } else
                        snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
                                   "last cmd=%#08x\n",
                                   res, res_ex,
                                   chip->last_cmd[addr]);
        }
}

/* receive a response */
static unsigned int azx_rirb_get_response(struct hda_bus *bus,
                                          unsigned int addr)
{
        struct azx *chip = bus->private_data;
        unsigned long timeout;
        int do_poll = 0;

 again:
        timeout = jiffies + msecs_to_jiffies(1000);
        for (;;) {
                if (chip->polling_mode || do_poll) {
                        spin_lock_irq(&chip->reg_lock);
                        azx_update_rirb(chip);
                        spin_unlock_irq(&chip->reg_lock);
                }
                if (!chip->rirb.cmds[addr]) {
                        smp_rmb();
                        bus->rirb_error = 0;

                        if (!do_poll)
                                chip->poll_count = 0;
                        return chip->rirb.res[addr]; /* the last value */
                }
                if (time_after(jiffies, timeout))
                        break;
                if (bus->needs_damn_long_delay)
                        msleep(2); /* temporary workaround */
                else {
                        udelay(10);
                        cond_resched();
                }
        }

        if (!chip->polling_mode && chip->poll_count < 2) {
                snd_printdd(SFX "azx_get_response timeout, "
                           "polling the codec once: last cmd=0x%08x\n",
                           chip->last_cmd[addr]);
                do_poll = 1;
                chip->poll_count++;
                goto again;
        }


        if (!chip->polling_mode) {
                snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
                           "switching to polling mode: last cmd=0x%08x\n",
                           chip->last_cmd[addr]);
                chip->polling_mode = 1;
                goto again;
        }

        if (chip->msi) {
                snd_printk(KERN_WARNING SFX "No response from codec, "
                           "disabling MSI: last cmd=0x%08x\n",
                           chip->last_cmd[addr]);
                free_irq(chip->irq, chip);
                chip->irq = -1;
                pci_disable_msi(chip->pci);
                chip->msi = 0;
                if (azx_acquire_irq(chip, 1) < 0) {
                        bus->rirb_error = 1;
                        return -1;
                }
                goto again;
        }

        if (chip->probing) {
                /* If this critical timeout happens during the codec probing
                 * phase, this is likely an access to a non-existing codec
                 * slot.  Better to return an error and reset the system.
                 */
                return -1;
        }

        /* a fatal communication error; need either to reset or to fallback
         * to the single_cmd mode
         */
        bus->rirb_error = 1;
        if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
                bus->response_reset = 1;
                return -1; /* give a chance to retry */
        }

        snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
                   "switching to single_cmd mode: last cmd=0x%08x\n",
                   chip->last_cmd[addr]);
        chip->single_cmd = 1;
        bus->response_reset = 0;
        /* release CORB/RIRB */
        azx_free_cmd_io(chip);
        /* disable unsolicited responses */
        azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
        return -1;
}

/*
 * Use the single immediate command instead of CORB/RIRB for simplicity
 *
 * Note: according to Intel, this is not preferred use.  The command was
 *       intended for the BIOS only, and may get confused with unsolicited
 *       responses.  So, we shouldn't use it for normal operation from the
 *       driver.
 *       I left the codes, however, for debugging/testing purposes.
 */

/* receive a response */
static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
{
        int timeout = 50;

        while (timeout--) {
                /* check IRV busy bit */
                if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
                        /* reuse rirb.res as the response return value */
                        chip->rirb.res[addr] = azx_readl(chip, IR);
                        return 0;
                }
                udelay(1);
        }
        if (printk_ratelimit())
                snd_printd(SFX "get_response timeout: IRS=0x%x\n",
                           azx_readw(chip, IRS));
        chip->rirb.res[addr] = -1;
        return -EIO;
}

/* send a command */
static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
{
        struct azx *chip = bus->private_data;
        unsigned int addr = azx_command_addr(val);
        int timeout = 50;

        bus->rirb_error = 0;
        while (timeout--) {
                /* check ICB busy bit */
                if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
                        /* Clear IRV valid bit */
                        azx_writew(chip, IRS, azx_readw(chip, IRS) |
                                   ICH6_IRS_VALID);
                        azx_writel(chip, IC, val);
                        azx_writew(chip, IRS, azx_readw(chip, IRS) |
                                   ICH6_IRS_BUSY);
                        return azx_single_wait_for_response(chip, addr);
                }
                udelay(1);
        }
        if (printk_ratelimit())
                snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
                           azx_readw(chip, IRS), val);
        return -EIO;
}

/* receive a response */
static unsigned int azx_single_get_response(struct hda_bus *bus,
                                            unsigned int addr)
{
        struct azx *chip = bus->private_data;
        return chip->rirb.res[addr];
}

/*
 * The below are the main callbacks from hda_codec.
 *
 * They are just the skeleton to call sub-callbacks according to the
 * current setting of chip->single_cmd.
 */

/* send a command */
static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
{
        struct azx *chip = bus->private_data;

        chip->last_cmd[azx_command_addr(val)] = val;
        if (chip->single_cmd)
                return azx_single_send_cmd(bus, val);
        else
                return azx_corb_send_cmd(bus, val);
}

/* get a response */
static unsigned int azx_get_response(struct hda_bus *bus,
                                     unsigned int addr)
{
        struct azx *chip = bus->private_data;
        if (chip->single_cmd)
                return azx_single_get_response(bus, addr);
        else
                return azx_rirb_get_response(bus, addr);
}

#ifdef CONFIG_SND_HDA_POWER_SAVE
static void azx_power_notify(struct hda_bus *bus);
#endif

/* reset codec link */
static int azx_reset(struct azx *chip, int full_reset)
{
        int count;

        if (!full_reset)
                goto __skip;

        /* clear STATESTS */
        azx_writeb(chip, STATESTS, STATESTS_INT_MASK);

        /* reset controller */
        azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);

        count = 50;
        while (azx_readb(chip, GCTL) && --count)
                msleep(1);

        /* delay for >= 100us for codec PLL to settle per spec
         * Rev 0.9 section 5.5.1
         */
        msleep(1);

        /* Bring controller out of reset */
        azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);

        count = 50;
        while (!azx_readb(chip, GCTL) && --count)
                msleep(1);

        /* Brent Chartrand said to wait >= 540us for codecs to initialize */
        msleep(1);

      __skip:
        /* check to see if controller is ready */
        if (!azx_readb(chip, GCTL)) {
                snd_printd(SFX "azx_reset: controller not ready!\n");
                return -EBUSY;
        }

        /* Accept unsolicited responses */
        if (!chip->single_cmd)
                azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
                           ICH6_GCTL_UNSOL);

        /* detect codecs */
        if (!chip->codec_mask) {
                chip->codec_mask = azx_readw(chip, STATESTS);
                snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
        }

        return 0;
}


/*
 * Lowlevel interface
 */  

/* enable interrupts */
static void azx_int_enable(struct azx *chip)
{
        /* enable controller CIE and GIE */
        azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
                   ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
}

/* disable interrupts */
static void azx_int_disable(struct azx *chip)
{
        int i;

        /* disable interrupts in stream descriptor */
        for (i = 0; i < chip->num_streams; i++) {
                struct azx_dev *azx_dev = &chip->azx_dev[i];
                azx_sd_writeb(azx_dev, SD_CTL,
                              azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
        }

        /* disable SIE for all streams */
        azx_writeb(chip, INTCTL, 0);

        /* disable controller CIE and GIE */
        azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
                   ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
}

/* clear interrupts */
static void azx_int_clear(struct azx *chip)
{
        int i;

        /* clear stream status */
        for (i = 0; i < chip->num_streams; i++) {
                struct azx_dev *azx_dev = &chip->azx_dev[i];
                azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
        }

        /* clear STATESTS */
        azx_writeb(chip, STATESTS, STATESTS_INT_MASK);

        /* clear rirb status */
        azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);

        /* clear int status */
        azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
}

/* start a stream */
static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
{
        /*
         * Before stream start, initialize parameter
         */
        azx_dev->insufficient = 1;

        /* enable SIE */
        azx_writel(chip, INTCTL,
                   azx_readl(chip, INTCTL) | (1 << azx_dev->index));
        /* set DMA start and interrupt mask */
        azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
                      SD_CTL_DMA_START | SD_INT_MASK);
}

/* stop DMA */
static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
{
        azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
                      ~(SD_CTL_DMA_START | SD_INT_MASK));
        azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
}

/* stop a stream */
static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
{
        azx_stream_clear(chip, azx_dev);

        /* disable SIE */
        azx_writel(chip, INTCTL,
                   azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
}


/*
 * reset and start the controller registers
 */
static void azx_init_chip(struct azx *chip, int full_reset)
{
        if (chip->initialized)
                return;

        /* reset controller */
        azx_reset(chip, full_reset);

        /* initialize interrupts */
        azx_int_clear(chip);
        azx_int_enable(chip);

        /* initialize the codec command I/O */
        if (!chip->single_cmd)
                azx_init_cmd_io(chip);

        /* program the position buffer */
        azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
        azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));

        chip->initialized = 1;
}

/*
 * initialize the PCI registers
 */
/* update bits in a PCI register byte */
static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
                            unsigned char mask, unsigned char val)
{
        unsigned char data;

        pci_read_config_byte(pci, reg, &data);
        data &= ~mask;
        data |= (val & mask);
        pci_write_config_byte(pci, reg, data);
}

static void azx_init_pci(struct azx *chip)
{
        unsigned short snoop;

        /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
         * TCSEL == Traffic Class Select Register, which sets PCI express QOS
         * Ensuring these bits are 0 clears playback static on some HD Audio
         * codecs.
         * The PCI register TCSEL is defined in the Intel manuals.
         */
        if (chip->driver_type != AZX_DRIVER_ATI &&
            chip->driver_type != AZX_DRIVER_ATIHDMI)
                update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);

        switch (chip->driver_type) {
        case AZX_DRIVER_ATI:
                /* For ATI SB450 azalia HD audio, we need to enable snoop */
                update_pci_byte(chip->pci,
                                ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
                                0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
                break;
        case AZX_DRIVER_NVIDIA:
                /* For NVIDIA HDA, enable snoop */
                update_pci_byte(chip->pci,
                                NVIDIA_HDA_TRANSREG_ADDR,
                                0x0f, NVIDIA_HDA_ENABLE_COHBITS);
                update_pci_byte(chip->pci,
                                NVIDIA_HDA_ISTRM_COH,
                                0x01, NVIDIA_HDA_ENABLE_COHBIT);
                update_pci_byte(chip->pci,
                                NVIDIA_HDA_OSTRM_COH,
                                0x01, NVIDIA_HDA_ENABLE_COHBIT);
                break;
        case AZX_DRIVER_SCH:
        case AZX_DRIVER_PCH:
                pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
                if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
                        pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
                                snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
                        pci_read_config_word(chip->pci,
                                INTEL_SCH_HDA_DEVC, &snoop);
                        snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
                                (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
                                ? "Failed" : "OK");
                }
                break;

        }
}


static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);

/*
 * interrupt handler
 */
static irqreturn_t azx_interrupt(int irq, void *dev_id)
{
        struct azx *chip = dev_id;
        struct azx_dev *azx_dev;
        u32 status;
        u8 sd_status;
        int i, ok;

        spin_lock(&chip->reg_lock);

        status = azx_readl(chip, INTSTS);
        if (status == 0) {
                spin_unlock(&chip->reg_lock);
                return IRQ_NONE;
        }
        
        for (i = 0; i < chip->num_streams; i++) {
                azx_dev = &chip->azx_dev[i];
                if (status & azx_dev->sd_int_sta_mask) {
                        sd_status = azx_sd_readb(azx_dev, SD_STS);
                        azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
                        if (!azx_dev->substream || !azx_dev->running ||
                            !(sd_status & SD_INT_COMPLETE))
                                continue;
                        /* check whether this IRQ is really acceptable */
                        ok = azx_position_ok(chip, azx_dev);
                        if (ok == 1) {
                                azx_dev->irq_pending = 0;
                                spin_unlock(&chip->reg_lock);
                                snd_pcm_period_elapsed(azx_dev->substream);
                                spin_lock(&chip->reg_lock);
                        } else if (ok == 0 && chip->bus && chip->bus->workq) {
                                /* bogus IRQ, process it later */
                                azx_dev->irq_pending = 1;
                                queue_work(chip->bus->workq,
                                           &chip->irq_pending_work);
                        }
                }
        }

        /* clear rirb int */
        status = azx_readb(chip, RIRBSTS);
        if (status & RIRB_INT_MASK) {
                if (status & RIRB_INT_RESPONSE) {
                        if (chip->driver_type == AZX_DRIVER_CTX)
                                udelay(80);
                        azx_update_rirb(chip);
                }
                azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
        }

#if 0
        /* clear state status int */
        if (azx_readb(chip, STATESTS) & 0x04)
                azx_writeb(chip, STATESTS, 0x04);
#endif
        spin_unlock(&chip->reg_lock);
        
        return IRQ_HANDLED;
}


/*
 * set up a BDL entry
 */
static int setup_bdle(struct snd_pcm_substream *substream,
                      struct azx_dev *azx_dev, u32 **bdlp,
                      int ofs, int size, int with_ioc)
{
        u32 *bdl = *bdlp;

        while (size > 0) {
                dma_addr_t addr;
                int chunk;

                if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
                        return -EINVAL;

                addr = snd_pcm_sgbuf_get_addr(substream, ofs);
                /* program the address field of the BDL entry */
                bdl[0] = cpu_to_le32((u32)addr);
                bdl[1] = cpu_to_le32(upper_32_bits(addr));
                /* program the size field of the BDL entry */
                chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
                bdl[2] = cpu_to_le32(chunk);
                /* program the IOC to enable interrupt
                 * only when the whole fragment is processed
                 */
                size -= chunk;
                bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
                bdl += 4;
                azx_dev->frags++;
                ofs += chunk;
        }
        *bdlp = bdl;
        return ofs;
}

/*
 * set up BDL entries
 */
static int azx_setup_periods(struct azx *chip,
                             struct snd_pcm_substream *substream,
                             struct azx_dev *azx_dev)
{
        u32 *bdl;
        int i, ofs, periods, period_bytes;
        int pos_adj;

        /* reset BDL address */
        azx_sd_writel(azx_dev, SD_BDLPL, 0);
        azx_sd_writel(azx_dev, SD_BDLPU, 0);

        period_bytes = azx_dev->period_bytes;
        periods = azx_dev->bufsize / period_bytes;

        /* program the initial BDL entries */
        bdl = (u32 *)azx_dev->bdl.area;
        ofs = 0;
        azx_dev->frags = 0;
        pos_adj = bdl_pos_adj[chip->dev_index];
        if (pos_adj > 0) {
                struct snd_pcm_runtime *runtime = substream->runtime;
                int pos_align = pos_adj;
                pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
                if (!pos_adj)
                        pos_adj = pos_align;
                else
                        pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
                                pos_align;
                pos_adj = frames_to_bytes(runtime, pos_adj);
                if (pos_adj >= period_bytes) {
                        snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
                                   bdl_pos_adj[chip->dev_index]);
                        pos_adj = 0;
                } else {
                        ofs = setup_bdle(substream, azx_dev,
                                         &bdl, ofs, pos_adj,
                                         !substream->runtime->no_period_wakeup);
                        if (ofs < 0)
                                goto error;
                }
        } else
                pos_adj = 0;
        for (i = 0; i < periods; i++) {
                if (i == periods - 1 && pos_adj)
                        ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
                                         period_bytes - pos_adj, 0);
                else
                        ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
                                         period_bytes,
                                         !substream->runtime->no_period_wakeup);
                if (ofs < 0)
                        goto error;
        }
        return 0;

 error:
        snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
                   azx_dev->bufsize, period_bytes);
        return -EINVAL;
}

/* reset stream */
static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
{
        unsigned char val;
        int timeout;

        azx_stream_clear(chip, azx_dev);

        azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
                      SD_CTL_STREAM_RESET);
        udelay(3);
        timeout = 300;
        while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
               --timeout)
                ;
        val &= ~SD_CTL_STREAM_RESET;
        azx_sd_writeb(azx_dev, SD_CTL, val);
        udelay(3);

        timeout = 300;
        /* waiting for hardware to report that the stream is out of reset */
        while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
               --timeout)
                ;

        /* reset first position - may not be synced with hw at this time */
        *azx_dev->posbuf = 0;
}

/*
 * set up the SD for streaming
 */
static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
{
        /* make sure the run bit is zero for SD */
        azx_stream_clear(chip, azx_dev);
        /* program the stream_tag */
        azx_sd_writel(azx_dev, SD_CTL,
                      (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
                      (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));

        /* program the length of samples in cyclic buffer */
        azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);

        /* program the stream format */
        /* this value needs to be the same as the one programmed */
        azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);

        /* program the stream LVI (last valid index) of the BDL */
        azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);

        /* program the BDL address */
        /* lower BDL address */
        azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
        /* upper BDL address */
        azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));

        /* enable the position buffer */
        if (chip->position_fix[0] != POS_FIX_LPIB ||
            chip->position_fix[1] != POS_FIX_LPIB) {
                if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
                        azx_writel(chip, DPLBASE,
                                (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
        }

        /* set the interrupt enable bits in the descriptor control register */
        azx_sd_writel(azx_dev, SD_CTL,
                      azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);

        return 0;
}

/*
 * Probe the given codec address
 */
static int probe_codec(struct azx *chip, int addr)
{
        unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
                (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
        unsigned int res;

        mutex_lock(&chip->bus->cmd_mutex);
        chip->probing = 1;
        azx_send_cmd(chip->bus, cmd);
        res = azx_get_response(chip->bus, addr);
        chip->probing = 0;
        mutex_unlock(&chip->bus->cmd_mutex);
        if (res == -1)
                return -EIO;
        snd_printdd(SFX "codec #%d probed OK\n", addr);
        return 0;
}

static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
                                 struct hda_pcm *cpcm);
static void azx_stop_chip(struct azx *chip);

static void azx_bus_reset(struct hda_bus *bus)
{
        struct azx *chip = bus->private_data;

        bus->in_reset = 1;
        azx_stop_chip(chip);
        azx_init_chip(chip, 1);
#ifdef CONFIG_PM
        if (chip->initialized) {
                int i;

                for (i = 0; i < HDA_MAX_PCMS; i++)
                        snd_pcm_suspend_all(chip->pcm[i]);
                snd_hda_suspend(chip->bus);
                snd_hda_resume(chip->bus);
        }
#endif
        bus->in_reset = 0;
}

/*
 * Codec initialization
 */

/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
        [AZX_DRIVER_NVIDIA] = 8,
        [AZX_DRIVER_TERA] = 1,
};

static int __devinit azx_codec_create(struct azx *chip, const char *model)
{
        struct hda_bus_template bus_temp;
        int c, codecs, err;
        int max_slots;

        memset(&bus_temp, 0, sizeof(bus_temp));
        bus_temp.private_data = chip;
        bus_temp.modelname = model;
        bus_temp.pci = chip->pci;
        bus_temp.ops.command = azx_send_cmd;
        bus_temp.ops.get_response = azx_get_response;
        bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
        bus_temp.ops.bus_reset = azx_bus_reset;
#ifdef CONFIG_SND_HDA_POWER_SAVE
        bus_temp.power_save = &power_save;
        bus_temp.ops.pm_notify = azx_power_notify;
#endif

        err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
        if (err < 0)
                return err;

        if (chip->driver_type == AZX_DRIVER_NVIDIA)
                chip->bus->needs_damn_long_delay = 1;

        codecs = 0;
        max_slots = azx_max_codecs[chip->driver_type];
        if (!max_slots)
                max_slots = AZX_DEFAULT_CODECS;

        /* First try to probe all given codec slots */
        for (c = 0; c < max_slots; c++) {
                if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
                        if (probe_codec(chip, c) < 0) {
                                /* Some BIOSen give you wrong codec addresses
                                 * that don't exist
                                 */
                                snd_printk(KERN_WARNING SFX
                                           "Codec #%d probe error; "
                                           "disabling it...\n", c);
                                chip->codec_mask &= ~(1 << c);
                                /* More badly, accessing to a non-existing
                                 * codec often screws up the controller chip,
                                 * and disturbs the further communications.
                                 * Thus if an error occurs during probing,
                                 * better to reset the controller chip to
                                 * get back to the sanity state.
                                 */
                                azx_stop_chip(chip);
                                azx_init_chip(chip, 1);
                        }
                }
        }

        /* Then create codec instances */
        for (c = 0; c < max_slots; c++) {
                if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
                        struct hda_codec *codec;
                        err = snd_hda_codec_new(chip->bus, c, &codec);
                        if (err < 0)
                                continue;
                        codec->beep_mode = chip->beep_mode;
                        codecs++;
                }
        }
        if (!codecs) {
                snd_printk(KERN_ERR SFX "no codecs initialized\n");
                return -ENXIO;
        }
        return 0;
}

/* configure each codec instance */
static int __devinit azx_codec_configure(struct azx *chip)
{
        struct hda_codec *codec;
        list_for_each_entry(codec, &chip->bus->codec_list, list) {
                snd_hda_codec_configure(codec);
        }
        return 0;
}


/*
 * PCM support
 */

/* assign a stream for the PCM */
static inline struct azx_dev *
azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
{
        int dev, i, nums;
        struct azx_dev *res = NULL;

        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
                dev = chip->playback_index_offset;
                nums = chip->playback_streams;
        } else {
                dev = chip->capture_index_offset;
                nums = chip->capture_streams;
        }
        for (i = 0; i < nums; i++, dev++)
                if (!chip->azx_dev[dev].opened) {
                        res = &chip->azx_dev[dev];
                        if (res->device == substream->pcm->device)
                                break;
                }
        if (res) {
                res->opened = 1;
                res->device = substream->pcm->device;
        }
        return res;
}

/* release the assigned stream */
static inline void azx_release_device(struct azx_dev *azx_dev)
{
        azx_dev->opened = 0;
}

static struct snd_pcm_hardware azx_pcm_hw = {
        .info =                 (SNDRV_PCM_INFO_MMAP |
                                 SNDRV_PCM_INFO_INTERLEAVED |
                                 SNDRV_PCM_INFO_BLOCK_TRANSFER |
                                 SNDRV_PCM_INFO_MMAP_VALID |
                                 /* No full-resume yet implemented */
                                 /* SNDRV_PCM_INFO_RESUME |*/
                                 SNDRV_PCM_INFO_PAUSE |
                                 SNDRV_PCM_INFO_SYNC_START |
                                 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
        .formats =              SNDRV_PCM_FMTBIT_S16_LE,
        .rates =                SNDRV_PCM_RATE_48000,
        .rate_min =             48000,
        .rate_max =             48000,
        .channels_min =         2,
        .channels_max =         2,
        .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
        .period_bytes_min =     128,
        .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
        .periods_min =          2,
        .periods_max =          AZX_MAX_FRAG,
        .fifo_size =            0,
};

struct azx_pcm {
        struct azx *chip;
        struct hda_codec *codec;
        struct hda_pcm_stream *hinfo[2];
};

static int azx_pcm_open(struct snd_pcm_substream *substream)
{
        struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
        struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
        struct azx *chip = apcm->chip;
        struct azx_dev *azx_dev;
        struct snd_pcm_runtime *runtime = substream->runtime;
        unsigned long flags;
        int err;

        mutex_lock(&chip->open_mutex);
        azx_dev = azx_assign_device(chip, substream);
        if (azx_dev == NULL) {
                mutex_unlock(&chip->open_mutex);
                return -EBUSY;
        }
        runtime->hw = azx_pcm_hw;
        runtime->hw.channels_min = hinfo->channels_min;
        runtime->hw.channels_max = hinfo->channels_max;
        runtime->hw.formats = hinfo->formats;
        runtime->hw.rates = hinfo->rates;
        snd_pcm_limit_hw_rates(runtime);
        snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
        snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
                                   128);
        snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
                                   128);
        snd_hda_power_up(apcm->codec);
        err = hinfo->ops.open(hinfo, apcm->codec, substream);
        if (err < 0) {
                azx_release_device(azx_dev);
                snd_hda_power_down(apcm->codec);
                mutex_unlock(&chip->open_mutex);
                return err;
        }
        snd_pcm_limit_hw_rates(runtime);
        /* sanity check */
        if (snd_BUG_ON(!runtime->hw.channels_min) ||
            snd_BUG_ON(!runtime->hw.channels_max) ||
            snd_BUG_ON(!runtime->hw.formats) ||
            snd_BUG_ON(!runtime->hw.rates)) {
                azx_release_device(azx_dev);
                hinfo->ops.close(hinfo, apcm->codec, substream);
                snd_hda_power_down(apcm->codec);
                mutex_unlock(&chip->open_mutex);
                return -EINVAL;
        }
        spin_lock_irqsave(&chip->reg_lock, flags);
        azx_dev->substream = substream;
        azx_dev->running = 0;
        spin_unlock_irqrestore(&chip->reg_lock, flags);

        runtime->private_data = azx_dev;
        snd_pcm_set_sync(substream);
        mutex_unlock(&chip->open_mutex);
        return 0;
}

static int azx_pcm_close(struct snd_pcm_substream *substream)
{
        struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
        struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
        struct azx *chip = apcm->chip;
        struct azx_dev *azx_dev = get_azx_dev(substream);
        unsigned long flags;

        mutex_lock(&chip->open_mutex);
        spin_lock_irqsave(&chip->reg_lock, flags);
        azx_dev->substream = NULL;
        azx_dev->running = 0;
        spin_unlock_irqrestore(&chip->reg_lock, flags);
        azx_release_device(azx_dev);
        hinfo->ops.close(hinfo, apcm->codec, substream);
        snd_hda_power_down(apcm->codec);
        mutex_unlock(&chip->open_mutex);
        return 0;
}

static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
                             struct snd_pcm_hw_params *hw_params)
{
        struct azx_dev *azx_dev = get_azx_dev(substream);

        azx_dev->bufsize = 0;
        azx_dev->period_bytes = 0;
        azx_dev->format_val = 0;
        return snd_pcm_lib_malloc_pages(substream,
                                        params_buffer_bytes(hw_params));
}

static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
{
        struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
        struct azx_dev *azx_dev = get_azx_dev(substream);
        struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];

        /* reset BDL address */
        azx_sd_writel(azx_dev, SD_BDLPL, 0);
        azx_sd_writel(azx_dev, SD_BDLPU, 0);
        azx_sd_writel(azx_dev, SD_CTL, 0);
        azx_dev->bufsize = 0;
        azx_dev->period_bytes = 0;
        azx_dev->format_val = 0;

        snd_hda_codec_cleanup(apcm->codec, hinfo, substream);

        return snd_pcm_lib_free_pages(substream);
}

static int azx_pcm_prepare(struct snd_pcm_substream *substream)
{
        struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
        struct azx *chip = apcm->chip;
        struct azx_dev *azx_dev = get_azx_dev(substream);
        struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
        struct snd_pcm_runtime *runtime = substream->runtime;
        unsigned int bufsize, period_bytes, format_val, stream_tag;
        int err;

        azx_stream_reset(chip, azx_dev);
        format_val = snd_hda_calc_stream_format(runtime->rate,
                                                runtime->channels,
                                                runtime->format,
                                                hinfo->maxbps,
                                                apcm->codec->spdif_ctls);
        if (!format_val) {
                snd_printk(KERN_ERR SFX
                           "invalid format_val, rate=%d, ch=%d, format=%d\n",
                           runtime->rate, runtime->channels, runtime->format);
                return -EINVAL;
        }

        bufsize = snd_pcm_lib_buffer_bytes(substream);
        period_bytes = snd_pcm_lib_period_bytes(substream);

        snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
                    bufsize, format_val);

        if (bufsize != azx_dev->bufsize ||
            period_bytes != azx_dev->period_bytes ||
            format_val != azx_dev->format_val) {
                azx_dev->bufsize = bufsize;
                azx_dev->period_bytes = period_bytes;
                azx_dev->format_val = format_val;
                err = azx_setup_periods(chip, substream, azx_dev);
                if (err < 0)
                        return err;
        }

        /* wallclk has 24Mhz clock source */
        azx_dev->period_wallclk = (((runtime->period_size * 24000) /
                                                runtime->rate) * 1000);
        azx_setup_controller(chip, azx_dev);
        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
                azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
        else
                azx_dev->fifo_size = 0;

        stream_tag = azx_dev->stream_tag;
        /* CA-IBG chips need the playback stream starting from 1 */
        if (chip->driver_type == AZX_DRIVER_CTX &&
            stream_tag > chip->capture_streams)
                stream_tag -= chip->capture_streams;
        return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
                                     azx_dev->format_val, substream);
}

static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
        struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
        struct azx *chip = apcm->chip;
        struct azx_dev *azx_dev;
        struct snd_pcm_substream *s;
        int rstart = 0, start, nsync = 0, sbits = 0;
        int nwait, timeout;

        switch (cmd) {
        case SNDRV_PCM_TRIGGER_START:
                rstart = 1;
        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
        case SNDRV_PCM_TRIGGER_RESUME:
                start = 1;
                break;
        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
        case SNDRV_PCM_TRIGGER_SUSPEND:
        case SNDRV_PCM_TRIGGER_STOP:
                start = 0;
                break;
        default:
                return -EINVAL;
        }

        snd_pcm_group_for_each_entry(s, substream) {
                if (s->pcm->card != substream->pcm->card)
                        continue;
                azx_dev = get_azx_dev(s);
                sbits |= 1 << azx_dev->index;
                nsync++;
                snd_pcm_trigger_done(s, substream);
        }

        spin_lock(&chip->reg_lock);
        if (nsync > 1) {
                /* first, set SYNC bits of corresponding streams */
                azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
        }
        snd_pcm_group_for_each_entry(s, substream) {
                if (s->pcm->card != substream->pcm->card)
                        continue;
                azx_dev = get_azx_dev(s);
                if (start) {
                        azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
                        if (!rstart)
                                azx_dev->start_wallclk -=
                                                azx_dev->period_wallclk;
                        azx_stream_start(chip, azx_dev);
                } else {
                        azx_stream_stop(chip, azx_dev);
                }
                azx_dev->running = start;
        }
        spin_unlock(&chip->reg_lock);
        if (start) {
                if (nsync == 1)
                        return 0;
                /* wait until all FIFOs get ready */
                for (timeout = 5000; timeout; timeout--) {
                        nwait = 0;
                        snd_pcm_group_for_each_entry(s, substream) {
                                if (s->pcm->card != substream->pcm->card)
                                        continue;
                                azx_dev = get_azx_dev(s);
                                if (!(azx_sd_readb(azx_dev, SD_STS) &
                                      SD_STS_FIFO_READY))
                                        nwait++;
                        }
                        if (!nwait)
                                break;
                        cpu_relax();
                }
        } else {
                /* wait until all RUN bits are cleared */
                for (timeout = 5000; timeout; timeout--) {
                        nwait = 0;
                        snd_pcm_group_for_each_entry(s, substream) {
                                if (s->pcm->card != substream->pcm->card)
                                        continue;
                                azx_dev = get_azx_dev(s);
                                if (azx_sd_readb(azx_dev, SD_CTL) &
                                    SD_CTL_DMA_START)
                                        nwait++;
                        }
                        if (!nwait)
                                break;
                        cpu_relax();
                }
        }
        if (nsync > 1) {
                spin_lock(&chip->reg_lock);
                /* reset SYNC bits */
                azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
                spin_unlock(&chip->reg_lock);
        }
        return 0;
}

/* get the current DMA position with correction on VIA chips */
static unsigned int azx_via_get_position(struct azx *chip,
                                         struct azx_dev *azx_dev)
{
        unsigned int link_pos, mini_pos, bound_pos;
        unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
        unsigned int fifo_size;

        link_pos = azx_sd_readl(azx_dev, SD_LPIB);
        if (azx_dev->index >= 4) {
                /* Playback, no problem using link position */
                return link_pos;
        }

        /* Capture */
        /* For new chipset,
         * use mod to get the DMA position just like old chipset
         */
        mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
        mod_dma_pos %= azx_dev->period_bytes;

        /* azx_dev->fifo_size can't get FIFO size of in stream.
         * Get from base address + offset.
         */
        fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);

        if (azx_dev->insufficient) {
                /* Link position never gather than FIFO size */
                if (link_pos <= fifo_size)
                        return 0;

                azx_dev->insufficient = 0;
        }

        if (link_pos <= fifo_size)
                mini_pos = azx_dev->bufsize + link_pos - fifo_size;
        else
                mini_pos = link_pos - fifo_size;

        /* Find nearest previous boudary */
        mod_mini_pos = mini_pos % azx_dev->period_bytes;
        mod_link_pos = link_pos % azx_dev->period_bytes;
        if (mod_link_pos >= fifo_size)
                bound_pos = link_pos - mod_link_pos;
        else if (mod_dma_pos >= mod_mini_pos)
                bound_pos = mini_pos - mod_mini_pos;
        else {
                bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
                if (bound_pos >= azx_dev->bufsize)
                        bound_pos = 0;
        }

        /* Calculate real DMA position we want */
        return bound_pos + mod_dma_pos;
}

static unsigned int azx_get_position(struct azx *chip,
                                     struct azx_dev *azx_dev)
{
        unsigned int pos;
        int stream = azx_dev->substream->stream;

        switch (chip->position_fix[stream]) {
        case POS_FIX_LPIB:
                /* read LPIB */
                pos = azx_sd_readl(azx_dev, SD_LPIB);
                break;
        case POS_FIX_VIACOMBO:
                pos = azx_via_get_position(chip, azx_dev);
                break;
        default:
                /* use the position buffer */
                pos = le32_to_cpu(*azx_dev->posbuf);
        }

        if (pos >= azx_dev->bufsize)
                pos = 0;
        return pos;
}

static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
{
        struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
        struct azx *chip = apcm->chip;
        struct azx_dev *azx_dev = get_azx_dev(substream);
        return bytes_to_frames(substream->runtime,
                               azx_get_position(chip, azx_dev));
}

/*
 * Check whether the current DMA position is acceptable for updating
 * periods.  Returns non-zero if it's OK.
 *
 * Many HD-audio controllers appear pretty inaccurate about
 * the update-IRQ timing.  The IRQ is issued before actually the
 * data is processed.  So, we need to process it afterwords in a
 * workqueue.
 */
static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
{
        u32 wallclk;
        unsigned int pos;
        int stream;

        wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
        if (wallclk < (azx_dev->period_wallclk * 2) / 3)
                return -1;      /* bogus (too early) interrupt */

        stream = azx_dev->substream->stream;
        pos = azx_get_position(chip, azx_dev);
        if (chip->position_fix[stream] == POS_FIX_AUTO) {
                if (!pos) {
                        printk(KERN_WARNING
                               "hda-intel: Invalid position buffer, "
                               "using LPIB read method instead.\n");
                        chip->position_fix[stream] = POS_FIX_LPIB;
                        pos = azx_get_position(chip, azx_dev);
                } else
                        chip->position_fix[stream] = POS_FIX_POSBUF;
        }

        if (WARN_ONCE(!azx_dev->period_bytes,
                      "hda-intel: zero azx_dev->period_bytes"))
                return -1; /* this shouldn't happen! */
        if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
            pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
                /* NG - it's below the first next period boundary */
                return bdl_pos_adj[chip->dev_index] ? 0 : -1;
        azx_dev->start_wallclk += wallclk;
        return 1; /* OK, it's fine */
}

/*
 * The work for pending PCM period updates.
 */
static void azx_irq_pending_work(struct work_struct *work)
{
        struct azx *chip = container_of(work, struct azx, irq_pending_work);
        int i, pending, ok;

        if (!chip->irq_pending_warned) {
                printk(KERN_WARNING
                       "hda-intel: IRQ timing workaround is activated "
                       "for card #%d. Suggest a bigger bdl_pos_adj.\n",
                       chip->card->number);
                chip->irq_pending_warned = 1;
        }

        for (;;) {
                pending = 0;
                spin_lock_irq(&chip->reg_lock);
                for (i = 0; i < chip->num_streams; i++) {
                        struct azx_dev *azx_dev = &chip->azx_dev[i];
                        if (!azx_dev->irq_pending ||
                            !azx_dev->substream ||
                            !azx_dev->running)
                                continue;
                        ok = azx_position_ok(chip, azx_dev);
                        if (ok > 0) {
                                azx_dev->irq_pending = 0;
                                spin_unlock(&chip->reg_lock);
                                snd_pcm_period_elapsed(azx_dev->substream);
                                spin_lock(&chip->reg_lock);
                        } else if (ok < 0) {
                                pending = 0;    /* too early */
                        } else
                                pending++;
                }
                spin_unlock_irq(&chip->reg_lock);
                if (!pending)
                        return;
                msleep(1);
        }
}

/* clear irq_pending flags and assure no on-going workq */
static void azx_clear_irq_pending(struct azx *chip)
{
        int i;

        spin_lock_irq(&chip->reg_lock);
        for (i = 0; i < chip->num_streams; i++)
                chip->azx_dev[i].irq_pending = 0;
        spin_unlock_irq(&chip->reg_lock);
}

static struct snd_pcm_ops azx_pcm_ops = {
        .open = azx_pcm_open,
        .close = azx_pcm_close,
        .ioctl = snd_pcm_lib_ioctl,