linux/drivers/mfd/asic3.c
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   1/*
   2 * driver/mfd/asic3.c
   3 *
   4 * Compaq ASIC3 support.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 * Copyright 2001 Compaq Computer Corporation.
  11 * Copyright 2004-2005 Phil Blundell
  12 * Copyright 2007-2008 OpenedHand Ltd.
  13 *
  14 * Authors: Phil Blundell <pb@handhelds.org>,
  15 *          Samuel Ortiz <sameo@openedhand.com>
  16 *
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/delay.h>
  21#include <linux/irq.h>
  22#include <linux/gpio.h>
  23#include <linux/io.h>
  24#include <linux/slab.h>
  25#include <linux/spinlock.h>
  26#include <linux/platform_device.h>
  27
  28#include <linux/mfd/asic3.h>
  29#include <linux/mfd/core.h>
  30#include <linux/mfd/ds1wm.h>
  31#include <linux/mfd/tmio.h>
  32
  33enum {
  34        ASIC3_CLOCK_SPI,
  35        ASIC3_CLOCK_OWM,
  36        ASIC3_CLOCK_PWM0,
  37        ASIC3_CLOCK_PWM1,
  38        ASIC3_CLOCK_LED0,
  39        ASIC3_CLOCK_LED1,
  40        ASIC3_CLOCK_LED2,
  41        ASIC3_CLOCK_SD_HOST,
  42        ASIC3_CLOCK_SD_BUS,
  43        ASIC3_CLOCK_SMBUS,
  44        ASIC3_CLOCK_EX0,
  45        ASIC3_CLOCK_EX1,
  46};
  47
  48struct asic3_clk {
  49        int enabled;
  50        unsigned int cdex;
  51        unsigned long rate;
  52};
  53
  54#define INIT_CDEX(_name, _rate) \
  55        [ASIC3_CLOCK_##_name] = {               \
  56                .cdex = CLOCK_CDEX_##_name,     \
  57                .rate = _rate,                  \
  58        }
  59
  60static struct asic3_clk asic3_clk_init[] __initdata = {
  61        INIT_CDEX(SPI, 0),
  62        INIT_CDEX(OWM, 5000000),
  63        INIT_CDEX(PWM0, 0),
  64        INIT_CDEX(PWM1, 0),
  65        INIT_CDEX(LED0, 0),
  66        INIT_CDEX(LED1, 0),
  67        INIT_CDEX(LED2, 0),
  68        INIT_CDEX(SD_HOST, 24576000),
  69        INIT_CDEX(SD_BUS, 12288000),
  70        INIT_CDEX(SMBUS, 0),
  71        INIT_CDEX(EX0, 32768),
  72        INIT_CDEX(EX1, 24576000),
  73};
  74
  75struct asic3 {
  76        void __iomem *mapping;
  77        unsigned int bus_shift;
  78        unsigned int irq_nr;
  79        unsigned int irq_base;
  80        spinlock_t lock;
  81        u16 irq_bothedge[4];
  82        struct gpio_chip gpio;
  83        struct device *dev;
  84        void __iomem *tmio_cnf;
  85
  86        struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
  87};
  88
  89static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
  90
  91static inline void asic3_write_register(struct asic3 *asic,
  92                                 unsigned int reg, u32 value)
  93{
  94        iowrite16(value, asic->mapping +
  95                  (reg >> asic->bus_shift));
  96}
  97
  98static inline u32 asic3_read_register(struct asic3 *asic,
  99                               unsigned int reg)
 100{
 101        return ioread16(asic->mapping +
 102                        (reg >> asic->bus_shift));
 103}
 104
 105static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
 106{
 107        unsigned long flags;
 108        u32 val;
 109
 110        spin_lock_irqsave(&asic->lock, flags);
 111        val = asic3_read_register(asic, reg);
 112        if (set)
 113                val |= bits;
 114        else
 115                val &= ~bits;
 116        asic3_write_register(asic, reg, val);
 117        spin_unlock_irqrestore(&asic->lock, flags);
 118}
 119
 120/* IRQs */
 121#define MAX_ASIC_ISR_LOOPS    20
 122#define ASIC3_GPIO_BASE_INCR \
 123        (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
 124
 125static void asic3_irq_flip_edge(struct asic3 *asic,
 126                                u32 base, int bit)
 127{
 128        u16 edge;
 129        unsigned long flags;
 130
 131        spin_lock_irqsave(&asic->lock, flags);
 132        edge = asic3_read_register(asic,
 133                                   base + ASIC3_GPIO_EDGE_TRIGGER);
 134        edge ^= bit;
 135        asic3_write_register(asic,
 136                             base + ASIC3_GPIO_EDGE_TRIGGER, edge);
 137        spin_unlock_irqrestore(&asic->lock, flags);
 138}
 139
 140static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
 141{
 142        struct asic3 *asic = irq_desc_get_handler_data(desc);
 143        struct irq_data *data = irq_desc_get_irq_data(desc);
 144        int iter, i;
 145        unsigned long flags;
 146
 147        data->chip->irq_ack(data);
 148
 149        for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
 150                u32 status;
 151                int bank;
 152
 153                spin_lock_irqsave(&asic->lock, flags);
 154                status = asic3_read_register(asic,
 155                                             ASIC3_OFFSET(INTR, P_INT_STAT));
 156                spin_unlock_irqrestore(&asic->lock, flags);
 157
 158                /* Check all ten register bits */
 159                if ((status & 0x3ff) == 0)
 160                        break;
 161
 162                /* Handle GPIO IRQs */
 163                for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
 164                        if (status & (1 << bank)) {
 165                                unsigned long base, istat;
 166
 167                                base = ASIC3_GPIO_A_BASE
 168                                       + bank * ASIC3_GPIO_BASE_INCR;
 169
 170                                spin_lock_irqsave(&asic->lock, flags);
 171                                istat = asic3_read_register(asic,
 172                                                            base +
 173                                                            ASIC3_GPIO_INT_STATUS);
 174                                /* Clearing IntStatus */
 175                                asic3_write_register(asic,
 176                                                     base +
 177                                                     ASIC3_GPIO_INT_STATUS, 0);
 178                                spin_unlock_irqrestore(&asic->lock, flags);
 179
 180                                for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
 181                                        int bit = (1 << i);
 182                                        unsigned int irqnr;
 183
 184                                        if (!(istat & bit))
 185                                                continue;
 186
 187                                        irqnr = asic->irq_base +
 188                                                (ASIC3_GPIOS_PER_BANK * bank)
 189                                                + i;
 190                                        generic_handle_irq(irqnr);
 191                                        if (asic->irq_bothedge[bank] & bit)
 192                                                asic3_irq_flip_edge(asic, base,
 193                                                                    bit);
 194                                }
 195                        }
 196                }
 197
 198                /* Handle remaining IRQs in the status register */
 199                for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
 200                        /* They start at bit 4 and go up */
 201                        if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
 202                                generic_handle_irq(asic->irq_base + i);
 203                }
 204        }
 205
 206        if (iter >= MAX_ASIC_ISR_LOOPS)
 207                dev_err(asic->dev, "interrupt processing overrun\n");
 208}
 209
 210static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
 211{
 212        int n;
 213
 214        n = (irq - asic->irq_base) >> 4;
 215
 216        return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
 217}
 218
 219static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
 220{
 221        return (irq - asic->irq_base) & 0xf;
 222}
 223
 224static void asic3_mask_gpio_irq(struct irq_data *data)
 225{
 226        struct asic3 *asic = irq_data_get_irq_chip_data(data);
 227        u32 val, bank, index;
 228        unsigned long flags;
 229
 230        bank = asic3_irq_to_bank(asic, data->irq);
 231        index = asic3_irq_to_index(asic, data->irq);
 232
 233        spin_lock_irqsave(&asic->lock, flags);
 234        val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
 235        val |= 1 << index;
 236        asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
 237        spin_unlock_irqrestore(&asic->lock, flags);
 238}
 239
 240static void asic3_mask_irq(struct irq_data *data)
 241{
 242        struct asic3 *asic = irq_data_get_irq_chip_data(data);
 243        int regval;
 244        unsigned long flags;
 245
 246        spin_lock_irqsave(&asic->lock, flags);
 247        regval = asic3_read_register(asic,
 248                                     ASIC3_INTR_BASE +
 249                                     ASIC3_INTR_INT_MASK);
 250
 251        regval &= ~(ASIC3_INTMASK_MASK0 <<
 252                    (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
 253
 254        asic3_write_register(asic,
 255                             ASIC3_INTR_BASE +
 256                             ASIC3_INTR_INT_MASK,
 257                             regval);
 258        spin_unlock_irqrestore(&asic->lock, flags);
 259}
 260
 261static void asic3_unmask_gpio_irq(struct irq_data *data)
 262{
 263        struct asic3 *asic = irq_data_get_irq_chip_data(data);
 264        u32 val, bank, index;
 265        unsigned long flags;
 266
 267        bank = asic3_irq_to_bank(asic, data->irq);
 268        index = asic3_irq_to_index(asic, data->irq);
 269
 270        spin_lock_irqsave(&asic->lock, flags);
 271        val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
 272        val &= ~(1 << index);
 273        asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
 274        spin_unlock_irqrestore(&asic->lock, flags);
 275}
 276
 277static void asic3_unmask_irq(struct irq_data *data)
 278{
 279        struct asic3 *asic = irq_data_get_irq_chip_data(data);
 280        int regval;
 281        unsigned long flags;
 282
 283        spin_lock_irqsave(&asic->lock, flags);
 284        regval = asic3_read_register(asic,
 285                                     ASIC3_INTR_BASE +
 286                                     ASIC3_INTR_INT_MASK);
 287
 288        regval |= (ASIC3_INTMASK_MASK0 <<
 289                   (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
 290
 291        asic3_write_register(asic,
 292                             ASIC3_INTR_BASE +
 293                             ASIC3_INTR_INT_MASK,
 294                             regval);
 295        spin_unlock_irqrestore(&asic->lock, flags);
 296}
 297
 298static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
 299{
 300        struct asic3 *asic = irq_data_get_irq_chip_data(data);
 301        u32 bank, index;
 302        u16 trigger, level, edge, bit;
 303        unsigned long flags;
 304
 305        bank = asic3_irq_to_bank(asic, data->irq);
 306        index = asic3_irq_to_index(asic, data->irq);
 307        bit = 1<<index;
 308
 309        spin_lock_irqsave(&asic->lock, flags);
 310        level = asic3_read_register(asic,
 311                                    bank + ASIC3_GPIO_LEVEL_TRIGGER);
 312        edge = asic3_read_register(asic,
 313                                   bank + ASIC3_GPIO_EDGE_TRIGGER);
 314        trigger = asic3_read_register(asic,
 315                                      bank + ASIC3_GPIO_TRIGGER_TYPE);
 316        asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
 317
 318        if (type == IRQ_TYPE_EDGE_RISING) {
 319                trigger |= bit;
 320                edge |= bit;
 321        } else if (type == IRQ_TYPE_EDGE_FALLING) {
 322                trigger |= bit;
 323                edge &= ~bit;
 324        } else if (type == IRQ_TYPE_EDGE_BOTH) {
 325                trigger |= bit;
 326                if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
 327                        edge &= ~bit;
 328                else
 329                        edge |= bit;
 330                asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
 331        } else if (type == IRQ_TYPE_LEVEL_LOW) {
 332                trigger &= ~bit;
 333                level &= ~bit;
 334        } else if (type == IRQ_TYPE_LEVEL_HIGH) {
 335                trigger &= ~bit;
 336                level |= bit;
 337        } else {
 338                /*
 339                 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
 340                 * be careful to not unmask them if mask was also called.
 341                 * Probably need internal state for mask.
 342                 */
 343                dev_notice(asic->dev, "irq type not changed\n");
 344        }
 345        asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
 346                             level);
 347        asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
 348                             edge);
 349        asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
 350                             trigger);
 351        spin_unlock_irqrestore(&asic->lock, flags);
 352        return 0;
 353}
 354
 355static struct irq_chip asic3_gpio_irq_chip = {
 356        .name           = "ASIC3-GPIO",
 357        .irq_ack        = asic3_mask_gpio_irq,
 358        .irq_mask       = asic3_mask_gpio_irq,
 359        .irq_unmask     = asic3_unmask_gpio_irq,
 360        .irq_set_type   = asic3_gpio_irq_type,
 361};
 362
 363static struct irq_chip asic3_irq_chip = {
 364        .name           = "ASIC3",
 365        .irq_ack        = asic3_mask_irq,
 366        .irq_mask       = asic3_mask_irq,
 367        .irq_unmask     = asic3_unmask_irq,
 368};
 369
 370static int __init asic3_irq_probe(struct platform_device *pdev)
 371{
 372        struct asic3 *asic = platform_get_drvdata(pdev);
 373        unsigned long clksel = 0;
 374        unsigned int irq, irq_base;
 375        int ret;
 376
 377        ret = platform_get_irq(pdev, 0);
 378        if (ret < 0)
 379                return ret;
 380        asic->irq_nr = ret;
 381
 382        /* turn on clock to IRQ controller */
 383        clksel |= CLOCK_SEL_CX;
 384        asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
 385                             clksel);
 386
 387        irq_base = asic->irq_base;
 388
 389        for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
 390                if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
 391                        irq_set_chip(irq, &asic3_gpio_irq_chip);
 392                else
 393                        irq_set_chip(irq, &asic3_irq_chip);
 394
 395                irq_set_chip_data(irq, asic);
 396                irq_set_handler(irq, handle_level_irq);
 397                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 398        }
 399
 400        asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
 401                             ASIC3_INTMASK_GINTMASK);
 402
 403        irq_set_chained_handler(asic->irq_nr, asic3_irq_demux);
 404        irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
 405        irq_set_handler_data(asic->irq_nr, asic);
 406
 407        return 0;
 408}
 409
 410static void asic3_irq_remove(struct platform_device *pdev)
 411{
 412        struct asic3 *asic = platform_get_drvdata(pdev);
 413        unsigned int irq, irq_base;
 414
 415        irq_base = asic->irq_base;
 416
 417        for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
 418                set_irq_flags(irq, 0);
 419                irq_set_chip_and_handler(irq, NULL, NULL);
 420                irq_set_chip_data(irq, NULL);
 421        }
 422        irq_set_chained_handler(asic->irq_nr, NULL);
 423}
 424
 425/* GPIOs */
 426static int asic3_gpio_direction(struct gpio_chip *chip,
 427                                unsigned offset, int out)
 428{
 429        u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
 430        unsigned int gpio_base;
 431        unsigned long flags;
 432        struct asic3 *asic;
 433
 434        asic = container_of(chip, struct asic3, gpio);
 435        gpio_base = ASIC3_GPIO_TO_BASE(offset);
 436
 437        if (gpio_base > ASIC3_GPIO_D_BASE) {
 438                dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 439                        gpio_base, offset);
 440                return -EINVAL;
 441        }
 442
 443        spin_lock_irqsave(&asic->lock, flags);
 444
 445        out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
 446
 447        /* Input is 0, Output is 1 */
 448        if (out)
 449                out_reg |= mask;
 450        else
 451                out_reg &= ~mask;
 452
 453        asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
 454
 455        spin_unlock_irqrestore(&asic->lock, flags);
 456
 457        return 0;
 458
 459}
 460
 461static int asic3_gpio_direction_input(struct gpio_chip *chip,
 462                                      unsigned offset)
 463{
 464        return asic3_gpio_direction(chip, offset, 0);
 465}
 466
 467static int asic3_gpio_direction_output(struct gpio_chip *chip,
 468                                       unsigned offset, int value)
 469{
 470        return asic3_gpio_direction(chip, offset, 1);
 471}
 472
 473static int asic3_gpio_get(struct gpio_chip *chip,
 474                          unsigned offset)
 475{
 476        unsigned int gpio_base;
 477        u32 mask = ASIC3_GPIO_TO_MASK(offset);
 478        struct asic3 *asic;
 479
 480        asic = container_of(chip, struct asic3, gpio);
 481        gpio_base = ASIC3_GPIO_TO_BASE(offset);
 482
 483        if (gpio_base > ASIC3_GPIO_D_BASE) {
 484                dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 485                        gpio_base, offset);
 486                return -EINVAL;
 487        }
 488
 489        return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
 490}
 491
 492static void asic3_gpio_set(struct gpio_chip *chip,
 493                           unsigned offset, int value)
 494{
 495        u32 mask, out_reg;
 496        unsigned int gpio_base;
 497        unsigned long flags;
 498        struct asic3 *asic;
 499
 500        asic = container_of(chip, struct asic3, gpio);
 501        gpio_base = ASIC3_GPIO_TO_BASE(offset);
 502
 503        if (gpio_base > ASIC3_GPIO_D_BASE) {
 504                dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 505                        gpio_base, offset);
 506                return;
 507        }
 508
 509        mask = ASIC3_GPIO_TO_MASK(offset);
 510
 511        spin_lock_irqsave(&asic->lock, flags);
 512
 513        out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
 514
 515        if (value)
 516                out_reg |= mask;
 517        else
 518                out_reg &= ~mask;
 519
 520        asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
 521
 522        spin_unlock_irqrestore(&asic->lock, flags);
 523
 524        return;
 525}
 526
 527static __init int asic3_gpio_probe(struct platform_device *pdev,
 528                                   u16 *gpio_config, int num)
 529{
 530        struct asic3 *asic = platform_get_drvdata(pdev);
 531        u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
 532        u16 out_reg[ASIC3_NUM_GPIO_BANKS];
 533        u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
 534        int i;
 535
 536        memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 537        memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 538        memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 539
 540        /* Enable all GPIOs */
 541        asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
 542        asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
 543        asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
 544        asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
 545
 546        for (i = 0; i < num; i++) {
 547                u8 alt, pin, dir, init, bank_num, bit_num;
 548                u16 config = gpio_config[i];
 549
 550                pin = ASIC3_CONFIG_GPIO_PIN(config);
 551                alt = ASIC3_CONFIG_GPIO_ALT(config);
 552                dir = ASIC3_CONFIG_GPIO_DIR(config);
 553                init = ASIC3_CONFIG_GPIO_INIT(config);
 554
 555                bank_num = ASIC3_GPIO_TO_BANK(pin);
 556                bit_num = ASIC3_GPIO_TO_BIT(pin);
 557
 558                alt_reg[bank_num] |= (alt << bit_num);
 559                out_reg[bank_num] |= (init << bit_num);
 560                dir_reg[bank_num] |= (dir << bit_num);
 561        }
 562
 563        for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
 564                asic3_write_register(asic,
 565                                     ASIC3_BANK_TO_BASE(i) +
 566                                     ASIC3_GPIO_DIRECTION,
 567                                     dir_reg[i]);
 568                asic3_write_register(asic,
 569                                     ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
 570                                     out_reg[i]);
 571                asic3_write_register(asic,
 572                                     ASIC3_BANK_TO_BASE(i) +
 573                                     ASIC3_GPIO_ALT_FUNCTION,
 574                                     alt_reg[i]);
 575        }
 576
 577        return gpiochip_add(&asic->gpio);
 578}
 579
 580static int asic3_gpio_remove(struct platform_device *pdev)
 581{
 582        struct asic3 *asic = platform_get_drvdata(pdev);
 583
 584        return gpiochip_remove(&asic->gpio);
 585}
 586
 587static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
 588{
 589        unsigned long flags;
 590        u32 cdex;
 591
 592        spin_lock_irqsave(&asic->lock, flags);
 593        if (clk->enabled++ == 0) {
 594                cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
 595                cdex |= clk->cdex;
 596                asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
 597        }
 598        spin_unlock_irqrestore(&asic->lock, flags);
 599
 600        return 0;
 601}
 602
 603static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
 604{
 605        unsigned long flags;
 606        u32 cdex;
 607
 608        WARN_ON(clk->enabled == 0);
 609
 610        spin_lock_irqsave(&asic->lock, flags);
 611        if (--clk->enabled == 0) {
 612                cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
 613                cdex &= ~clk->cdex;
 614                asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
 615        }
 616        spin_unlock_irqrestore(&asic->lock, flags);
 617}
 618
 619/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
 620static struct ds1wm_driver_data ds1wm_pdata = {
 621        .active_high = 1,
 622};
 623
 624static struct resource ds1wm_resources[] = {
 625        {
 626                .start = ASIC3_OWM_BASE,
 627                .end   = ASIC3_OWM_BASE + 0x13,
 628                .flags = IORESOURCE_MEM,
 629        },
 630        {
 631                .start = ASIC3_IRQ_OWM,
 632                .end   = ASIC3_IRQ_OWM,
 633                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 634        },
 635};
 636
 637static int ds1wm_enable(struct platform_device *pdev)
 638{
 639        struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 640
 641        /* Turn on external clocks and the OWM clock */
 642        asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 643        asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 644        asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
 645        msleep(1);
 646
 647        /* Reset and enable DS1WM */
 648        asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
 649                           ASIC3_EXTCF_OWM_RESET, 1);
 650        msleep(1);
 651        asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
 652                           ASIC3_EXTCF_OWM_RESET, 0);
 653        msleep(1);
 654        asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 655                           ASIC3_EXTCF_OWM_EN, 1);
 656        msleep(1);
 657
 658        return 0;
 659}
 660
 661static int ds1wm_disable(struct platform_device *pdev)
 662{
 663        struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 664
 665        asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 666                           ASIC3_EXTCF_OWM_EN, 0);
 667
 668        asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
 669        asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 670        asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 671
 672        return 0;
 673}
 674
 675static struct mfd_cell asic3_cell_ds1wm = {
 676        .name          = "ds1wm",
 677        .enable        = ds1wm_enable,
 678        .disable       = ds1wm_disable,
 679        .mfd_data      = &ds1wm_pdata,
 680        .num_resources = ARRAY_SIZE(ds1wm_resources),
 681        .resources     = ds1wm_resources,
 682};
 683
 684static void asic3_mmc_pwr(struct platform_device *pdev, int state)
 685{
 686        struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 687
 688        tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
 689}
 690
 691static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
 692{
 693        struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 694
 695        tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
 696}
 697
 698static struct tmio_mmc_data asic3_mmc_data = {
 699        .hclk           = 24576000,
 700        .set_pwr        = asic3_mmc_pwr,
 701        .set_clk_div    = asic3_mmc_clk_div,
 702};
 703
 704static struct resource asic3_mmc_resources[] = {
 705        {
 706                .start = ASIC3_SD_CTRL_BASE,
 707                .end   = ASIC3_SD_CTRL_BASE + 0x3ff,
 708                .flags = IORESOURCE_MEM,
 709        },
 710        {
 711                .start = 0,
 712                .end   = 0,
 713                .flags = IORESOURCE_IRQ,
 714        },
 715};
 716
 717static int asic3_mmc_enable(struct platform_device *pdev)
 718{
 719        struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 720
 721        /* Not sure if it must be done bit by bit, but leaving as-is */
 722        asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 723                           ASIC3_SDHWCTRL_LEVCD, 1);
 724        asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 725                           ASIC3_SDHWCTRL_LEVWP, 1);
 726        asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 727                           ASIC3_SDHWCTRL_SUSPEND, 0);
 728        asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 729                           ASIC3_SDHWCTRL_PCLR, 0);
 730
 731        asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 732        /* CLK32 used for card detection and for interruption detection
 733         * when HCLK is stopped.
 734         */
 735        asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 736        msleep(1);
 737
 738        /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
 739        asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
 740                CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
 741
 742        asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
 743        asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
 744        msleep(1);
 745
 746        asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 747                           ASIC3_EXTCF_SD_MEM_ENABLE, 1);
 748
 749        /* Enable SD card slot 3.3V power supply */
 750        asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 751                           ASIC3_SDHWCTRL_SDPWR, 1);
 752
 753        /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
 754        tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
 755                             ASIC3_SD_CTRL_BASE >> 1);
 756
 757        return 0;
 758}
 759
 760static int asic3_mmc_disable(struct platform_device *pdev)
 761{
 762        struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 763
 764        /* Put in suspend mode */
 765        asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 766                           ASIC3_SDHWCTRL_SUSPEND, 1);
 767
 768        /* Disable clocks */
 769        asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
 770        asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
 771        asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 772        asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 773        return 0;
 774}
 775
 776static struct mfd_cell asic3_cell_mmc = {
 777        .name          = "tmio-mmc",
 778        .enable        = asic3_mmc_enable,
 779        .disable       = asic3_mmc_disable,
 780        .mfd_data      = &asic3_mmc_data,
 781        .num_resources = ARRAY_SIZE(asic3_mmc_resources),
 782        .resources     = asic3_mmc_resources,
 783};
 784
 785static int __init asic3_mfd_probe(struct platform_device *pdev,
 786                                  struct resource *mem)
 787{
 788        struct asic3 *asic = platform_get_drvdata(pdev);
 789        struct resource *mem_sdio;
 790        int irq, ret;
 791
 792        mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 793        if (!mem_sdio)
 794                dev_dbg(asic->dev, "no SDIO MEM resource\n");
 795
 796        irq = platform_get_irq(pdev, 1);
 797        if (irq < 0)
 798                dev_dbg(asic->dev, "no SDIO IRQ resource\n");
 799
 800        /* DS1WM */
 801        asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 802                           ASIC3_EXTCF_OWM_SMB, 0);
 803
 804        ds1wm_resources[0].start >>= asic->bus_shift;
 805        ds1wm_resources[0].end   >>= asic->bus_shift;
 806
 807        /* MMC */
 808        asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
 809                                 mem_sdio->start, 0x400 >> asic->bus_shift);
 810        if (!asic->tmio_cnf) {
 811                ret = -ENOMEM;
 812                dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
 813                goto out;
 814        }
 815        asic3_mmc_resources[0].start >>= asic->bus_shift;
 816        asic3_mmc_resources[0].end   >>= asic->bus_shift;
 817
 818        ret = mfd_add_devices(&pdev->dev, pdev->id,
 819                        &asic3_cell_ds1wm, 1, mem, asic->irq_base);
 820        if (ret < 0)
 821                goto out;
 822
 823        if (mem_sdio && (irq >= 0))
 824                ret = mfd_add_devices(&pdev->dev, pdev->id,
 825                        &asic3_cell_mmc, 1, mem_sdio, irq);
 826
 827 out:
 828        return ret;
 829}
 830
 831static void asic3_mfd_remove(struct platform_device *pdev)
 832{
 833        struct asic3 *asic = platform_get_drvdata(pdev);
 834
 835        mfd_remove_devices(&pdev->dev);
 836        iounmap(asic->tmio_cnf);
 837}
 838
 839/* Core */
 840static int __init asic3_probe(struct platform_device *pdev)
 841{
 842        struct asic3_platform_data *pdata = pdev->dev.platform_data;
 843        struct asic3 *asic;
 844        struct resource *mem;
 845        unsigned long clksel;
 846        int ret = 0;
 847
 848        asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
 849        if (asic == NULL) {
 850                printk(KERN_ERR "kzalloc failed\n");
 851                return -ENOMEM;
 852        }
 853
 854        spin_lock_init(&asic->lock);
 855        platform_set_drvdata(pdev, asic);
 856        asic->dev = &pdev->dev;
 857
 858        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 859        if (!mem) {
 860                ret = -ENOMEM;
 861                dev_err(asic->dev, "no MEM resource\n");
 862                goto out_free;
 863        }
 864
 865        asic->mapping = ioremap(mem->start, resource_size(mem));
 866        if (!asic->mapping) {
 867                ret = -ENOMEM;
 868                dev_err(asic->dev, "Couldn't ioremap\n");
 869                goto out_free;
 870        }
 871
 872        asic->irq_base = pdata->irq_base;
 873
 874        /* calculate bus shift from mem resource */
 875        asic->bus_shift = 2 - (resource_size(mem) >> 12);
 876
 877        clksel = 0;
 878        asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
 879
 880        ret = asic3_irq_probe(pdev);
 881        if (ret < 0) {
 882                dev_err(asic->dev, "Couldn't probe IRQs\n");
 883                goto out_unmap;
 884        }
 885
 886        asic->gpio.base = pdata->gpio_base;
 887        asic->gpio.ngpio = ASIC3_NUM_GPIOS;
 888        asic->gpio.get = asic3_gpio_get;
 889        asic->gpio.set = asic3_gpio_set;
 890        asic->gpio.direction_input = asic3_gpio_direction_input;
 891        asic->gpio.direction_output = asic3_gpio_direction_output;
 892
 893        ret = asic3_gpio_probe(pdev,
 894                               pdata->gpio_config,
 895                               pdata->gpio_config_num);
 896        if (ret < 0) {
 897                dev_err(asic->dev, "GPIO probe failed\n");
 898                goto out_irq;
 899        }
 900
 901        /* Making a per-device copy is only needed for the
 902         * theoretical case of multiple ASIC3s on one board:
 903         */
 904        memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
 905
 906        asic3_mfd_probe(pdev, mem);
 907
 908        dev_info(asic->dev, "ASIC3 Core driver\n");
 909
 910        return 0;
 911
 912 out_irq:
 913        asic3_irq_remove(pdev);
 914
 915 out_unmap:
 916        iounmap(asic->mapping);
 917
 918 out_free:
 919        kfree(asic);
 920
 921        return ret;
 922}
 923
 924static int __devexit asic3_remove(struct platform_device *pdev)
 925{
 926        int ret;
 927        struct asic3 *asic = platform_get_drvdata(pdev);
 928
 929        asic3_mfd_remove(pdev);
 930
 931        ret = asic3_gpio_remove(pdev);
 932        if (ret < 0)
 933                return ret;
 934        asic3_irq_remove(pdev);
 935
 936        asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
 937
 938        iounmap(asic->mapping);
 939
 940        kfree(asic);
 941
 942        return 0;
 943}
 944
 945static void asic3_shutdown(struct platform_device *pdev)
 946{
 947}
 948
 949static struct platform_driver asic3_device_driver = {
 950        .driver         = {
 951                .name   = "asic3",
 952        },
 953        .remove         = __devexit_p(asic3_remove),
 954        .shutdown       = asic3_shutdown,
 955};
 956
 957static int __init asic3_init(void)
 958{
 959        int retval = 0;
 960        retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
 961        return retval;
 962}
 963
 964subsys_initcall(asic3_init);
 965