linux/drivers/edac/mpc85xx_edac.c
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   1/*
   2 * Freescale MPC85xx Memory Controller kenel module
   3 *
   4 * Author: Dave Jiang <djiang@mvista.com>
   5 *
   6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
   7 * the terms of the GNU General Public License version 2. This program
   8 * is licensed "as is" without any warranty of any kind, whether express
   9 * or implied.
  10 *
  11 */
  12#include <linux/module.h>
  13#include <linux/init.h>
  14#include <linux/interrupt.h>
  15#include <linux/ctype.h>
  16#include <linux/io.h>
  17#include <linux/mod_devicetable.h>
  18#include <linux/edac.h>
  19#include <linux/smp.h>
  20#include <linux/gfp.h>
  21
  22#include <linux/of_platform.h>
  23#include <linux/of_device.h>
  24#include "edac_module.h"
  25#include "edac_core.h"
  26#include "mpc85xx_edac.h"
  27
  28static int edac_dev_idx;
  29#ifdef CONFIG_PCI
  30static int edac_pci_idx;
  31#endif
  32static int edac_mc_idx;
  33
  34static u32 orig_ddr_err_disable;
  35static u32 orig_ddr_err_sbe;
  36
  37/*
  38 * PCI Err defines
  39 */
  40#ifdef CONFIG_PCI
  41static u32 orig_pci_err_cap_dr;
  42static u32 orig_pci_err_en;
  43#endif
  44
  45static u32 orig_l2_err_disable;
  46#ifdef CONFIG_FSL_SOC_BOOKE
  47static u32 orig_hid1[2];
  48#endif
  49
  50/************************ MC SYSFS parts ***********************************/
  51
  52static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci,
  53                                              char *data)
  54{
  55        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  56        return sprintf(data, "0x%08x",
  57                       in_be32(pdata->mc_vbase +
  58                               MPC85XX_MC_DATA_ERR_INJECT_HI));
  59}
  60
  61static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci,
  62                                              char *data)
  63{
  64        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  65        return sprintf(data, "0x%08x",
  66                       in_be32(pdata->mc_vbase +
  67                               MPC85XX_MC_DATA_ERR_INJECT_LO));
  68}
  69
  70static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data)
  71{
  72        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  73        return sprintf(data, "0x%08x",
  74                       in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
  75}
  76
  77static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci,
  78                                               const char *data, size_t count)
  79{
  80        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  81        if (isdigit(*data)) {
  82                out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
  83                         simple_strtoul(data, NULL, 0));
  84                return count;
  85        }
  86        return 0;
  87}
  88
  89static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci,
  90                                               const char *data, size_t count)
  91{
  92        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  93        if (isdigit(*data)) {
  94                out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
  95                         simple_strtoul(data, NULL, 0));
  96                return count;
  97        }
  98        return 0;
  99}
 100
 101static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci,
 102                                            const char *data, size_t count)
 103{
 104        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 105        if (isdigit(*data)) {
 106                out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
 107                         simple_strtoul(data, NULL, 0));
 108                return count;
 109        }
 110        return 0;
 111}
 112
 113static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = {
 114        {
 115         .attr = {
 116                  .name = "inject_data_hi",
 117                  .mode = (S_IRUGO | S_IWUSR)
 118                  },
 119         .show = mpc85xx_mc_inject_data_hi_show,
 120         .store = mpc85xx_mc_inject_data_hi_store},
 121        {
 122         .attr = {
 123                  .name = "inject_data_lo",
 124                  .mode = (S_IRUGO | S_IWUSR)
 125                  },
 126         .show = mpc85xx_mc_inject_data_lo_show,
 127         .store = mpc85xx_mc_inject_data_lo_store},
 128        {
 129         .attr = {
 130                  .name = "inject_ctrl",
 131                  .mode = (S_IRUGO | S_IWUSR)
 132                  },
 133         .show = mpc85xx_mc_inject_ctrl_show,
 134         .store = mpc85xx_mc_inject_ctrl_store},
 135
 136        /* End of list */
 137        {
 138         .attr = {.name = NULL}
 139         }
 140};
 141
 142static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
 143{
 144        mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes;
 145}
 146
 147/**************************** PCI Err device ***************************/
 148#ifdef CONFIG_PCI
 149
 150static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
 151{
 152        struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 153        u32 err_detect;
 154
 155        err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
 156
 157        /* master aborts can happen during PCI config cycles */
 158        if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
 159                out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
 160                return;
 161        }
 162
 163        printk(KERN_ERR "PCI error(s) detected\n");
 164        printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
 165
 166        printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
 167               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
 168        printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
 169               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
 170        printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
 171               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
 172        printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
 173               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
 174        printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
 175               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
 176
 177        /* clear error bits */
 178        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
 179
 180        if (err_detect & PCI_EDE_PERR_MASK)
 181                edac_pci_handle_pe(pci, pci->ctl_name);
 182
 183        if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
 184                edac_pci_handle_npe(pci, pci->ctl_name);
 185}
 186
 187static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
 188{
 189        struct edac_pci_ctl_info *pci = dev_id;
 190        struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 191        u32 err_detect;
 192
 193        err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
 194
 195        if (!err_detect)
 196                return IRQ_NONE;
 197
 198        mpc85xx_pci_check(pci);
 199
 200        return IRQ_HANDLED;
 201}
 202
 203static int __devinit mpc85xx_pci_err_probe(struct platform_device *op,
 204                                           const struct of_device_id *match)
 205{
 206        struct edac_pci_ctl_info *pci;
 207        struct mpc85xx_pci_pdata *pdata;
 208        struct resource r;
 209        int res = 0;
 210
 211        if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
 212                return -ENOMEM;
 213
 214        pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
 215        if (!pci)
 216                return -ENOMEM;
 217
 218        pdata = pci->pvt_info;
 219        pdata->name = "mpc85xx_pci_err";
 220        pdata->irq = NO_IRQ;
 221        dev_set_drvdata(&op->dev, pci);
 222        pci->dev = &op->dev;
 223        pci->mod_name = EDAC_MOD_STR;
 224        pci->ctl_name = pdata->name;
 225        pci->dev_name = dev_name(&op->dev);
 226
 227        if (edac_op_state == EDAC_OPSTATE_POLL)
 228                pci->edac_check = mpc85xx_pci_check;
 229
 230        pdata->edac_idx = edac_pci_idx++;
 231
 232        res = of_address_to_resource(op->dev.of_node, 0, &r);
 233        if (res) {
 234                printk(KERN_ERR "%s: Unable to get resource for "
 235                       "PCI err regs\n", __func__);
 236                goto err;
 237        }
 238
 239        /* we only need the error registers */
 240        r.start += 0xe00;
 241
 242        if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
 243                                        pdata->name)) {
 244                printk(KERN_ERR "%s: Error while requesting mem region\n",
 245                       __func__);
 246                res = -EBUSY;
 247                goto err;
 248        }
 249
 250        pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
 251        if (!pdata->pci_vbase) {
 252                printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
 253                res = -ENOMEM;
 254                goto err;
 255        }
 256
 257        orig_pci_err_cap_dr =
 258            in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
 259
 260        /* PCI master abort is expected during config cycles */
 261        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
 262
 263        orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
 264
 265        /* disable master abort reporting */
 266        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
 267
 268        /* clear error bits */
 269        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
 270
 271        if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
 272                debugf3("%s(): failed edac_pci_add_device()\n", __func__);
 273                goto err;
 274        }
 275
 276        if (edac_op_state == EDAC_OPSTATE_INT) {
 277                pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 278                res = devm_request_irq(&op->dev, pdata->irq,
 279                                       mpc85xx_pci_isr, IRQF_DISABLED,
 280                                       "[EDAC] PCI err", pci);
 281                if (res < 0) {
 282                        printk(KERN_ERR
 283                               "%s: Unable to requiest irq %d for "
 284                               "MPC85xx PCI err\n", __func__, pdata->irq);
 285                        irq_dispose_mapping(pdata->irq);
 286                        res = -ENODEV;
 287                        goto err2;
 288                }
 289
 290                printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
 291                       pdata->irq);
 292        }
 293
 294        devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
 295        debugf3("%s(): success\n", __func__);
 296        printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
 297
 298        return 0;
 299
 300err2:
 301        edac_pci_del_device(&op->dev);
 302err:
 303        edac_pci_free_ctl_info(pci);
 304        devres_release_group(&op->dev, mpc85xx_pci_err_probe);
 305        return res;
 306}
 307
 308static int mpc85xx_pci_err_remove(struct platform_device *op)
 309{
 310        struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
 311        struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 312
 313        debugf0("%s()\n", __func__);
 314
 315        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
 316                 orig_pci_err_cap_dr);
 317
 318        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
 319
 320        edac_pci_del_device(pci->dev);
 321
 322        if (edac_op_state == EDAC_OPSTATE_INT)
 323                irq_dispose_mapping(pdata->irq);
 324
 325        edac_pci_free_ctl_info(pci);
 326
 327        return 0;
 328}
 329
 330static struct of_device_id mpc85xx_pci_err_of_match[] = {
 331        {
 332         .compatible = "fsl,mpc8540-pcix",
 333         },
 334        {
 335         .compatible = "fsl,mpc8540-pci",
 336        },
 337        {},
 338};
 339MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
 340
 341static struct of_platform_driver mpc85xx_pci_err_driver = {
 342        .probe = mpc85xx_pci_err_probe,
 343        .remove = __devexit_p(mpc85xx_pci_err_remove),
 344        .driver = {
 345                .name = "mpc85xx_pci_err",
 346                .owner = THIS_MODULE,
 347                .of_match_table = mpc85xx_pci_err_of_match,
 348        },
 349};
 350
 351#endif                          /* CONFIG_PCI */
 352
 353/**************************** L2 Err device ***************************/
 354
 355/************************ L2 SYSFS parts ***********************************/
 356
 357static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
 358                                              *edac_dev, char *data)
 359{
 360        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 361        return sprintf(data, "0x%08x",
 362                       in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
 363}
 364
 365static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
 366                                              *edac_dev, char *data)
 367{
 368        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 369        return sprintf(data, "0x%08x",
 370                       in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
 371}
 372
 373static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
 374                                           *edac_dev, char *data)
 375{
 376        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 377        return sprintf(data, "0x%08x",
 378                       in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
 379}
 380
 381static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
 382                                               *edac_dev, const char *data,
 383                                               size_t count)
 384{
 385        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 386        if (isdigit(*data)) {
 387                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
 388                         simple_strtoul(data, NULL, 0));
 389                return count;
 390        }
 391        return 0;
 392}
 393
 394static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
 395                                               *edac_dev, const char *data,
 396                                               size_t count)
 397{
 398        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 399        if (isdigit(*data)) {
 400                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
 401                         simple_strtoul(data, NULL, 0));
 402                return count;
 403        }
 404        return 0;
 405}
 406
 407static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
 408                                            *edac_dev, const char *data,
 409                                            size_t count)
 410{
 411        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 412        if (isdigit(*data)) {
 413                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
 414                         simple_strtoul(data, NULL, 0));
 415                return count;
 416        }
 417        return 0;
 418}
 419
 420static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
 421        {
 422         .attr = {
 423                  .name = "inject_data_hi",
 424                  .mode = (S_IRUGO | S_IWUSR)
 425                  },
 426         .show = mpc85xx_l2_inject_data_hi_show,
 427         .store = mpc85xx_l2_inject_data_hi_store},
 428        {
 429         .attr = {
 430                  .name = "inject_data_lo",
 431                  .mode = (S_IRUGO | S_IWUSR)
 432                  },
 433         .show = mpc85xx_l2_inject_data_lo_show,
 434         .store = mpc85xx_l2_inject_data_lo_store},
 435        {
 436         .attr = {
 437                  .name = "inject_ctrl",
 438                  .mode = (S_IRUGO | S_IWUSR)
 439                  },
 440         .show = mpc85xx_l2_inject_ctrl_show,
 441         .store = mpc85xx_l2_inject_ctrl_store},
 442
 443        /* End of list */
 444        {
 445         .attr = {.name = NULL}
 446         }
 447};
 448
 449static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
 450                                            *edac_dev)
 451{
 452        edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
 453}
 454
 455/***************************** L2 ops ***********************************/
 456
 457static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
 458{
 459        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 460        u32 err_detect;
 461
 462        err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
 463
 464        if (!(err_detect & L2_EDE_MASK))
 465                return;
 466
 467        printk(KERN_ERR "ECC Error in CPU L2 cache\n");
 468        printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
 469        printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
 470               in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
 471        printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
 472               in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
 473        printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
 474               in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
 475        printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
 476               in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
 477        printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
 478               in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
 479
 480        /* clear error detect register */
 481        out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
 482
 483        if (err_detect & L2_EDE_CE_MASK)
 484                edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
 485
 486        if (err_detect & L2_EDE_UE_MASK)
 487                edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
 488}
 489
 490static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
 491{
 492        struct edac_device_ctl_info *edac_dev = dev_id;
 493        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 494        u32 err_detect;
 495
 496        err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
 497
 498        if (!(err_detect & L2_EDE_MASK))
 499                return IRQ_NONE;
 500
 501        mpc85xx_l2_check(edac_dev);
 502
 503        return IRQ_HANDLED;
 504}
 505
 506static int __devinit mpc85xx_l2_err_probe(struct platform_device *op,
 507                                          const struct of_device_id *match)
 508{
 509        struct edac_device_ctl_info *edac_dev;
 510        struct mpc85xx_l2_pdata *pdata;
 511        struct resource r;
 512        int res;
 513
 514        if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
 515                return -ENOMEM;
 516
 517        edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
 518                                              "cpu", 1, "L", 1, 2, NULL, 0,
 519                                              edac_dev_idx);
 520        if (!edac_dev) {
 521                devres_release_group(&op->dev, mpc85xx_l2_err_probe);
 522                return -ENOMEM;
 523        }
 524
 525        pdata = edac_dev->pvt_info;
 526        pdata->name = "mpc85xx_l2_err";
 527        pdata->irq = NO_IRQ;
 528        edac_dev->dev = &op->dev;
 529        dev_set_drvdata(edac_dev->dev, edac_dev);
 530        edac_dev->ctl_name = pdata->name;
 531        edac_dev->dev_name = pdata->name;
 532
 533        res = of_address_to_resource(op->dev.of_node, 0, &r);
 534        if (res) {
 535                printk(KERN_ERR "%s: Unable to get resource for "
 536                       "L2 err regs\n", __func__);
 537                goto err;
 538        }
 539
 540        /* we only need the error registers */
 541        r.start += 0xe00;
 542
 543        if (!devm_request_mem_region(&op->dev, r.start,
 544                                     r.end - r.start + 1, pdata->name)) {
 545                printk(KERN_ERR "%s: Error while requesting mem region\n",
 546                       __func__);
 547                res = -EBUSY;
 548                goto err;
 549        }
 550
 551        pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
 552        if (!pdata->l2_vbase) {
 553                printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
 554                res = -ENOMEM;
 555                goto err;
 556        }
 557
 558        out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
 559
 560        orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
 561
 562        /* clear the err_dis */
 563        out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
 564
 565        edac_dev->mod_name = EDAC_MOD_STR;
 566
 567        if (edac_op_state == EDAC_OPSTATE_POLL)
 568                edac_dev->edac_check = mpc85xx_l2_check;
 569
 570        mpc85xx_set_l2_sysfs_attributes(edac_dev);
 571
 572        pdata->edac_idx = edac_dev_idx++;
 573
 574        if (edac_device_add_device(edac_dev) > 0) {
 575                debugf3("%s(): failed edac_device_add_device()\n", __func__);
 576                goto err;
 577        }
 578
 579        if (edac_op_state == EDAC_OPSTATE_INT) {
 580                pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 581                res = devm_request_irq(&op->dev, pdata->irq,
 582                                       mpc85xx_l2_isr, IRQF_DISABLED,
 583                                       "[EDAC] L2 err", edac_dev);
 584                if (res < 0) {
 585                        printk(KERN_ERR
 586                               "%s: Unable to requiest irq %d for "
 587                               "MPC85xx L2 err\n", __func__, pdata->irq);
 588                        irq_dispose_mapping(pdata->irq);
 589                        res = -ENODEV;
 590                        goto err2;
 591                }
 592
 593                printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
 594                       pdata->irq);
 595
 596                edac_dev->op_state = OP_RUNNING_INTERRUPT;
 597
 598                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
 599        }
 600
 601        devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
 602
 603        debugf3("%s(): success\n", __func__);
 604        printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
 605
 606        return 0;
 607
 608err2:
 609        edac_device_del_device(&op->dev);
 610err:
 611        devres_release_group(&op->dev, mpc85xx_l2_err_probe);
 612        edac_device_free_ctl_info(edac_dev);
 613        return res;
 614}
 615
 616static int mpc85xx_l2_err_remove(struct platform_device *op)
 617{
 618        struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
 619        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 620
 621        debugf0("%s()\n", __func__);
 622
 623        if (edac_op_state == EDAC_OPSTATE_INT) {
 624                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
 625                irq_dispose_mapping(pdata->irq);
 626        }
 627
 628        out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
 629        edac_device_del_device(&op->dev);
 630        edac_device_free_ctl_info(edac_dev);
 631        return 0;
 632}
 633
 634static struct of_device_id mpc85xx_l2_err_of_match[] = {
 635/* deprecate the fsl,85.. forms in the future, 2.6.30? */
 636        { .compatible = "fsl,8540-l2-cache-controller", },
 637        { .compatible = "fsl,8541-l2-cache-controller", },
 638        { .compatible = "fsl,8544-l2-cache-controller", },
 639        { .compatible = "fsl,8548-l2-cache-controller", },
 640        { .compatible = "fsl,8555-l2-cache-controller", },
 641        { .compatible = "fsl,8568-l2-cache-controller", },
 642        { .compatible = "fsl,mpc8536-l2-cache-controller", },
 643        { .compatible = "fsl,mpc8540-l2-cache-controller", },
 644        { .compatible = "fsl,mpc8541-l2-cache-controller", },
 645        { .compatible = "fsl,mpc8544-l2-cache-controller", },
 646        { .compatible = "fsl,mpc8548-l2-cache-controller", },
 647        { .compatible = "fsl,mpc8555-l2-cache-controller", },
 648        { .compatible = "fsl,mpc8560-l2-cache-controller", },
 649        { .compatible = "fsl,mpc8568-l2-cache-controller", },
 650        { .compatible = "fsl,mpc8569-l2-cache-controller", },
 651        { .compatible = "fsl,mpc8572-l2-cache-controller", },
 652        { .compatible = "fsl,p1020-l2-cache-controller", },
 653        { .compatible = "fsl,p1021-l2-cache-controller", },
 654        { .compatible = "fsl,p2020-l2-cache-controller", },
 655        {},
 656};
 657MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
 658
 659static struct of_platform_driver mpc85xx_l2_err_driver = {
 660        .probe = mpc85xx_l2_err_probe,
 661        .remove = mpc85xx_l2_err_remove,
 662        .driver = {
 663                .name = "mpc85xx_l2_err",
 664                .owner = THIS_MODULE,
 665                .of_match_table = mpc85xx_l2_err_of_match,
 666        },
 667};
 668
 669/**************************** MC Err device ***************************/
 670
 671/*
 672 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
 673 * MPC8572 User's Manual.  Each line represents a syndrome bit column as a
 674 * 64-bit value, but split into an upper and lower 32-bit chunk.  The labels
 675 * below correspond to Freescale's manuals.
 676 */
 677static unsigned int ecc_table[16] = {
 678        /* MSB           LSB */
 679        /* [0:31]    [32:63] */
 680        0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
 681        0x00ff00ff, 0x00fff0ff,
 682        0x0f0f0f0f, 0x0f0fff00,
 683        0x11113333, 0x7777000f,
 684        0x22224444, 0x8888222f,
 685        0x44448888, 0xffff4441,
 686        0x8888ffff, 0x11118882,
 687        0xffff1111, 0x22221114, /* Syndrome bit 0 */
 688};
 689
 690/*
 691 * Calculate the correct ECC value for a 64-bit value specified by high:low
 692 */
 693static u8 calculate_ecc(u32 high, u32 low)
 694{
 695        u32 mask_low;
 696        u32 mask_high;
 697        int bit_cnt;
 698        u8 ecc = 0;
 699        int i;
 700        int j;
 701
 702        for (i = 0; i < 8; i++) {
 703                mask_high = ecc_table[i * 2];
 704                mask_low = ecc_table[i * 2 + 1];
 705                bit_cnt = 0;
 706
 707                for (j = 0; j < 32; j++) {
 708                        if ((mask_high >> j) & 1)
 709                                bit_cnt ^= (high >> j) & 1;
 710                        if ((mask_low >> j) & 1)
 711                                bit_cnt ^= (low >> j) & 1;
 712                }
 713
 714                ecc |= bit_cnt << i;
 715        }
 716
 717        return ecc;
 718}
 719
 720/*
 721 * Create the syndrome code which is generated if the data line specified by
 722 * 'bit' failed.  Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
 723 * User's Manual and 9-61 in the MPC8572 User's Manual.
 724 */
 725static u8 syndrome_from_bit(unsigned int bit) {
 726        int i;
 727        u8 syndrome = 0;
 728
 729        /*
 730         * Cycle through the upper or lower 32-bit portion of each value in
 731         * ecc_table depending on if 'bit' is in the upper or lower half of
 732         * 64-bit data.
 733         */
 734        for (i = bit < 32; i < 16; i += 2)
 735                syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
 736
 737        return syndrome;
 738}
 739
 740/*
 741 * Decode data and ecc syndrome to determine what went wrong
 742 * Note: This can only decode single-bit errors
 743 */
 744static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
 745                       int *bad_data_bit, int *bad_ecc_bit)
 746{
 747        int i;
 748        u8 syndrome;
 749
 750        *bad_data_bit = -1;
 751        *bad_ecc_bit = -1;
 752
 753        /*
 754         * Calculate the ECC of the captured data and XOR it with the captured
 755         * ECC to find an ECC syndrome value we can search for
 756         */
 757        syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
 758
 759        /* Check if a data line is stuck... */
 760        for (i = 0; i < 64; i++) {
 761                if (syndrome == syndrome_from_bit(i)) {
 762                        *bad_data_bit = i;
 763                        return;
 764                }
 765        }
 766
 767        /* If data is correct, check ECC bits for errors... */
 768        for (i = 0; i < 8; i++) {
 769                if ((syndrome >> i) & 0x1) {
 770                        *bad_ecc_bit = i;
 771                        return;
 772                }
 773        }
 774}
 775
 776static void mpc85xx_mc_check(struct mem_ctl_info *mci)
 777{
 778        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 779        struct csrow_info *csrow;
 780        u32 bus_width;
 781        u32 err_detect;
 782        u32 syndrome;
 783        u32 err_addr;
 784        u32 pfn;
 785        int row_index;
 786        u32 cap_high;
 787        u32 cap_low;
 788        int bad_data_bit;
 789        int bad_ecc_bit;
 790
 791        err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
 792        if (!err_detect)
 793                return;
 794
 795        mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
 796                          err_detect);
 797
 798        /* no more processing if not ECC bit errors */
 799        if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
 800                out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
 801                return;
 802        }
 803
 804        syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
 805
 806        /* Mask off appropriate bits of syndrome based on bus width */
 807        bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
 808                        DSC_DBW_MASK) ? 32 : 64;
 809        if (bus_width == 64)
 810                syndrome &= 0xff;
 811        else
 812                syndrome &= 0xffff;
 813
 814        err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
 815        pfn = err_addr >> PAGE_SHIFT;
 816
 817        for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
 818                csrow = &mci->csrows[row_index];
 819                if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
 820                        break;
 821        }
 822
 823        cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
 824        cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
 825
 826        /*
 827         * Analyze single-bit errors on 64-bit wide buses
 828         * TODO: Add support for 32-bit wide buses
 829         */
 830        if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
 831                sbe_ecc_decode(cap_high, cap_low, syndrome,
 832                                &bad_data_bit, &bad_ecc_bit);
 833
 834                if (bad_data_bit != -1)
 835                        mpc85xx_mc_printk(mci, KERN_ERR,
 836                                "Faulty Data bit: %d\n", bad_data_bit);
 837                if (bad_ecc_bit != -1)
 838                        mpc85xx_mc_printk(mci, KERN_ERR,
 839                                "Faulty ECC bit: %d\n", bad_ecc_bit);
 840
 841                mpc85xx_mc_printk(mci, KERN_ERR,
 842                        "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
 843                        cap_high ^ (1 << (bad_data_bit - 32)),
 844                        cap_low ^ (1 << bad_data_bit),
 845                        syndrome ^ (1 << bad_ecc_bit));
 846        }
 847
 848        mpc85xx_mc_printk(mci, KERN_ERR,
 849                        "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
 850                        cap_high, cap_low, syndrome);
 851        mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr);
 852        mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
 853
 854        /* we are out of range */
 855        if (row_index == mci->nr_csrows)
 856                mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
 857
 858        if (err_detect & DDR_EDE_SBE)
 859                edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
 860                                  syndrome, row_index, 0, mci->ctl_name);
 861
 862        if (err_detect & DDR_EDE_MBE)
 863                edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
 864                                  row_index, mci->ctl_name);
 865
 866        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
 867}
 868
 869static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
 870{
 871        struct mem_ctl_info *mci = dev_id;
 872        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 873        u32 err_detect;
 874
 875        err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
 876        if (!err_detect)
 877                return IRQ_NONE;
 878
 879        mpc85xx_mc_check(mci);
 880
 881        return IRQ_HANDLED;
 882}
 883
 884static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
 885{
 886        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 887        struct csrow_info *csrow;
 888        u32 sdram_ctl;
 889        u32 sdtype;
 890        enum mem_type mtype;
 891        u32 cs_bnds;
 892        int index;
 893
 894        sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
 895
 896        sdtype = sdram_ctl & DSC_SDTYPE_MASK;
 897        if (sdram_ctl & DSC_RD_EN) {
 898                switch (sdtype) {
 899                case DSC_SDTYPE_DDR:
 900                        mtype = MEM_RDDR;
 901                        break;
 902                case DSC_SDTYPE_DDR2:
 903                        mtype = MEM_RDDR2;
 904                        break;
 905                case DSC_SDTYPE_DDR3:
 906                        mtype = MEM_RDDR3;
 907                        break;
 908                default:
 909                        mtype = MEM_UNKNOWN;
 910                        break;
 911                }
 912        } else {
 913                switch (sdtype) {
 914                case DSC_SDTYPE_DDR:
 915                        mtype = MEM_DDR;
 916                        break;
 917                case DSC_SDTYPE_DDR2:
 918                        mtype = MEM_DDR2;
 919                        break;
 920                case DSC_SDTYPE_DDR3:
 921                        mtype = MEM_DDR3;
 922                        break;
 923                default:
 924                        mtype = MEM_UNKNOWN;
 925                        break;
 926                }
 927        }
 928
 929        for (index = 0; index < mci->nr_csrows; index++) {
 930                u32 start;
 931                u32 end;
 932
 933                csrow = &mci->csrows[index];
 934                cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
 935                                  (index * MPC85XX_MC_CS_BNDS_OFS));
 936
 937                start = (cs_bnds & 0xffff0000) >> 16;
 938                end   = (cs_bnds & 0x0000ffff);
 939
 940                if (start == end)
 941                        continue;       /* not populated */
 942
 943                start <<= (24 - PAGE_SHIFT);
 944                end   <<= (24 - PAGE_SHIFT);
 945                end    |= (1 << (24 - PAGE_SHIFT)) - 1;
 946
 947                csrow->first_page = start;
 948                csrow->last_page = end;
 949                csrow->nr_pages = end + 1 - start;
 950                csrow->grain = 8;
 951                csrow->mtype = mtype;
 952                csrow->dtype = DEV_UNKNOWN;
 953                if (sdram_ctl & DSC_X32_EN)
 954                        csrow->dtype = DEV_X32;
 955                csrow->edac_mode = EDAC_SECDED;
 956        }
 957}
 958
 959static int __devinit mpc85xx_mc_err_probe(struct platform_device *op,
 960                                          const struct of_device_id *match)
 961{
 962        struct mem_ctl_info *mci;
 963        struct mpc85xx_mc_pdata *pdata;
 964        struct resource r;
 965        u32 sdram_ctl;
 966        int res;
 967
 968        if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
 969                return -ENOMEM;
 970
 971        mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx);
 972        if (!mci) {
 973                devres_release_group(&op->dev, mpc85xx_mc_err_probe);
 974                return -ENOMEM;
 975        }
 976
 977        pdata = mci->pvt_info;
 978        pdata->name = "mpc85xx_mc_err";
 979        pdata->irq = NO_IRQ;
 980        mci->dev = &op->dev;
 981        pdata->edac_idx = edac_mc_idx++;
 982        dev_set_drvdata(mci->dev, mci);
 983        mci->ctl_name = pdata->name;
 984        mci->dev_name = pdata->name;
 985
 986        res = of_address_to_resource(op->dev.of_node, 0, &r);
 987        if (res) {
 988                printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
 989                       __func__);
 990                goto err;
 991        }
 992
 993        if (!devm_request_mem_region(&op->dev, r.start,
 994                                     r.end - r.start + 1, pdata->name)) {
 995                printk(KERN_ERR "%s: Error while requesting mem region\n",
 996                       __func__);
 997                res = -EBUSY;
 998                goto err;
 999        }
1000
1001        pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
1002        if (!pdata->mc_vbase) {
1003                printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
1004                res = -ENOMEM;
1005                goto err;
1006        }
1007
1008        sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
1009        if (!(sdram_ctl & DSC_ECC_EN)) {
1010                /* no ECC */
1011                printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
1012                res = -ENODEV;
1013                goto err;
1014        }
1015
1016        debugf3("%s(): init mci\n", __func__);
1017        mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1018            MEM_FLAG_DDR | MEM_FLAG_DDR2;
1019        mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1020        mci->edac_cap = EDAC_FLAG_SECDED;
1021        mci->mod_name = EDAC_MOD_STR;
1022        mci->mod_ver = MPC85XX_REVISION;
1023
1024        if (edac_op_state == EDAC_OPSTATE_POLL)
1025                mci->edac_check = mpc85xx_mc_check;
1026
1027        mci->ctl_page_to_phys = NULL;
1028
1029        mci->scrub_mode = SCRUB_SW_SRC;
1030
1031        mpc85xx_set_mc_sysfs_attributes(mci);
1032
1033        mpc85xx_init_csrows(mci);
1034
1035        /* store the original error disable bits */
1036        orig_ddr_err_disable =
1037            in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
1038        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
1039
1040        /* clear all error bits */
1041        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1042
1043        if (edac_mc_add_mc(mci)) {
1044                debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1045                goto err;
1046        }
1047
1048        if (edac_op_state == EDAC_OPSTATE_INT) {
1049                out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
1050                         DDR_EIE_MBEE | DDR_EIE_SBEE);
1051
1052                /* store the original error management threshold */
1053                orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
1054                                           MPC85XX_MC_ERR_SBE) & 0xff0000;
1055
1056                /* set threshold to 1 error per interrupt */
1057                out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
1058
1059                /* register interrupts */
1060                pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1061                res = devm_request_irq(&op->dev, pdata->irq,
1062                                       mpc85xx_mc_isr,
1063                                        IRQF_DISABLED | IRQF_SHARED,
1064                                       "[EDAC] MC err", mci);
1065                if (res < 0) {
1066                        printk(KERN_ERR "%s: Unable to request irq %d for "
1067                               "MPC85xx DRAM ERR\n", __func__, pdata->irq);
1068                        irq_dispose_mapping(pdata->irq);
1069                        res = -ENODEV;
1070                        goto err2;
1071                }
1072
1073                printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
1074                       pdata->irq);
1075        }
1076
1077        devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
1078        debugf3("%s(): success\n", __func__);
1079        printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1080
1081        return 0;
1082
1083err2:
1084        edac_mc_del_mc(&op->dev);
1085err:
1086        devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1087        edac_mc_free(mci);
1088        return res;
1089}
1090
1091static int mpc85xx_mc_err_remove(struct platform_device *op)
1092{
1093        struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1094        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1095
1096        debugf0("%s()\n", __func__);
1097
1098        if (edac_op_state == EDAC_OPSTATE_INT) {
1099                out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
1100                irq_dispose_mapping(pdata->irq);
1101        }
1102
1103        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
1104                 orig_ddr_err_disable);
1105        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
1106
1107        edac_mc_del_mc(&op->dev);
1108        edac_mc_free(mci);
1109        return 0;
1110}
1111
1112static struct of_device_id mpc85xx_mc_err_of_match[] = {
1113/* deprecate the fsl,85.. forms in the future, 2.6.30? */
1114        { .compatible = "fsl,8540-memory-controller", },
1115        { .compatible = "fsl,8541-memory-controller", },
1116        { .compatible = "fsl,8544-memory-controller", },
1117        { .compatible = "fsl,8548-memory-controller", },
1118        { .compatible = "fsl,8555-memory-controller", },
1119        { .compatible = "fsl,8568-memory-controller", },
1120        { .compatible = "fsl,mpc8536-memory-controller", },
1121        { .compatible = "fsl,mpc8540-memory-controller", },
1122        { .compatible = "fsl,mpc8541-memory-controller", },
1123        { .compatible = "fsl,mpc8544-memory-controller", },
1124        { .compatible = "fsl,mpc8548-memory-controller", },
1125        { .compatible = "fsl,mpc8555-memory-controller", },
1126        { .compatible = "fsl,mpc8560-memory-controller", },
1127        { .compatible = "fsl,mpc8568-memory-controller", },
1128        { .compatible = "fsl,mpc8569-memory-controller", },
1129        { .compatible = "fsl,mpc8572-memory-controller", },
1130        { .compatible = "fsl,mpc8349-memory-controller", },
1131        { .compatible = "fsl,p1020-memory-controller", },
1132        { .compatible = "fsl,p1021-memory-controller", },
1133        { .compatible = "fsl,p2020-memory-controller", },
1134        { .compatible = "fsl,p4080-memory-controller", },
1135        {},
1136};
1137MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
1138
1139static struct of_platform_driver mpc85xx_mc_err_driver = {
1140        .probe = mpc85xx_mc_err_probe,
1141        .remove = mpc85xx_mc_err_remove,
1142        .driver = {
1143                .name = "mpc85xx_mc_err",
1144                .owner = THIS_MODULE,
1145                .of_match_table = mpc85xx_mc_err_of_match,
1146        },
1147};
1148
1149#ifdef CONFIG_FSL_SOC_BOOKE
1150static void __init mpc85xx_mc_clear_rfxe(void *data)
1151{
1152        orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1153        mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
1154}
1155#endif
1156
1157static int __init mpc85xx_mc_init(void)
1158{
1159        int res = 0;
1160
1161        printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1162               "(C) 2006 Montavista Software\n");
1163
1164        /* make sure error reporting method is sane */
1165        switch (edac_op_state) {
1166        case EDAC_OPSTATE_POLL:
1167        case EDAC_OPSTATE_INT:
1168                break;
1169        default:
1170                edac_op_state = EDAC_OPSTATE_INT;
1171                break;
1172        }
1173
1174        res = of_register_platform_driver(&mpc85xx_mc_err_driver);
1175        if (res)
1176                printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1177
1178        res = of_register_platform_driver(&mpc85xx_l2_err_driver);
1179        if (res)
1180                printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1181
1182#ifdef CONFIG_PCI
1183        res = of_register_platform_driver(&mpc85xx_pci_err_driver);
1184        if (res)
1185                printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1186#endif
1187
1188#ifdef CONFIG_FSL_SOC_BOOKE
1189        /*
1190         * need to clear HID1[RFXE] to disable machine check int
1191         * so we can catch it
1192         */
1193        if (edac_op_state == EDAC_OPSTATE_INT)
1194                on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
1195#endif
1196
1197        return 0;
1198}
1199
1200module_init(mpc85xx_mc_init);
1201
1202#ifdef CONFIG_FSL_SOC_BOOKE
1203static void __exit mpc85xx_mc_restore_hid1(void *data)
1204{
1205        mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1206}
1207#endif
1208
1209static void __exit mpc85xx_mc_exit(void)
1210{
1211#ifdef CONFIG_FSL_SOC_BOOKE
1212        on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
1213#endif
1214#ifdef CONFIG_PCI
1215        of_unregister_platform_driver(&mpc85xx_pci_err_driver);
1216#endif
1217        of_unregister_platform_driver(&mpc85xx_l2_err_driver);
1218        of_unregister_platform_driver(&mpc85xx_mc_err_driver);
1219}
1220
1221module_exit(mpc85xx_mc_exit);
1222
1223MODULE_LICENSE("GPL");
1224MODULE_AUTHOR("Montavista Software, Inc.");
1225module_param(edac_op_state, int, 0444);
1226MODULE_PARM_DESC(edac_op_state,
1227                 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
1228