linux/drivers/parisc/dino.c
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   1/*
   2**      DINO manager
   3**
   4**      (c) Copyright 1999 Red Hat Software
   5**      (c) Copyright 1999 SuSE GmbH
   6**      (c) Copyright 1999,2000 Hewlett-Packard Company
   7**      (c) Copyright 2000 Grant Grundler
   8**      (c) Copyright 2006 Helge Deller
   9**
  10**      This program is free software; you can redistribute it and/or modify
  11**      it under the terms of the GNU General Public License as published by
  12**      the Free Software Foundation; either version 2 of the License, or
  13**      (at your option) any later version.
  14**
  15**      This module provides access to Dino PCI bus (config/IOport spaces)
  16**      and helps manage Dino IRQ lines.
  17**
  18**      Dino interrupt handling is a bit complicated.
  19**      Dino always writes to the broadcast EIR via irr0 for now.
  20**      (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
  21**      Only one processor interrupt is used for the 11 IRQ line 
  22**      inputs to dino.
  23**
  24**      The different between Built-in Dino and Card-Mode
  25**      dino is in chip initialization and pci device initialization.
  26**
  27**      Linux drivers can only use Card-Mode Dino if pci devices I/O port
  28**      BARs are configured and used by the driver. Programming MMIO address 
  29**      requires substantial knowledge of available Host I/O address ranges
  30**      is currently not supported.  Port/Config accessor functions are the
  31**      same. "BIOS" differences are handled within the existing routines.
  32*/
  33
  34/*      Changes :
  35**      2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
  36**              - added support for the integrated RS232.       
  37*/
  38
  39/*
  40** TODO: create a virtual address for each Dino HPA.
  41**       GSC code might be able to do this since IODC data tells us
  42**       how many pages are used. PCI subsystem could (must?) do this
  43**       for PCI drivers devices which implement/use MMIO registers.
  44*/
  45
  46#include <linux/delay.h>
  47#include <linux/types.h>
  48#include <linux/kernel.h>
  49#include <linux/pci.h>
  50#include <linux/init.h>
  51#include <linux/ioport.h>
  52#include <linux/slab.h>
  53#include <linux/interrupt.h>    /* for struct irqaction */
  54#include <linux/spinlock.h>     /* for spinlock_t and prototypes */
  55
  56#include <asm/pdc.h>
  57#include <asm/page.h>
  58#include <asm/system.h>
  59#include <asm/io.h>
  60#include <asm/hardware.h>
  61
  62#include "gsc.h"
  63
  64#undef DINO_DEBUG
  65
  66#ifdef DINO_DEBUG
  67#define DBG(x...) printk(x)
  68#else
  69#define DBG(x...)
  70#endif
  71
  72/*
  73** Config accessor functions only pass in the 8-bit bus number
  74** and not the 8-bit "PCI Segment" number. Each Dino will be
  75** assigned a PCI bus number based on "when" it's discovered.
  76**
  77** The "secondary" bus number is set to this before calling
  78** pci_scan_bus(). If any PPB's are present, the scan will
  79** discover them and update the "secondary" and "subordinate"
  80** fields in Dino's pci_bus structure.
  81**
  82** Changes in the configuration *will* result in a different
  83** bus number for each dino.
  84*/
  85
  86#define is_card_dino(id)        ((id)->hw_type == HPHW_A_DMA)
  87#define is_cujo(id)             ((id)->hversion == 0x682)
  88
  89#define DINO_IAR0               0x004
  90#define DINO_IODC_ADDR          0x008
  91#define DINO_IODC_DATA_0        0x008
  92#define DINO_IODC_DATA_1        0x008
  93#define DINO_IRR0               0x00C
  94#define DINO_IAR1               0x010
  95#define DINO_IRR1               0x014
  96#define DINO_IMR                0x018
  97#define DINO_IPR                0x01C
  98#define DINO_TOC_ADDR           0x020
  99#define DINO_ICR                0x024
 100#define DINO_ILR                0x028
 101#define DINO_IO_COMMAND         0x030
 102#define DINO_IO_STATUS          0x034
 103#define DINO_IO_CONTROL         0x038
 104#define DINO_IO_GSC_ERR_RESP    0x040
 105#define DINO_IO_ERR_INFO        0x044
 106#define DINO_IO_PCI_ERR_RESP    0x048
 107#define DINO_IO_FBB_EN          0x05c
 108#define DINO_IO_ADDR_EN         0x060
 109#define DINO_PCI_ADDR           0x064
 110#define DINO_CONFIG_DATA        0x068
 111#define DINO_IO_DATA            0x06c
 112#define DINO_MEM_DATA           0x070   /* Dino 3.x only */
 113#define DINO_GSC2X_CONFIG       0x7b4
 114#define DINO_GMASK              0x800
 115#define DINO_PAMR               0x804
 116#define DINO_PAPR               0x808
 117#define DINO_DAMODE             0x80c
 118#define DINO_PCICMD             0x810
 119#define DINO_PCISTS             0x814
 120#define DINO_MLTIM              0x81c
 121#define DINO_BRDG_FEAT          0x820
 122#define DINO_PCIROR             0x824
 123#define DINO_PCIWOR             0x828
 124#define DINO_TLTIM              0x830
 125
 126#define DINO_IRQS 11            /* bits 0-10 are architected */
 127#define DINO_IRR_MASK   0x5ff   /* only 10 bits are implemented */
 128#define DINO_LOCAL_IRQS (DINO_IRQS+1)
 129
 130#define DINO_MASK_IRQ(x)        (1<<(x))
 131
 132#define PCIINTA   0x001
 133#define PCIINTB   0x002
 134#define PCIINTC   0x004
 135#define PCIINTD   0x008
 136#define PCIINTE   0x010
 137#define PCIINTF   0x020
 138#define GSCEXTINT 0x040
 139/* #define xxx       0x080 - bit 7 is "default" */
 140/* #define xxx    0x100 - bit 8 not used */
 141/* #define xxx    0x200 - bit 9 not used */
 142#define RS232INT  0x400
 143
 144struct dino_device
 145{
 146        struct pci_hba_data     hba;    /* 'C' inheritance - must be first */
 147        spinlock_t              dinosaur_pen;
 148        unsigned long           txn_addr; /* EIR addr to generate interrupt */ 
 149        u32                     txn_data; /* EIR data assign to each dino */ 
 150        u32                     imr;      /* IRQ's which are enabled */ 
 151        int                     global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
 152#ifdef DINO_DEBUG
 153        unsigned int            dino_irr0; /* save most recent IRQ line stat */
 154#endif
 155};
 156
 157/* Looks nice and keeps the compiler happy */
 158#define DINO_DEV(d) ((struct dino_device *) d)
 159
 160
 161/*
 162 * Dino Configuration Space Accessor Functions
 163 */
 164
 165#define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
 166
 167/*
 168 * keep the current highest bus count to assist in allocating busses.  This
 169 * tries to keep a global bus count total so that when we discover an 
 170 * entirely new bus, it can be given a unique bus number.
 171 */
 172static int dino_current_bus = 0;
 173
 174static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
 175                int size, u32 *val)
 176{
 177        struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
 178        u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
 179        u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
 180        void __iomem *base_addr = d->hba.base_addr;
 181        unsigned long flags;
 182
 183        DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
 184                                                                        size);
 185        spin_lock_irqsave(&d->dinosaur_pen, flags);
 186
 187        /* tell HW which CFG address */
 188        __raw_writel(v, base_addr + DINO_PCI_ADDR);
 189
 190        /* generate cfg read cycle */
 191        if (size == 1) {
 192                *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
 193        } else if (size == 2) {
 194                *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
 195        } else if (size == 4) {
 196                *val = readl(base_addr + DINO_CONFIG_DATA);
 197        }
 198
 199        spin_unlock_irqrestore(&d->dinosaur_pen, flags);
 200        return 0;
 201}
 202
 203/*
 204 * Dino address stepping "feature":
 205 * When address stepping, Dino attempts to drive the bus one cycle too soon
 206 * even though the type of cycle (config vs. MMIO) might be different. 
 207 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
 208 */
 209static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
 210        int size, u32 val)
 211{
 212        struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
 213        u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
 214        u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
 215        void __iomem *base_addr = d->hba.base_addr;
 216        unsigned long flags;
 217
 218        DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
 219                                                                        size);
 220        spin_lock_irqsave(&d->dinosaur_pen, flags);
 221
 222        /* avoid address stepping feature */
 223        __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
 224        __raw_readl(base_addr + DINO_CONFIG_DATA);
 225
 226        /* tell HW which CFG address */
 227        __raw_writel(v, base_addr + DINO_PCI_ADDR);
 228        /* generate cfg read cycle */
 229        if (size == 1) {
 230                writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
 231        } else if (size == 2) {
 232                writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
 233        } else if (size == 4) {
 234                writel(val, base_addr + DINO_CONFIG_DATA);
 235        }
 236
 237        spin_unlock_irqrestore(&d->dinosaur_pen, flags);
 238        return 0;
 239}
 240
 241static struct pci_ops dino_cfg_ops = {
 242        .read =         dino_cfg_read,
 243        .write =        dino_cfg_write,
 244};
 245
 246
 247/*
 248 * Dino "I/O Port" Space Accessor Functions
 249 *
 250 * Many PCI devices don't require use of I/O port space (eg Tulip,
 251 * NCR720) since they export the same registers to both MMIO and
 252 * I/O port space.  Performance is going to stink if drivers use
 253 * I/O port instead of MMIO.
 254 */
 255
 256#define DINO_PORT_IN(type, size, mask) \
 257static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
 258{ \
 259        u##size v; \
 260        unsigned long flags; \
 261        spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
 262        /* tell HW which IO Port address */ \
 263        __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
 264        /* generate I/O PORT read cycle */ \
 265        v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
 266        spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
 267        return v; \
 268}
 269
 270DINO_PORT_IN(b,  8, 3)
 271DINO_PORT_IN(w, 16, 2)
 272DINO_PORT_IN(l, 32, 0)
 273
 274#define DINO_PORT_OUT(type, size, mask) \
 275static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
 276{ \
 277        unsigned long flags; \
 278        spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
 279        /* tell HW which IO port address */ \
 280        __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
 281        /* generate cfg write cycle */ \
 282        write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
 283        spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
 284}
 285
 286DINO_PORT_OUT(b,  8, 3)
 287DINO_PORT_OUT(w, 16, 2)
 288DINO_PORT_OUT(l, 32, 0)
 289
 290static struct pci_port_ops dino_port_ops = {
 291        .inb    = dino_in8,
 292        .inw    = dino_in16,
 293        .inl    = dino_in32,
 294        .outb   = dino_out8,
 295        .outw   = dino_out16,
 296        .outl   = dino_out32
 297};
 298
 299static void dino_mask_irq(unsigned int irq)
 300{
 301        struct dino_device *dino_dev = get_irq_chip_data(irq);
 302        int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
 303
 304        DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, irq);
 305
 306        /* Clear the matching bit in the IMR register */
 307        dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
 308        __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
 309}
 310
 311static void dino_unmask_irq(unsigned int irq)
 312{
 313        struct dino_device *dino_dev = get_irq_chip_data(irq);
 314        int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
 315        u32 tmp;
 316
 317        DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, irq);
 318
 319        /*
 320        ** clear pending IRQ bits
 321        **
 322        ** This does NOT change ILR state!
 323        ** See comment below for ILR usage.
 324        */
 325        __raw_readl(dino_dev->hba.base_addr+DINO_IPR);
 326
 327        /* set the matching bit in the IMR register */
 328        dino_dev->imr |= DINO_MASK_IRQ(local_irq);      /* used in dino_isr() */
 329        __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
 330
 331        /* Emulate "Level Triggered" Interrupt
 332        ** Basically, a driver is blowing it if the IRQ line is asserted
 333        ** while the IRQ is disabled.  But tulip.c seems to do that....
 334        ** Give 'em a kluge award and a nice round of applause!
 335        **
 336        ** The gsc_write will generate an interrupt which invokes dino_isr().
 337        ** dino_isr() will read IPR and find nothing. But then catch this
 338        ** when it also checks ILR.
 339        */
 340        tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
 341        if (tmp & DINO_MASK_IRQ(local_irq)) {
 342                DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
 343                                __func__, tmp);
 344                gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
 345        }
 346}
 347
 348static struct irq_chip dino_interrupt_type = {
 349        .name   = "GSC-PCI",
 350        .unmask = dino_unmask_irq,
 351        .mask   = dino_mask_irq,
 352};
 353
 354
 355/*
 356 * Handle a Processor interrupt generated by Dino.
 357 *
 358 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
 359 * wedging the CPU. Could be removed or made optional at some point.
 360 */
 361static irqreturn_t dino_isr(int irq, void *intr_dev)
 362{
 363        struct dino_device *dino_dev = intr_dev;
 364        u32 mask;
 365        int ilr_loop = 100;
 366
 367        /* read and acknowledge pending interrupts */
 368#ifdef DINO_DEBUG
 369        dino_dev->dino_irr0 =
 370#endif
 371        mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
 372
 373        if (mask == 0)
 374                return IRQ_NONE;
 375
 376ilr_again:
 377        do {
 378                int local_irq = __ffs(mask);
 379                int irq = dino_dev->global_irq[local_irq];
 380                DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
 381                        __func__, irq, intr_dev, mask);
 382                generic_handle_irq(irq);
 383                mask &= ~(1 << local_irq);
 384        } while (mask);
 385
 386        /* Support for level triggered IRQ lines.
 387        ** 
 388        ** Dropping this support would make this routine *much* faster.
 389        ** But since PCI requires level triggered IRQ line to share lines...
 390        ** device drivers may assume lines are level triggered (and not
 391        ** edge triggered like EISA/ISA can be).
 392        */
 393        mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
 394        if (mask) {
 395                if (--ilr_loop > 0)
 396                        goto ilr_again;
 397                printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n", 
 398                       dino_dev->hba.base_addr, mask);
 399                return IRQ_NONE;
 400        }
 401        return IRQ_HANDLED;
 402}
 403
 404static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
 405{
 406        int irq = gsc_assign_irq(&dino_interrupt_type, dino);
 407        if (irq == NO_IRQ)
 408                return;
 409
 410        *irqp = irq;
 411        dino->global_irq[local_irq] = irq;
 412}
 413
 414static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
 415{
 416        int irq;
 417        struct dino_device *dino = ctrl;
 418
 419        switch (dev->id.sversion) {
 420                case 0x00084:   irq =  8; break; /* PS/2 */
 421                case 0x0008c:   irq = 10; break; /* RS232 */
 422                case 0x00096:   irq =  8; break; /* PS/2 */
 423                default:        return;          /* Unknown */
 424        }
 425
 426        dino_assign_irq(dino, irq, &dev->irq);
 427}
 428
 429
 430/*
 431 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
 432 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
 433 */
 434static void __devinit quirk_cirrus_cardbus(struct pci_dev *dev)
 435{
 436        u8 new_irq = dev->irq - 1;
 437        printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
 438                        pci_name(dev), dev->irq, new_irq);
 439        dev->irq = new_irq;
 440}
 441DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
 442
 443
 444static void __init
 445dino_bios_init(void)
 446{
 447        DBG("dino_bios_init\n");
 448}
 449
 450/*
 451 * dino_card_setup - Set up the memory space for a Dino in card mode.
 452 * @bus: the bus under this dino
 453 *
 454 * Claim an 8MB chunk of unused IO space and call the generic PCI routines
 455 * to set up the addresses of the devices on this bus.
 456 */
 457#define _8MB 0x00800000UL
 458static void __init
 459dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
 460{
 461        int i;
 462        struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
 463        struct resource *res;
 464        char name[128];
 465        int size;
 466
 467        res = &dino_dev->hba.lmmio_space;
 468        res->flags = IORESOURCE_MEM;
 469        size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 
 470                         dev_name(bus->bridge));
 471        res->name = kmalloc(size+1, GFP_KERNEL);
 472        if(res->name)
 473                strcpy((char *)res->name, name);
 474        else
 475                res->name = dino_dev->hba.lmmio_space.name;
 476        
 477
 478        if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
 479                                F_EXTEND(0xf0000000UL) | _8MB,
 480                                F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
 481                struct list_head *ln, *tmp_ln;
 482
 483                printk(KERN_ERR "Dino: cannot attach bus %s\n",
 484                       dev_name(bus->bridge));
 485                /* kill the bus, we can't do anything with it */
 486                list_for_each_safe(ln, tmp_ln, &bus->devices) {
 487                        struct pci_dev *dev = pci_dev_b(ln);
 488
 489                        list_del(&dev->bus_list);
 490                }
 491                        
 492                return;
 493        }
 494        bus->resource[1] = res;
 495        bus->resource[0] = &(dino_dev->hba.io_space);
 496
 497        /* Now tell dino what range it has */
 498        for (i = 1; i < 31; i++) {
 499                if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
 500                        break;
 501        }
 502        DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
 503            i, res->start, base_addr + DINO_IO_ADDR_EN);
 504        __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
 505}
 506
 507static void __init
 508dino_card_fixup(struct pci_dev *dev)
 509{
 510        u32 irq_pin;
 511
 512        /*
 513        ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
 514        **         Not sure they were ever productized.
 515        **         Die here since we'll die later in dino_inb() anyway.
 516        */
 517        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 518                panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
 519        }
 520
 521        /*
 522        ** Set Latency Timer to 0xff (not a shared bus)
 523        ** Set CACHELINE_SIZE.
 524        */
 525        dino_cfg_write(dev->bus, dev->devfn, 
 526                       PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 
 527
 528        /*
 529        ** Program INT_LINE for card-mode devices.
 530        ** The cards are hardwired according to this algorithm.
 531        ** And it doesn't matter if PPB's are present or not since
 532        ** the IRQ lines bypass the PPB.
 533        **
 534        ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
 535        ** The additional "-1" adjusts for skewing the IRQ<->slot.
 536        */
 537        dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 
 538        dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
 539
 540        /* Shouldn't really need to do this but it's in case someone tries
 541        ** to bypass PCI services and look at the card themselves.
 542        */
 543        dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 
 544}
 545
 546/* The alignment contraints for PCI bridges under dino */
 547#define DINO_BRIDGE_ALIGN 0x100000
 548
 549
 550static void __init
 551dino_fixup_bus(struct pci_bus *bus)
 552{
 553        struct list_head *ln;
 554        struct pci_dev *dev;
 555        struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
 556        int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num);
 557
 558        DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n",
 559            __func__, bus, bus->secondary,
 560            bus->bridge->platform_data);
 561
 562        /* Firmware doesn't set up card-mode dino, so we have to */
 563        if (is_card_dino(&dino_dev->hba.dev->id)) {
 564                dino_card_setup(bus, dino_dev->hba.base_addr);
 565        } else if(bus->parent == NULL) {
 566                /* must have a dino above it, reparent the resources
 567                 * into the dino window */
 568                int i;
 569                struct resource *res = &dino_dev->hba.lmmio_space;
 570
 571                bus->resource[0] = &(dino_dev->hba.io_space);
 572                for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
 573                        if(res[i].flags == 0)
 574                                break;
 575                        bus->resource[i+1] = &res[i];
 576                }
 577
 578        } else if (bus->parent) {
 579                int i;
 580
 581                pci_read_bridge_bases(bus);
 582
 583
 584                for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
 585                        if((bus->self->resource[i].flags & 
 586                            (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
 587                                continue;
 588                        
 589                        if(bus->self->resource[i].flags & IORESOURCE_MEM) {
 590                                /* There's a quirk to alignment of
 591                                 * bridge memory resources: the start
 592                                 * is the alignment and start-end is
 593                                 * the size.  However, firmware will
 594                                 * have assigned start and end, so we
 595                                 * need to take this into account */
 596                                bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
 597                                bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
 598                                
 599                        }
 600                                        
 601                        DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n",
 602                            dev_name(&bus->self->dev), i,
 603                            bus->self->resource[i].start,
 604                            bus->self->resource[i].end);
 605                        WARN_ON(pci_assign_resource(bus->self, i));
 606                        DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n",
 607                            dev_name(&bus->self->dev), i,
 608                            bus->self->resource[i].start,
 609                            bus->self->resource[i].end);
 610                }
 611        }
 612
 613
 614        list_for_each(ln, &bus->devices) {
 615                int i;
 616
 617                dev = pci_dev_b(ln);
 618                if (is_card_dino(&dino_dev->hba.dev->id))
 619                        dino_card_fixup(dev);
 620
 621                /*
 622                ** P2PB's only have 2 BARs, no IRQs.
 623                ** I'd like to just ignore them for now.
 624                */
 625                if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 626                        continue;
 627
 628                /* Adjust the I/O Port space addresses */
 629                for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 630                        struct resource *res = &dev->resource[i];
 631                        if (res->flags & IORESOURCE_IO) {
 632                                res->start |= port_base;
 633                                res->end |= port_base;
 634                        }
 635#ifdef __LP64__
 636                        /* Sign Extend MMIO addresses */
 637                        else if (res->flags & IORESOURCE_MEM) {
 638                                res->start |= F_EXTEND(0UL);
 639                                res->end   |= F_EXTEND(0UL);
 640                        }
 641#endif
 642                }
 643                /* null out the ROM resource if there is one (we don't
 644                 * care about an expansion rom on parisc, since it
 645                 * usually contains (x86) bios code) */
 646                dev->resource[PCI_ROM_RESOURCE].flags = 0;
 647                                
 648                if(dev->irq == 255) {
 649
 650#define DINO_FIX_UNASSIGNED_INTERRUPTS
 651#ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
 652
 653                        /* This code tries to assign an unassigned
 654                         * interrupt.  Leave it disabled unless you
 655                         * *really* know what you're doing since the
 656                         * pin<->interrupt line mapping varies by bus
 657                         * and machine */
 658
 659                        u32 irq_pin;
 660                        
 661                        dino_cfg_read(dev->bus, dev->devfn, 
 662                                      PCI_INTERRUPT_PIN, 1, &irq_pin);
 663                        irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
 664                        printk(KERN_WARNING "Device %s has undefined IRQ, "
 665                                        "setting to %d\n", pci_name(dev), irq_pin);
 666                        dino_cfg_write(dev->bus, dev->devfn, 
 667                                       PCI_INTERRUPT_LINE, 1, irq_pin);
 668                        dino_assign_irq(dino_dev, irq_pin, &dev->irq);
 669#else
 670                        dev->irq = 65535;
 671                        printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
 672#endif
 673                } else {
 674                        /* Adjust INT_LINE for that busses region */
 675                        dino_assign_irq(dino_dev, dev->irq, &dev->irq);
 676                }
 677        }
 678}
 679
 680
 681static struct pci_bios_ops dino_bios_ops = {
 682        .init           = dino_bios_init,
 683        .fixup_bus      = dino_fixup_bus
 684};
 685
 686
 687/*
 688 *      Initialise a DINO controller chip
 689 */
 690static void __init
 691dino_card_init(struct dino_device *dino_dev)
 692{
 693        u32 brdg_feat = 0x00784e05;
 694        unsigned long status;
 695
 696        status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
 697        if (status & 0x0000ff80) {
 698                __raw_writel(0x00000005,
 699                                dino_dev->hba.base_addr+DINO_IO_COMMAND);
 700                udelay(1);
 701        }
 702
 703        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
 704        __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
 705        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
 706
 707#if 1
 708/* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
 709        /*
 710        ** PCX-L processors don't support XQL like Dino wants it.
 711        ** PCX-L2 ignore XQL signal and it doesn't matter.
 712        */
 713        brdg_feat &= ~0x4;      /* UXQL */
 714#endif
 715        __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
 716
 717        /*
 718        ** Don't enable address decoding until we know which I/O range
 719        ** currently is available from the host. Only affects MMIO
 720        ** and not I/O port space.
 721        */
 722        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
 723
 724        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
 725        __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
 726        __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
 727
 728        __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
 729        __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
 730        __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
 731
 732        /* Disable PAMR before writing PAPR */
 733        __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
 734        __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
 735        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
 736
 737        /*
 738        ** Dino ERS encourages enabling FBB (0x6f).
 739        ** We can't until we know *all* devices below us can support it.
 740        ** (Something in device configuration header tells us).
 741        */
 742        __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
 743
 744        /* Somewhere, the PCI spec says give devices 1 second
 745        ** to recover from the #RESET being de-asserted.
 746        ** Experience shows most devices only need 10ms.
 747        ** This short-cut speeds up booting significantly.
 748        */
 749        mdelay(pci_post_reset_delay);
 750}
 751
 752static int __init
 753dino_bridge_init(struct dino_device *dino_dev, const char *name)
 754{
 755        unsigned long io_addr;
 756        int result, i, count=0;
 757        struct resource *res, *prevres = NULL;
 758        /*
 759         * Decoding IO_ADDR_EN only works for Built-in Dino
 760         * since PDC has already initialized this.
 761         */
 762
 763        io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
 764        if (io_addr == 0) {
 765                printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
 766                return -ENODEV;
 767        }
 768
 769        res = &dino_dev->hba.lmmio_space;
 770        for (i = 0; i < 32; i++) {
 771                unsigned long start, end;
 772
 773                if((io_addr & (1 << i)) == 0)
 774                        continue;
 775
 776                start = F_EXTEND(0xf0000000UL) | (i << 23);
 777                end = start + 8 * 1024 * 1024 - 1;
 778
 779                DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
 780                    start, end);
 781
 782                if(prevres && prevres->end + 1 == start) {
 783                        prevres->end = end;
 784                } else {
 785                        if(count >= DINO_MAX_LMMIO_RESOURCES) {
 786                                printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
 787                                break;
 788                        }
 789                        prevres = res;
 790                        res->start = start;
 791                        res->end = end;
 792                        res->flags = IORESOURCE_MEM;
 793                        res->name = kmalloc(64, GFP_KERNEL);
 794                        if(res->name)
 795                                snprintf((char *)res->name, 64, "%s LMMIO %d",
 796                                         name, count);
 797                        res++;
 798                        count++;
 799                }
 800        }
 801
 802        res = &dino_dev->hba.lmmio_space;
 803
 804        for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
 805                if(res[i].flags == 0)
 806                        break;
 807
 808                result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
 809                if (result < 0) {
 810                        printk(KERN_ERR "%s: failed to claim PCI Bus address "
 811                               "space %d (0x%lx-0x%lx)!\n", name, i,
 812                               (unsigned long)res[i].start, (unsigned long)res[i].end);
 813                        return result;
 814                }
 815        }
 816        return 0;
 817}
 818
 819static int __init dino_common_init(struct parisc_device *dev,
 820                struct dino_device *dino_dev, const char *name)
 821{
 822        int status;
 823        u32 eim;
 824        struct gsc_irq gsc_irq;
 825        struct resource *res;
 826
 827        pcibios_register_hba(&dino_dev->hba);
 828
 829        pci_bios = &dino_bios_ops;   /* used by pci_scan_bus() */
 830        pci_port = &dino_port_ops;
 831
 832        /*
 833        ** Note: SMP systems can make use of IRR1/IAR1 registers
 834        **   But it won't buy much performance except in very
 835        **   specific applications/configurations. Note Dino
 836        **   still only has 11 IRQ input lines - just map some of them
 837        **   to a different processor.
 838        */
 839        dev->irq = gsc_alloc_irq(&gsc_irq);
 840        dino_dev->txn_addr = gsc_irq.txn_addr;
 841        dino_dev->txn_data = gsc_irq.txn_data;
 842        eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
 843
 844        /* 
 845        ** Dino needs a PA "IRQ" to get a processor's attention.
 846        ** arch/parisc/kernel/irq.c returns an EIRR bit.
 847        */
 848        if (dev->irq < 0) {
 849                printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
 850                return 1;
 851        }
 852
 853        status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
 854        if (status) {
 855                printk(KERN_WARNING "%s: request_irq() failed with %d\n", 
 856                        name, status);
 857                return 1;
 858        }
 859
 860        /* Support the serial port which is sometimes attached on built-in
 861         * Dino / Cujo chips.
 862         */
 863
 864        gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
 865
 866        /*
 867        ** This enables DINO to generate interrupts when it sees
 868        ** any of its inputs *change*. Just asserting an IRQ
 869        ** before it's enabled (ie unmasked) isn't good enough.
 870        */
 871        __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
 872
 873        /*
 874        ** Some platforms don't clear Dino's IRR0 register at boot time.
 875        ** Reading will clear it now.
 876        */
 877        __raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
 878
 879        /* allocate I/O Port resource region */
 880        res = &dino_dev->hba.io_space;
 881        if (!is_cujo(&dev->id)) {
 882                res->name = "Dino I/O Port";
 883        } else {
 884                res->name = "Cujo I/O Port";
 885        }
 886        res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
 887        res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
 888        res->flags = IORESOURCE_IO; /* do not mark it busy ! */
 889        if (request_resource(&ioport_resource, res) < 0) {
 890                printk(KERN_ERR "%s: request I/O Port region failed "
 891                       "0x%lx/%lx (hpa 0x%p)\n",
 892                       name, (unsigned long)res->start, (unsigned long)res->end,
 893                       dino_dev->hba.base_addr);
 894                return 1;
 895        }
 896
 897        return 0;
 898}
 899
 900#define CUJO_RAVEN_ADDR         F_EXTEND(0xf1000000UL)
 901#define CUJO_FIREHAWK_ADDR      F_EXTEND(0xf1604000UL)
 902#define CUJO_RAVEN_BADPAGE      0x01003000UL
 903#define CUJO_FIREHAWK_BADPAGE   0x01607000UL
 904
 905static const char *dino_vers[] = {
 906        "2.0",
 907        "2.1",
 908        "3.0",
 909        "3.1"
 910};
 911
 912static const char *cujo_vers[] = {
 913        "1.0",
 914        "2.0"
 915};
 916
 917void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
 918
 919/*
 920** Determine if dino should claim this chip (return 0) or not (return 1).
 921** If so, initialize the chip appropriately (card-mode vs bridge mode).
 922** Much of the initialization is common though.
 923*/
 924static int __init dino_probe(struct parisc_device *dev)
 925{
 926        struct dino_device *dino_dev;   // Dino specific control struct
 927        const char *version = "unknown";
 928        char *name;
 929        int is_cujo = 0;
 930        struct pci_bus *bus;
 931        unsigned long hpa = dev->hpa.start;
 932
 933        name = "Dino";
 934        if (is_card_dino(&dev->id)) {
 935                version = "3.x (card mode)";
 936        } else {
 937                if (!is_cujo(&dev->id)) {
 938                        if (dev->id.hversion_rev < 4) {
 939                                version = dino_vers[dev->id.hversion_rev];
 940                        }
 941                } else {
 942                        name = "Cujo";
 943                        is_cujo = 1;
 944                        if (dev->id.hversion_rev < 2) {
 945                                version = cujo_vers[dev->id.hversion_rev];
 946                        }
 947                }
 948        }
 949
 950        printk("%s version %s found at 0x%lx\n", name, version, hpa);
 951
 952        if (!request_mem_region(hpa, PAGE_SIZE, name)) {
 953                printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n",
 954                        hpa);
 955                return 1;
 956        }
 957
 958        /* Check for bugs */
 959        if (is_cujo && dev->id.hversion_rev == 1) {
 960#ifdef CONFIG_IOMMU_CCIO
 961                printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
 962                if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
 963                        ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
 964                } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
 965                        ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
 966                } else {
 967                        printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
 968                }
 969#endif
 970        } else if (!is_cujo && !is_card_dino(&dev->id) &&
 971                        dev->id.hversion_rev < 3) {
 972                printk(KERN_WARNING
 973"The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
 974"data corruption.  See Service Note Numbers: A4190A-01, A4191A-01.\n"
 975"Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
 976"Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
 977                        dev->id.hversion_rev);
 978/* REVISIT: why are C200/C240 listed in the README table but not
 979**   "Models affected"? Could be an omission in the original literature.
 980*/
 981        }
 982
 983        dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
 984        if (!dino_dev) {
 985                printk("dino_init_chip - couldn't alloc dino_device\n");
 986                return 1;
 987        }
 988
 989        dino_dev->hba.dev = dev;
 990        dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096);
 991        dino_dev->hba.lmmio_space_offset = 0;   /* CPU addrs == bus addrs */
 992        spin_lock_init(&dino_dev->dinosaur_pen);
 993        dino_dev->hba.iommu = ccio_get_iommu(dev);
 994
 995        if (is_card_dino(&dev->id)) {
 996                dino_card_init(dino_dev);
 997        } else {
 998                dino_bridge_init(dino_dev, name);
 999        }
1000
1001        if (dino_common_init(dev, dino_dev, name))
1002                return 1;
1003
1004        dev->dev.platform_data = dino_dev;
1005
1006        /*
1007        ** It's not used to avoid chicken/egg problems
1008        ** with configuration accessor functions.
1009        */
1010        dino_dev->hba.hba_bus = bus = pci_scan_bus_parented(&dev->dev,
1011                         dino_current_bus, &dino_cfg_ops, NULL);
1012
1013        if(bus) {
1014                /* This code *depends* on scanning being single threaded
1015                 * if it isn't, this global bus number count will fail
1016                 */
1017                dino_current_bus = bus->subordinate + 1;
1018                pci_bus_assign_resources(bus);
1019                pci_bus_add_devices(bus);
1020        } else {
1021                printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
1022                       dev_name(&dev->dev), dino_current_bus);
1023                /* increment the bus number in case of duplicates */
1024                dino_current_bus++;
1025        }
1026        return 0;
1027}
1028
1029/*
1030 * Normally, we would just test sversion.  But the Elroy PCI adapter has
1031 * the same sversion as Dino, so we have to check hversion as well.
1032 * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1033 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1034 * For card-mode Dino, most machines report an sversion of 9D.  But 715
1035 * and 725 firmware misreport it as 0x08080 for no adequately explained
1036 * reason.
1037 */
1038static struct parisc_device_id dino_tbl[] = {
1039        { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1040        { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1041        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1042        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1043        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1044        { 0, }
1045};
1046
1047static struct parisc_driver dino_driver = {
1048        .name =         "dino",
1049        .id_table =     dino_tbl,
1050        .probe =        dino_probe,
1051};
1052
1053/*
1054 * One time initialization to let the world know Dino is here.
1055 * This is the only routine which is NOT static.
1056 * Must be called exactly once before pci_init().
1057 */
1058int __init dino_init(void)
1059{
1060        register_parisc_driver(&dino_driver);
1061        return 0;
1062}
1063
1064